An FPGA Platform for Next-Generation Grating Encoders.

Among various nanometer-level displacement measurement methods, grating interferometry-based linear encoders are widely used due to their high robustness, relatively low cost, and compactness. One trend of grating encoders is multi-axis measurement capability for simultaneous precision positioning and small order error motion measurement. However, due to both lack of suitable hardware data processing platform and of a real-time displacement calculation system, meeting the requirements of real-time data processing while maintaining the nanometer order resolutions on all these axes is a challenge. To solve above-mentioned problem, in this paper we introduce a design and experimental validation of a field programmable gate array (FPGA)-cored real-time data processing platform for grating encoders. This platform includes the following functions. First, a front-end photodetector and I/V conversion analog circuit are used to realize basic analog signal filtering, while an eight-channel parallel, 16-bit precision, 200 kSPS maximum acquisition rate Analog-to-digital (ADC) is used to obtain digital signals that are easy to process. Then, an FPGA-based digital signal processing platform is implemented, which can calculate the displacement values corresponding to the phase subdivision signals in parallel and in real time at high speed. Finally, the displacement result is transferred by USB2.0 to the PC in real time through an Universal Asynchronous Receiver/Transmitter (UART) serial port to form a complete real-time displacement calculation system. The experimental results show that the system achieves real-time data processing and displacement result display while meeting the high accuracy of traditional offline data solution methods, which demonstrates the industrial potential and practicality of our absolute two-dimensional grating scale displacement measurement system.


Introduction
Grating encoders, a specific type of linear encoder, are key components for precision positioning in various industrial engineering applications. Due to their high accuracy, robustness against environmental variances, relatively low cost, and compactness, grating encoders now hold more than 75% market share among various precision positioning solutions. Depending on the measurement method, there are two trends of grating encoders; one is single axis ultra-high precision and the other is multi-axis [1][2][3][4][5][6]. For high precision applications, the diffraction beam interferometry principle is utilized. This method is also known as interference scanning, and employs a fine grating with a Sensors 2020, 20, 2266 3 of 12 subsequent structural and algorithm optimization. Thus, FPGAs are as suitable as the hardware platform to realize high-precision, high-speed, low-latency, parallelization, and large data displacement measurements [32,33]. Therefore, in this paper we present a method using FPGA to implement existing optical algorithms into the circuit structure. Using Analog-to-Digital Converters (ADCs), we process the data in parallel through the FPGA hardware platform, calculate the displacement values and transmit them to the PC in real time through the serial port to realize the real-time display of displacement measurement.
The following Section explains the principle of the grating reading head. The third section presents the design of the algorithm and FPGA circuit structure. The fourth section describes the experimental platform and the results. In Section 5, we discuss the results and compare them with traditional scale displacement calculation methods. Figure 1 shows our laboratory's optical layout of a multi-axis grating encoder, for which the real-time data processing platform was designed. It consists of a reading head and a scale grating that are mounted on a stage base and moving element, respectively, for detecting the displacement of the moving element. The scale grating is usually a two-axis one, i.e., it includes the same grating types in orthogonal directions, usually in a one-micron scale. It should be noted that, for simplicity, in this manuscript we use a one-axis grating for explanations. The one-axis grating can provide in-plane X-direction positioning and an out-of-plane Z-direction error motion detection, and this can be easily expanded to in-plane X-and Y-directions using two-axis scale gratings.

Principle
Sensors 2020, 20, x FOR PEER REVIEW 3 of 12 to implement existing optical algorithms into the circuit structure. Using Analog-to-Digital Converters (ADCs), we process the data in parallel through the FPGA hardware platform, calculate the displacement values and transmit them to the PC in real time through the serial port to realize the real-time display of displacement measurement.
The following Section explains the principle of the grating reading head. The third section presents the design of the algorithm and FPGA circuit structure. The fourth section describes the experimental platform and the results. In Section 5, we discuss the results and compare them with traditional scale displacement calculation methods. Figure 1 shows our laboratory's optical layout of a multi-axis grating encoder, for which the realtime data processing platform was designed. It consists of a reading head and a scale grating that are mounted on a stage base and moving element, respectively, for detecting the displacement of the moving element. The scale grating is usually a two-axis one, i.e., it includes the same grating types in orthogonal directions, usually in a one-micron scale. It should be noted that, for simplicity, in this manuscript we use a one-axis grating for explanations. The one-axis grating can provide in-plane Xdirection positioning and an out-of-plane Z-direction error motion detection, and this can be easily expanded to in-plane X-and Y-directions using two-axis scale gratings.  The reading head is composed of a coherent laser diode (LD) as the light source, while a grating having the same parameters with the scale grating is used as a reference and is called the reference grating. The beam from the LD is split using a polarizing beam splitter (PBS) into P-and Spolarization beams, which then propagate towards the scale and reference gratings, respectively. Between the PBS and the gratings, quarter-wave plates (QWPs) are placed with fast axis at 45° to the polarization direction. In this manner, the two sets of two first-order diffraction beams from the two gratings change their polarization states and completely pass through and are reflected by PBS1, which greatly improves the power usage. After this, the four first-order diffraction beams are projected to a four-step optical layout, where BS2 divides the diffraction beams in two halves and QWP 4 generates a 90° phase delay for the half projected onto PBS2. Mirrors 1 and 2 here are used to change propagation direction so that these optics can be reconfigured if necessary. QWPs 3 and 5 are used to change the p-and s-polarization into left-and right-circular polarization so than they can be further divided by PBSs 2 and 3. By using the four sets of interference signals with a 90° phase delay, The reading head is composed of a coherent laser diode (LD) as the light source, while a grating having the same parameters with the scale grating is used as a reference and is called the reference grating. The beam from the LD is split using a polarizing beam splitter (PBS) into P-and S-polarization beams, which then propagate towards the scale and reference gratings, respectively. Between the PBS and the gratings, quarter-wave plates (QWPs) are placed with fast axis at 45 • to the polarization direction. In this manner, the two sets of two first-order diffraction beams from the two gratings change their polarization states and completely pass through and are reflected by PBS1, which greatly improves the power usage. After this, the four first-order diffraction beams are projected to a four-step optical layout, where BS2 divides the diffraction beams in two halves and QWP 4 generates a 90 • phase delay for the half projected onto PBS2. Mirrors 1 and 2 here are used to change propagation Sensors 2020, 20, 2266 4 of 12 direction so that these optics can be reconfigured if necessary. QWPs 3 and 5 are used to change the p-and s-polarization into left-and right-circular polarization so than they can be further divided by PBSs 2 and 3. By using the four sets of interference signals with a 90 • phase delay, the DC components of the eight interference signals can be eliminated and the motion direction can be determined.

Principle
As mentioned above, the light beam generated by LD is divided into p-line and s-line polarized light through BS1, and is incident on a reference grating and a diffraction grating through a quarter wave plate. The measurement beam Us α generated at the measurement grating and the diffraction beam Ur α generated at the diffraction grating pass through the two quarter-wave plates again and converge at PBS1. After passing through BS2, a part of the diffracted beam passes through QWP4, QWP5, and PBS2 in this order and is received by the photodetector (PD) to obtain 90 • and 270 • ± 1 level interference signals.
Therefore, the intensity of the interference signal detected by PD (90 • ) and PD (270 • ) are: where Uα represents the combined light intensity. The other part of the diffracted beam passes through BS2, QWP3, and PBS3 in that order and is received by the PDs, which is considered as ±1 level interference signals at 0 • and 180 • . So, the intensities of the interference signals detected by PD (0 • ) and PD (180 • ) are: Combining Equations (5)-(8), we obtain the displacement of the scale along the X-and Z-directions, which are: − Sensors 2020, 20, 2266

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According to the above equation, it is possible to calculate the displacement of the grating in the X-direction, and the magnitude of the jitter in the Z-direction: where λ is the laser wavelength, g is the groove width of the grating, and the scale is 1 µm.

Data Processing Algorithm Design
The schematic design for the hardware platform is shown in Figure 2. First, the laser beam passes through the grating reading head sensor described above to generate eight interference signals, which are received by the PDs. Then, the analog circuit at the front end converts and converts the mA-level current signal to a V-level voltage signal. In the next step, the eight-channel analog signals are converted into digital signals by the ADC chip, which are then input to the FPGA in parallel for digital signal processing.
Sensors 2020, 20, x FOR PEER REVIEW 5 of 12 where λ is the laser wavelength, g is the groove width of the grating, and the scale is 1 μm.

Data Processing Algorithm Design
The schematic design for the hardware platform is shown in Figure 2. First, the laser beam passes through the grating reading head sensor described above to generate eight interference signals, which are received by the PDs. Then, the analog circuit at the front end converts and converts the mA-level current signal to a V-level voltage signal. In the next step, the eight-channel analog signals are converted into digital signals by the ADC chip, which are then input to the FPGA in parallel for digital signal processing. The FPGA is our core platform for algorithm implementation. The main algorithm first filters the noise-containing signals through a 32-order Finite Impulse Response (FIR) filter in order to facilitate subsequent calculations. Then, the filtered output enters the digital signal processing module, which mainly includes three steps: first, we normalize the eight-channel filtered signals to convert the unequal-amplitude signals into equal-amplitude signals. Due to errors in the manufacturing process of the reading head, the obtained signal will add a certain phase shift to the original phase. Therefore, a phase correction module is used to correct the phase shift signal to the ideal 0°, 90°, 180°, and 270° signals. Finally, arctangent phase demodulation is performed and a COordinate Rotation DIgital Computer (CORDIC) algorithm is used to calculate the true phase information. After that, the whole phase counting and scattered period calculation are performed on the existing phase information. The whole period calculation method is to count the number of peaks and the scattered phase calculation method is Equation (11), described above. The next module is Binary-Coded Decimal(BCD) transcoding, which converts hexadecimal to decimal numbers that are transmitted to the PC through a Universal Asynchronous Receiver/Transmitter (UART). This allows real-time calculation and display of the displacement.
The specific implementation block diagram is shown in Figure 3. In this paper, an AD7606 analog-to-digital conversion chip is used, and a drive algorithm is applied to implement parallel sampling of eight-phase analog signals at a sampling rate of 100 kHz with a sampling accuracy of 16 bits. We use a 32-order FIR filter to remove the noise of the sampled signal. The principle is to convolve the original signal and the filter impulse response constants. The equation is as follows: where x(n) is the input signal, h(n) is the impulse response, that is, the tap coefficient, and N is the order of the FIR filter, which means that the tap number is n + 1. In order to fully apply the advantages of FPGA in implementing the FIR algorithm, we choose a three-stage pipeline, which reduces the The FPGA is our core platform for algorithm implementation. The main algorithm first filters the noise-containing signals through a 32-order Finite Impulse Response (FIR) filter in order to facilitate subsequent calculations. Then, the filtered output enters the digital signal processing module, which mainly includes three steps: first, we normalize the eight-channel filtered signals to convert the unequal-amplitude signals into equal-amplitude signals. Due to errors in the manufacturing process of the reading head, the obtained signal will add a certain phase shift to the original phase. Therefore, a phase correction module is used to correct the phase shift signal to the ideal 0 • , 90 • , 180 • , and 270 • signals. Finally, arctangent phase demodulation is performed and a COordinate Rotation DIgital Computer (CORDIC) algorithm is used to calculate the true phase information. After that, the whole phase counting and scattered period calculation are performed on the existing phase information. The whole period calculation method is to count the number of peaks and the scattered phase calculation method is Equation (11), described above. The next module is Binary-Coded Decimal (BCD) transcoding, which converts hexadecimal to decimal numbers that are transmitted to the PC through a Universal Asynchronous Receiver/Transmitter (UART). This allows real-time calculation and display of the displacement.
The specific implementation block diagram is shown in Figure 3. In this paper, an AD7606 analog-to-digital conversion chip is used, and a drive algorithm is applied to implement parallel sampling of eight-phase analog signals at a sampling rate of 100 kHz with a sampling accuracy of 16 bits. We use a 32-order FIR filter to remove the noise of the sampled signal. The principle is to convolve the original signal and the filter impulse response constants. The equation is as follows: Sensors 2020, 20, 2266 6 of 12 where x(n) is the input signal, h(n) is the impulse response, that is, the tap coefficient, and N is the order of the FIR filter, which means that the tap number is n + 1. In order to fully apply the advantages of FPGA in implementing the FIR algorithm, we choose a three-stage pipeline, which reduces the delay and ensures the real-time performance of data calculation and demodulation. The three-stage pipeline algorithm is as follows:  The original signal is affected by the interference intensity of the optical signal and the amplification effect of the front-end analog circuit, resulting in different amplitudes. For the accuracy of subsequent calculations, we applied a normalization algorithm, implemented by first storing the eight filtered signals in parallel into the FIFO, then setting a certain depth to obtain enough useful signal data. Then, we read the data in the FIFO and determine the maximum absolute value of the filtered signal in real time. After that, all output signals are divided by the maximum absolute value.
After analyzing the normalized signals, we found that the phases of the four signals of the same interference level do not have a strict difference of 90° difference. The reason is that the grating reading head causes a phase error due to glue sticking or stress release during the installation process. This kind of error is difficult to eliminate in the process, so we implemented an algorithm on the FPGA circuit platform to correct the phase error in real time. The normalized real signal equation is as follows: ( ) 1 sin , ( ) 1 cos , Compared with the theoretical signals, as shown in Equations (5) and (6), real signals do not have exactly a 90° difference, but have a phase error, as shown in Equation (15). So, we implemented a hardware algorithm to eliminate the phase error and correct the normalized signal in real time. The required signal calculation equation is as follows: Taking SX+1 as the signal of reference, to obtain the corrected signal (SX+1)corrected, the same threestage pipeline is applied: one-stage multiplication, one-stage subtraction, and one-stage division with the IP core to implement the phase correction algorithm. The original signal is affected by the interference intensity of the optical signal and the amplification effect of the front-end analog circuit, resulting in different amplitudes. For the accuracy of subsequent calculations, we applied a normalization algorithm, implemented by first storing the eight filtered signals in parallel into the FIFO, then setting a certain depth to obtain enough useful signal data. Then, we read the data in the FIFO and determine the maximum absolute value of the filtered signal in real time. After that, all output signals are divided by the maximum absolute value.
After analyzing the normalized signals, we found that the phases of the four signals of the same interference level do not have a strict difference of 90 • difference. The reason is that the grating reading head causes a phase error due to glue sticking or stress release during the installation process. This kind of error is difficult to eliminate in the process, so we implemented an algorithm on the FPGA circuit platform to correct the phase error in real time. The normalized real signal equation is as follows: Compared with the theoretical signals, as shown in Equations (5) and (6), real signals do not have exactly a 90 • difference, but have a phase error, as shown in Equation (15). So, we implemented a hardware algorithm to eliminate the phase error and correct the normalized signal in real time. The required signal calculation equation is as follows: Sensors 2020, 20, 2266 7 of 12 Taking S X+1 as the signal of reference, to obtain the corrected signal (S X+1 ) corrected , the same three-stage pipeline is applied: one-stage multiplication, one-stage subtraction, and one-stage division with the IP core to implement the phase correction algorithm.
After obtaining the four phase-corrected signals, the arctangent values of the ±1 levels need to be calculated separately. This algorithm uses CORDIC's arctangent IP core and inputs two 16-bit sine and cosine signals. The output arctangent phase value is also 16-bit from −π to +π. Then, we use the method of threshold determination to count the peak number of the whole period of the arctangent value, determine the number of changes in the whole period caused by the scale displacement, and then apply Equation (11) to calculate the phase of the scattered period in real time. The output result is a 16-bit fixed-point number. Then the result is BCD decoded, that is, the hexadecimal is converted into a decimal number that can be displayed by PC. The classic "greater than 4 shift plus 3" algorithm is used to ensure the low delay of the decoding module in the form of a combination circuit. Finally, we designed the Universal Asynchronous Receiver/Transmitter (UART) serial port driver timing code, the baud rate and the UART frequency-divided clock, and set the parity bit to prevent slipping and errors, and transmit the result to the PC for display correctly and in real time.
The above is the main module of the FPGA hardware platform algorithm design of this paper. The Register Transfer Level (RTL) netlist structure was synthesized, and MODELSIM was used for timing simulation. Pin and timing constraints and layout were performed, and CHIPSCOPE was used to debug the chip. A signal generator was used as the waveform input to verify the correctness of the algorithm. Finally, we combined the FPGA platform, the optical platform and other units to validate the system performance.

Results
The experimental equipment and devices are shown in Figure 4. From left to right are the laser light source, the precision stage, the grating reading head, the 8-channel I/V conversion circuit, the ADC chip, and the FPGA board. The power was set to about 60 mA to excite the photodiode and generate a 660 nm laser beam to irradiate the grating reading head. When the precision stage was displaced in the X direction, eight phase difference signals were generated. The eight optical signals were received by the photodetector and the small current signal was transmitted to the I/V conversion circuit, converted into a voltage signal and amplified, followed by simple low-pass filtering. Then, the eight analog voltage signals were input to the AD7606 chip, whose 40-pin interface was connected to the FPGA development board. Finally, the calculated displacement value is transmitted to the PC through the UART interface on the board. After obtaining the four phase-corrected signals, the arctangent values of the ±1 levels need to be calculated separately. This algorithm uses CORDIC's arctangent IP core and inputs two 16-bit sine and cosine signals. The output arctangent phase value is also 16-bit from −π to +π. Then, we use the method of threshold determination to count the peak number of the whole period of the arctangent value, determine the number of changes in the whole period caused by the scale displacement, and then apply Equation (11) to calculate the phase of the scattered period in real time. The output result is a 16-bit fixed-point number. Then the result is BCD decoded, that is, the hexadecimal is converted into a decimal number that can be displayed by PC. The classic "greater than 4 shift plus 3" algorithm is used to ensure the low delay of the decoding module in the form of a combination circuit. Finally, we designed the Universal Asynchronous Receiver/Transmitter (UART) serial port driver timing code, the baud rate and the UART frequency-divided clock, and set the parity bit to prevent slipping and errors, and transmit the result to the PC for display correctly and in real time.
The above is the main module of the FPGA hardware platform algorithm design of this paper. The Register Transfer Level (RTL) netlist structure was synthesized, and MODELSIM was used for timing simulation. Pin and timing constraints and layout were performed, and CHIPSCOPE was used to debug the chip. A signal generator was used as the waveform input to verify the correctness of the algorithm. Finally, we combined the FPGA platform, the optical platform and other units to validate the system performance.

Results
The experimental equipment and devices are shown in Figure 4. From left to right are the laser light source, the precision stage, the grating reading head, the 8-channel I/V conversion circuit, the ADC chip, and the FPGA board. The power was set to about 60 mA to excite the photodiode and generate a 660 nm laser beam to irradiate the grating reading head. When the precision stage was displaced in the X direction, eight phase difference signals were generated. The eight optical signals were received by the photodetector and the small current signal was transmitted to the I/V conversion circuit, converted into a voltage signal and amplified, followed by simple low-pass filtering. Then, the eight analog voltage signals were input to the AD7606 chip, whose 40-pin interface was connected to the FPGA development board. Finally, the calculated displacement value is transmitted to the PC through the UART interface on the board. We programmed the designed algorithm file, turned on the displacement stage, power supply, analog circuit, FPGA platform, and other hardware, connected the PC and opened the serial port for experimental analysis. The results of each part are shown in Figure 5. Figure 5a shows the data chart after recording of the eight channels using the AD7606. It is clear that the original data contains some We programmed the designed algorithm file, turned on the displacement stage, power supply, analog circuit, FPGA platform, and other hardware, connected the PC and opened the serial port for experimental analysis. The results of each part are shown in Figure 5. Figure 5a shows the data chart after recording of the eight channels using the AD7606. It is clear that the original data contains some signal noise, which causes the signal itself to not be smooth, inhibiting subsequent digital signal processing. After analyzing the noise signal, we found that our useful signal frequency is from 10 Hz to 100 Hz and the noise is mainly low frequency. So we chose low pass filter so that we could get the specific parameters for FPGA by MATLAB's filter designer tool. Figure 5b shows the signal filtered by the 32-order FIR filter. Compared with Figure 5a, it can be clearly seen that the original noise is eliminated, the signal is smooth, and the effect is significant.
Sensors 2020, 20, x FOR PEER REVIEW 8 of 12 signal noise, which causes the signal itself to not be smooth, inhibiting subsequent digital signal processing. After analyzing the noise signal, we found that our useful signal frequency is from 10 Hz to 100 Hz and the noise is mainly low frequency. So we chose low pass filter so that we could get the specific parameters for FPGA by MATLAB's filter designer tool. Figure 5b shows the signal filtered by the 32-order FIR filter. Compared with Figure 5a, it can be clearly seen that the original noise is eliminated, the signal is smooth, and the effect is significant. In order to eliminate the DC component in the phase-subdivided signal, as shown in Equations (5)-(8), the original ±1 level interference signal needs to be subtracted separately to obtain four channels to be calculated using the arctangent algorithm. However, as mentioned above, since the real signal is different from the ideal signal, it is not strictly a 90° phase difference value, so phase correction is required.  In order to eliminate the DC component in the phase-subdivided signal, as shown in Equations (5)-(8), the original ±1 level interference signal needs to be subtracted separately to obtain four channels to be calculated using the arctangent algorithm. However, as mentioned above, since the real signal is different from the ideal signal, it is not strictly a 90 • phase difference value, so phase correction is required. Figure 6a is the signal before phase correction. For the +1 level signals I x+1 (0 • ) − I x+1 (180 • ) and I x+1 (90 • ) − I x+1 (270 • ), it can be seen that the phase difference basically meets the requirements, i.e., it is close to 90 • ; but for −1 level signals I x−1 (0 • ) − I x−1 (180 • ) and I x−1 (90 • ) − I x−1 (270 • ), it can be seen that the phase difference of the original signal is close to 0 • . Theoretically, the former must lead the latter by a 90 • phase difference, otherwise the accuracy of subsequent arctangent calculation will be greatly affected. Therefore, as shown in Figure 6b, phase correction is performed using Equation (16). After correction, the new (I x+1 (90 • ) − I x+1 (270 • )) corrected and (I x−1 (90 • ) − I x−1 (270 • )) corrected values are obtained. It can be seen that every two signals of the ±1 levels have a strict phase difference of 90 • . The result is consistent with the ideal waveform, and the effect is significant.
After obtaining the four corrected signals, we need to find the arctangent value of the two channels separately. We used the Xilinx CORDIC IP core to realize the arctangent algorithm. The original result range was −π~π, but in order to meet the subsequent algorithm requirements, we converted it to −π/2~π/2. The final arctangent results are shown in Figure 7 below. In order to eliminate the DC component in the phase-subdivided signal, as shown in Equations (5)-(8), the original ±1 level interference signal needs to be subtracted separately to obtain four channels to be calculated using the arctangent algorithm. However, as mentioned above, since the real signal is different from the ideal signal, it is not strictly a 90° phase difference value, so phase correction is required.  Sensors 2020, 20, x FOR PEER REVIEW 9 of 12 Figure 6a is the signal before phase correction. For the +1 level signals Ix+1(0°) − Ix+1(180°) and Ix+1(90°) − Ix+1(270°), it can be seen that the phase difference basically meets the requirements, i.e., it is close to 90°; but for −1 level signals Ix−1(0°) − Ix−1(180°) and Ix−1(90°) − Ix−1(270°), it can be seen that the phase difference of the original signal is close to 0°. Theoretically, the former must lead the latter by a 90° phase difference, otherwise the accuracy of subsequent arctangent calculation will be greatly affected. Therefore, as shown in Figure 6b, phase correction is performed using Equation (16). After correction, the new (Ix+1(90°) − Ix+1(270°))corrected and (Ix−1(90°) − Ix−1(270°))corrected values are obtained. It can be seen that every two signals of the ±1 levels have a strict phase difference of 90°. The result is consistent with the ideal waveform, and the effect is significant.
After obtaining the four corrected signals, we need to find the arctangent value of the two channels separately. We used the Xilinx CORDIC IP core to realize the arctangent algorithm. The original result range was −π ~ π, but in order to meet the subsequent algorithm requirements, we converted it to −π/2 ~ π/2. The final arctangent results are shown in Figure 7 below. After calculating the arctangent phase value of the ±1 levels interference signals, the displacement in the X-direction can be determined using Equation (11), and the displacement results are analyzed, as shown in the following Table 1: After calculating the arctangent phase value of the ±1 levels interference signals, the displacement in the X-direction can be determined using Equation (11), and the displacement results are analyzed, as shown in the following Table 1:

Discussion
In this paper, the high-speed, parallel, and erasable circuit structure of an FPGA is utilized to realize the design and implementation of a high-precision, high-speed real-time data processing platform. In view of the lack of real-time calculations in traditional scale displacement measurement platforms, the traditional offline data solution method was improved, and a substantial contribution to the practicality and industrialization of scale displacement measurement is made.
By analyzing the results and comparing the displacement accuracy between the FPGA online real-time platform and offline displacement calculation method using MATLAB, we see that the absolute error of the results obtained using the FPGA hardware platform is less than 0.006 µm, which meets the requirements of this paper. In addition, as for real-time performance, when the FPGA clock frequency is 50 MHz, the maximum delay time of the FPGA algorithm is 13 ms, which also meets the real-time requirement. If the delay must be further reduced, more advanced FPGA chips can be used to achieve a clock frequency of thousands of MHz, and the algorithm delay time can be less than 1 ms.
For our future work, we will explore achieving lower latency and higher bit accuracy using more powerful FPGA hardware platform. In addition, the core algorithm will be encapsulated, pins can be derived and optical custom IP cores will be generated, which can increase the portability and versatility of the algorithm. Furthermore, a universal circuit structure for the optical displacement platform will be designed.