A Power Amplifier with Large High-Efficiency Range for 5G Communication

This paper presents a new method to design a Doherty power amplifier (DPA) with a large, high-efficiency range for 5G communication. This is through analyzing the drain-to-source capacitance (CDS) of DPAs, and adopting appropriate impedance of the peak device. A closed design process is proposed, to design the extended efficiency range DPA based on derived theories. For validation, a DPA with large efficiency range was designed and fabricated by using two equal devices. The measured results showed that the saturated output power was between 43.4 dBm and 43.7 dBm in the target band. Around 70% saturated drain efficiency is obtained with a gain of greater than 11 dB. Moreover, the obtained drain efficiency is larger than 50% at the 10 dB power back-off, when operating at 3.5 GHz. These superior performances illustrate that the implemented DPA can be applied well in 5G communication.

using digital techniques [15,16]. However, dual-input DPAs with digital controlling techniques suffer from increased circuit complexity, and/or higher manufacturing costs.
Many efficiency range extension methods are also presented in symmetrical architecture [17][18][19][20][21][22]. In [17], a symmetrical DPA with complex impedance at the DPA combiner is demonstrated to achieve larger load modulation compared to a conventional symmetrical DPA. High efficiency over large dynamic ranges is achieved using symmetrical devices, while still maintaining full voltage and current utilization of both transistor cells. This is achieved by modifying the combiner [18]. In [19], an explicit circuit model of generalized symmetrical DPA is proposed to design DPAs with an extended high-efficiency range. A methodology is proposed for extending the high-efficiency power range of symmetrical DPAs by taking advantage of the output impedance of peaking stage [20]. Recently, a symmetrical DPA with an extended efficiency range has been presented, where the phase relationship between the carrier and peaking currents at the DPA's combiner is used to extend the dynamic load modulation range [21]. In [22], the transistor's nonlinear phase distortion architecture is used to enhance the average drain efficiency of the DPA with the proper choice of carrier and peaking PA load trajectories. In the fore-mentioned papers, current, impedance and even phase distortion are analyzed and used to enhance efficiency of DPAs by improving the design. In practical design, some methods are introduced to eliminate the influence of drain-to-source capacitance, C DS . As described in [23,24], the quasi-lumped transmission line is used to absorb C DS when designing the matching output network. In [25], the quarter-wave impedance inverter is approximated by the internal and packaged elements of transistors, together with carrier matching network. However, DPAs' theories with C DS are not analyzed and derived in detail. Unlike the above papers, in this work, we are not committed to eliminating the impact of C DS on DPA performance, although we have developed a method to use C DS to achieve a larger OBO range. In other words, the existence of C DS can be positive for expanding the OBO range through proper design. In [26], the nonlinear output capacitor of the transistor has been used to generate harmonic components, thus, improving the saturated drain efficiency. Different from [26], this work is aimed at a large range of high efficiency, including two levels of saturation and power back-off, not just the saturation level.
This paper briefly analyzes DPAs with the drain-to-source (C DS ). Adopting suitable impedance of peak device is presented to extend the high-efficiency range, which depends on the existence of the C DS . The design parameters are derived in detail for DPAs with C DS . A closed design process is proposed to design extended efficiency range DPA based on the modified theories and two equal transistors. An extended efficiency range DPA is fabricated using two identical devices. The structure of this paper is as follows: the theories of DPAs with C DS are analyzed in Section 2; the closed design process of the extended efficiency range DPA is described in detail in Section 3; simulated and measured results are analyzed in detail in Section 4; Section 5 summarizes the content of this paper.

Theory Analysis of The Proposed DPA
The traditional DPA includes a carrier PA branch and a peak PA branch. At the combiner, there is a load of R OPT /2. A transistor can be equivalent to an ideal current source. The equivalent traditional DPA topology is shown in Figure 1. There is an impedance converter line in the carrier PA branch, as shown in Figure 1. In the analysis of conventional ideal DPAs, the drain-source capacitance C DS is often ignored. In the practical design process, the drain-source capacitance C DS is usually adopted into the output matching circuits to reduce its impact on the performance of the PA.
As shown in Figure 1, we consider the current source and drain-source capacitance C DS as comprising a black box. Therefore, considering the voltage V C and current I C1 outside the black box, the analysis method of traditional DPAs is still applicable. The only difference is that conventional DPAs have an ideal current source, and the current source in this paper is with a C DS . Sensors 2020, 20, x FOR PEER REVIEW 3 of 15 As shown in Figure 1, we consider the current source and drain-source capacitance CDS as comprising a black box. Therefore, considering the voltage VC and current IC1 outside the black box, the analysis method of traditional DPAs is still applicable. The only difference is that conventional DPAs have an ideal current source, and the current source in this paper is with a CDS.
Based on Figure 1, a more general schematic diagram is shown in Figure 2. The output matching networks (OMN) and offset lines of carrier and peak PAs are represented by two ABCD transfer matrices. We will derive the design theories of DPAs with CDS using the topology shown in Figure 2. While deriving the theories of DPAs, the CDS is considered as shown in Figure 2. Based on Figure 2, the following equations can be obtained based on two-port network theories.
Then, the voltage of the carrier device, VC, and the voltage of the peak device, VP, can be derived as The carrier branch current IT and the peak branch current IT1 at the combiner can be expressed as Based on Figure 1, a more general schematic diagram is shown in Figure 2. The output matching networks (OMN) and offset lines of carrier and peak PAs are represented by two ABCD transfer matrices. We will derive the design theories of DPAs with C DS using the topology shown in Figure 2. While deriving the theories of DPAs, the C DS is considered as shown in Figure 2. As shown in Figure 1, we consider the current source and drain-source capacitance CDS as comprising a black box. Therefore, considering the voltage VC and current IC1 outside the black box, the analysis method of traditional DPAs is still applicable. The only difference is that conventional DPAs have an ideal current source, and the current source in this paper is with a CDS.
Based on Figure 1, a more general schematic diagram is shown in Figure 2. The output matching networks (OMN) and offset lines of carrier and peak PAs are represented by two ABCD transfer matrices. We will derive the design theories of DPAs with CDS using the topology shown in Figure 2. While deriving the theories of DPAs, the CDS is considered as shown in Figure 2. Based on Figure 2, the following equations can be obtained based on two-port network theories.
Then, the voltage of the carrier device, VC, and the voltage of the peak device, VP, can be derived as The carrier branch current IT and the peak branch current IT1 at the combiner can be expressed as Based on Figure 2, the following equations can be obtained based on two-port network theories.
Then, the voltage of the carrier device, V C , and the voltage of the peak device, V P , can be derived as The carrier branch current I T and the peak branch current I T1 at the combiner can be expressed as where W = The load impedance of the carrier transistor Z C can be calculated as A coefficient of β can be defined as where Z C,SAT and Z C,BACK represent the load impedance of the carrier transistor at the saturation and the OBO level, respectively.
The OBO with C DS effect included can be calculated as OBO = 10 log P OUT,SAT P OUT,BACK = 10 log (2β) where I C,SAT and I P,SAT represent the saturated current of the carrier and the peak PA, respectively.
From Equation (11), the (Z CDS −V P,SAT /I P,SAT ) (Z CDS −V C,SAT /I C,SAT ) is introduced due to the existence of C DS , which makes the OBO range more flexible in design parameters compared to OBO expression of traditional DPAs. In fact, OBO is also related to output capacitance. Furthermore, we can use different Z CDS to obtain a different OBO. Figure 3 shows the relationships between OBO, coefficient γ, frequency and capacitance. To keep the OBO larger than 6 dB, the capacitance is up to 1.4 pF. In this paper, the DPA with a large OBO range is designed at 3.5 GHz. Therefore, the appropriate capacitance value and coefficient γ can be obtained from Figure 3.
For an ideal symmetrical DPA, the saturated current of carrier transistor I C,SAT should be equal to the saturated current of peak transistor I P,SAT . Therefore, Equation (11) can be simplified as In the design of conventional DPA, the V P,SAT /I P,SAT is equal to V C,SAT /I C,SAT that is R OPT . So, the OBO range expressed in Equation (12) is the same as that of traditional DPAs.
Here, the mentioned relationships should be defined as where γ is a coefficient. Therefore, Equation (12) can be modified as From Equation (15), it is clear that the OBO would be larger than that of conventional DPAs when γ is between 0 and 1. A simple way to realize the γR OPT is to use different size transistors for the carrier and peak PA. However, choosing different transistors means asymmetric topology, which has some drawbacks as described in the introduction section. So, in this paper, the same devices in the carrier and the peak PA are used.
For an ideal symmetrical DPA, β value being 2, the OBO is calculated and plotted in Figures 4 and 5. Figure 4 shows the voltage and current of the carrier PA and peak PA. From Figures 4 and 5, the OBO value is 6 dB when γ value is 1, which is the same as that of conventional DPAs. As γ decreases, the OBO range begins to extend. When γ decreases to 0.8, the OBO can ideally reach 12 dB. This back-off range is excellent. However, it is worth noting that the saturated output power of the Sensors 2020, 20, 5581 5 of 15 peak PA will decrease when load impedance deviates from the optimal impedance R OPT . It can also be seen from Figure 5 that the drain efficiency at the saturated level is smaller than 78.5%, and the drain efficiency at the OBO level can reach 78.5%.
where IC,SAT and IP,SAT represent the saturated current of the carrier and the peak PA, respectively.
From Equation (11), the , , ⁄ , , ⁄ is introduced due to the existence of CDS, which makes the OBO range more flexible in design parameters compared to OBO expression of traditional DPAs. In fact, OBO is also related to output capacitance. Furthermore, we can use different ZCDS to obtain a different OBO. Figure 3 shows the relationships between OBO, coefficient γ, frequency and capacitance. To keep the OBO larger than 6 dB, the capacitance is up to 1.4 pF. In this paper, the DPA with a large OBO range is designed at 3.5 GHz. Therefore, the appropriate capacitance value and coefficient γ can be obtained from Figure 3. For an ideal symmetrical DPA, the saturated current of carrier transistor IC,SAT should be equal to the saturated current of peak transistor IP,SAT. Therefore, Equation (11) can be simplified as In the design of conventional DPA, the , , ⁄ is equal to , , ⁄ that is ROPT. So, the OBO range expressed in Equation (12) is the same as that of traditional DPAs.
Here, the mentioned relationships should be defined as , , where is a coefficient. Therefore, Equation (12) can be modified as From Equation (15), it is clear that the OBO would be larger than that of conventional DPAs when γ is between 0 and 1. A simple way to realize the γROPT is to use different size transistors for   The output power , of peak PA can be calculated as It can be seen that the output power is a linear function of γ. Because γ is less than 1, the output be set to γVmax. As seen from Figure 5, the current and voltage of the peak PA satisfy the desired value. It means that the saturated current of the peak PA is equal to that of the carrier PA. At the same time, the saturated voltage of the peak PA is equal to γVmax. Thus, the impedance modulation of combine node of DPA is the same as that of the symmetrical DPA. Therefore, this proposed DPA is still called a symmetrical DPA despite different output power of carrier PA and peak PA.  Figure 6 displays the impedance conversion of the DPA at the saturation and OBO level. In this paper, IT is equal to IT1 and they are in phase. In saturation, impedance at the combiner seen from the The output power P OUT,P of peak PA can be calculated as It can be seen that the output power is a linear function of γ. Because γ is less than 1, the output power of the peak PA would decline. For example, γ of 0.91 should be taken for realizing the OBO of 9 dB. At the same time, the output power of peak PA will be 10% less. Different applications would mean a different tendency. So, in practical design, compromise should be made between saturated output power and OBO.
In traditional DPAs, if matching to a different γR OPT resistance, the current of the peak PA and the carrier is usually different. Thus, the impedance modulation of combined nodes of DPA will be changed. Thereby, it becomes an asymmetrical DPA. In this paper the same transistor is used, however, the optimal load impedance of the peak PA is set to γR OPT . In order to ensure that the saturated current of the peak PA and the carrier PA is consistent, the voltage of the peak PA should be set to γV max . As seen from Figure 5, the current and voltage of the peak PA satisfy the desired value. It means that the saturated current of the peak PA is equal to that of the carrier PA. At the same time, the saturated voltage of the peak PA is equal to γV max . Thus, the impedance modulation of combine node of DPA is the same as that of the symmetrical DPA. Therefore, this proposed DPA is still called a symmetrical DPA despite different output power of carrier PA and peak PA. Figure 6 displays the impedance conversion of the DPA at the saturation and OBO level. In this paper, I T is equal to I T1 and they are in phase. In saturation, impedance at the combiner seen from the carrier branch is 2Z L , and the load impedance Z C of the carrier transistor is R OPT . The 2Z L is transformed to Z C by using the (OMN) C and the C DS . At the OBO level, the impedance at the combiner seen from the carrier branch is Z L , and the load impedance Z C of the carrier transistor is βR OPT . The Z L is also transformed to βR OPT by using the (OMN) C and the C DS . The impedance at the combiner seen from the peak branch is 2Z L , and the load impedance Z P of the peak transistor is γR OPT in saturation. The 2Z L is transformed to R OPT by using the (OMN) P and the C DS . At the OBO level, the peak transistor is off, where the impedance Z P is infinite. The impedance at the combiner seen from the peak branch is also ∞. This impedance conversion is also achieved by using the (OMN) P and the C DS . seen from the carrier branch is ZL, and the load impedance ZC of the carrier transistor is βROPT. The ZL is also transformed to βROPT by using the (OMN)C and the CDS. The impedance at the combiner seen from the peak branch is 2ZL, and the load impedance ZP of the peak transistor is γROPT in saturation. The 2ZL is transformed to ROPT by using the (OMN)P and the CDS. At the OBO level, the peak transistor is off, where the impedance ZP is infinite. The impedance at the combiner seen from the peak branch is also ∞. This impedance conversion is also achieved by using the (OMN)P and the CDS. Figure 6. Impedance conversion of the DPA.

Design of the Proposed DPA
In this section, a closed method is presented in detail to design the extended efficiency range symmetrical DPA based on the above-mentioned theories. In order to validate the proposed method, a DPA with extended efficiency range was designed using CGH40010F GaN HEMT, based on Rogers R4350B substrate. The drain voltage Vds was set at 28 V. The gate voltage of the carrier PA Vgs1 was −2.8 V and the gate voltage of the peak PA Vgs2 was −5.7 V. The optimum load impedance ROPT is determined as 32 Ω for CGH40010F considering Vknee. Load-pull simulation should be processed in the ADS software to obtain the optimized load impedance ZOPT at the package plane, for deriving package parameters. Fortunately, the package parameters of CGH40010F can be found from [27], Combining the impedance conversion with Equations (1)-(10), the (OMN) C and (OMN) P parameters can be derived as

Design of the Proposed DPA
In this section, a closed method is presented in detail to design the extended efficiency range symmetrical DPA based on the above-mentioned theories. In order to validate the proposed method, a DPA with extended efficiency range was designed using CGH40010F GaN HEMT, based on Rogers R4350B substrate. The drain voltage V ds was set at 28 V. The gate voltage of the carrier PA V gs1 was −2.8 V and the gate voltage of the peak PA V gs2 was −5.7 V. The optimum load impedance R OPT is determined as 32 Ω for CGH40010F considering V knee . Load-pull simulation should be processed in the ADS software to obtain the optimized load impedance Z OPT at the package plane, for deriving package parameters. Fortunately, the package parameters of CGH40010F can be found from [27], shown in Figure 7. As shown in Figure 7, the package parameters are included for consideration in the practical design process. shown in Figure 7. As shown in Figure 7, the package parameters are included for consideration in the practical design process.
Package plane Figure 7. PA branch topology with device parameters.

Output Matching Network Design
The design process of output circuit network can be represented in Figure 8. Firstly, the OBO should be determined; in this work, a 10 dB OBO was chosen. Then, load

Output Matching Network Design
The design process of output circuit network can be represented in Figure 8. and TL2 should be added to eliminate the package influence on accuracy of OMN, owing to the fact that ABCD transfer matrices of OMN are derived including CDS, and excluding package parameters. By selecting and optimizing the appropriate impedance and electrical length of the microstrip lines TL1 and TL2, the parasitic parameters can effectively be cancelled. Figure 9 shows the simulated value of impedances ZOPT1 and ZOPT2 that are labeled in Figure 7. It can be seen from Figure 9 that ZOPT1 and ZOPT2 have no large deviations. It confirms that the parasitic parameters are effectively eliminated by using microstrip lines TL1 and TL2. Then, the parameters value of (OMN)C and (OMN)P can be calculated based on Equations (17)- (24). The designed (OMN)C and (OMN)P based on the obtained values are shown in Figure 10.  Firstly, the OBO should be determined; in this work, a 10 dB OBO was chosen. Then, load impedance R OPT , γR OPT of carrier and peak device can be calculated using Equation (15), respectively. The value of γ was 0.85. The load impedance at the combine node Z L should be set, and was determined as 15·(1 + 0.9) Ω. Thirdly, load-pull simulation should be used to derive the C DS and the package parameters of transistor. In this work, a general transistor CGH40010F was taken, and its parameters have been reported in previous papers. So, this step can be omitted. Micro-strip line TL1 and TL2 should be added to eliminate the package influence on accuracy of OMN, owing to the fact that ABCD transfer matrices of OMN are derived including C DS , and excluding package parameters. By selecting and optimizing the appropriate impedance and electrical length of the microstrip lines TL1 and TL2, the parasitic parameters can effectively be cancelled. Figure 9 shows the simulated value of impedances Z OPT1 and Z OPT2 that are labeled in Figure 7. It can be seen from Figure 9 that Z OPT1 and Z OPT2 have no large deviations. It confirms that the parasitic parameters are effectively eliminated by using microstrip lines TL1 and TL2. Then, the parameters value of (OMN) C and (OMN) P can be calculated based on Equations (17)- (24). The designed (OMN) C and (OMN) P based on the obtained values are shown in Figure 10.

Input Matching Network Design
Stepped impedance matching technique is used to synthesize suitable input matching networks and provide a targeted saturation gain of around 10 dB. A resistor R was added to the gate dc bias circuit to ensure the stability of both transistors. Before the input matching networks of PAs, a 3-dB Wilkinson divider was first employed to split the signal. Offset lines were also added in the input networks, to ensure that the signals of the carrier and peak branches were in phase at the combine node. Its circuit schematic is also shown in Figure 10.

Post Matching Network Design and DPA Overall Circuit Optimization
As mentioned before, the load impedance ZL was set to be 15·(1 + 0.9) Ω. Post-matching circuits should be designed to enable the load impedance to be matched to the 50 Ω standard. After all networks were designed, these circuits were combined into a completed DPA. The circuit of distributed parameters was as shown in Figure 10. In this paper, optimization was done in the Advanced Design System (ADS) software to improve performance. Simulated results are plotted in

Input Matching Network Design
Stepped impedance matching technique is used to synthesize suitable input matching networks and provide a targeted saturation gain of around 10 dB. A resistor R was added to the gate dc bias circuit to ensure the stability of both transistors. Before the input matching networks of PAs, a 3-dB Wilkinson divider was first employed to split the signal. Offset lines were also added in the input networks, to ensure that the signals of the carrier and peak branches were in phase at the combine node. Its circuit schematic is also shown in Figure 10.

Post Matching Network Design and DPA Overall Circuit Optimization
As mentioned before, the load impedance ZL was set to be 15·(1 + 0.9) Ω. Post-matching circuits should be designed to enable the load impedance to be matched to the 50 Ω standard. After all networks were designed, these circuits were combined into a completed DPA. The circuit of distributed parameters was as shown in Figure 10. In this paper, optimization was done in the Advanced Design System (ADS) software to improve performance. Simulated results are plotted in

Input Matching Network Design
Stepped impedance matching technique is used to synthesize suitable input matching networks and provide a targeted saturation gain of around 10 dB. A resistor R was added to the gate dc bias circuit to ensure the stability of both transistors. Before the input matching networks of PAs, a 3-dB Wilkinson divider was first employed to split the signal. Offset lines were also added in the input networks, to ensure that the signals of the carrier and peak branches were in phase at the combine node. Its circuit schematic is also shown in Figure 10.

Post Matching Network Design and DPA Overall Circuit Optimization
As mentioned before, the load impedance Z L was set to be 15·(1 + 0.9) Ω. Post-matching circuits should be designed to enable the load impedance to be matched to the 50 Ω standard. After all networks were designed, these circuits were combined into a completed DPA. The circuit of distributed parameters was as shown in Figure 10. In this paper, optimization was done in the Advanced Design System (ADS) software to improve performance. Simulated results are plotted in Figures 11  and 12. Figure 11a,b display the drain efficiency versus output power for the proposed DPA and the conventional DPA at 3.4 GHz, 3.5 GHz, and 3.6 GHz, respectively.  Figure 11a,b show that the proposed DPA with load impedance 0.85 ROPT of peak PA has a larger OBO compared to that of the conventional DPAs with load impedance ROPT of the peak PA. This verifies the effectiveness of the proposed method. It also can be seen from Figure 11a that around 55% drain efficiency can be obtained at the 11 dB power back-off. Regarding saturated output power and drain efficiency, these are reduced by about 13% compared with that of conventional DPAs as shown in Figure 12. These simulated performances of the DPA validate the previously described theories. 0.85 ROPT of peak PA is selected, to sacrifice a certain amount of output power and efficiency in the saturation state in exchange for larger OBO. Figure 13 shows the simulated impedance traces that are consistent with the theories. As shown in Figure 13, in saturation, the load impedance of the peak PA is about 0.85 ROPT, which is close to the theoretical value. The load modulation trajectories of the carrier PA also illustrate a larger OBO range compared to that of traditional DPAs. The load modulation trajectories of the proposed DPA are closer to the real axis, which means higher efficiency can be achieved, compared to that of the traditional DPA.  Figure 11a,b show that the proposed DPA with load impedance 0.85 ROPT of peak PA has a larger OBO compared to that of the conventional DPAs with load impedance ROPT of the peak PA. This verifies the effectiveness of the proposed method. It also can be seen from Figure 11a that around 55% drain efficiency can be obtained at the 11 dB power back-off. Regarding saturated output power and drain efficiency, these are reduced by about 13% compared with that of conventional DPAs as shown in Figure 12. These simulated performances of the DPA validate the previously described theories. 0.85 ROPT of peak PA is selected, to sacrifice a certain amount of output power and efficiency in the saturation state in exchange for larger OBO. Figure 13 shows the simulated impedance traces that are consistent with the theories. As shown in Figure 13, in saturation, the load impedance of the peak PA is about 0.85 ROPT, which is close to the theoretical value. The load modulation trajectories of the carrier PA also illustrate a larger OBO range compared to that of traditional DPAs. The load modulation trajectories of the proposed DPA are closer to the real axis, which means higher efficiency can be achieved, compared to that of the traditional DPA.  Figure 11a,b show that the proposed DPA with load impedance 0.85 R OPT of peak PA has a larger OBO compared to that of the conventional DPAs with load impedance R OPT of the peak PA. This verifies the effectiveness of the proposed method. It also can be seen from Figure 11a that around 55% drain efficiency can be obtained at the 11 dB power back-off. Regarding saturated output power and drain efficiency, these are reduced by about 13% compared with that of conventional DPAs as shown in Figure 12. These simulated performances of the DPA validate the previously described theories. 0.85 R OPT of peak PA is selected, to sacrifice a certain amount of output power and efficiency in the saturation state in exchange for larger OBO. Figure 13 shows the simulated impedance traces that are consistent with the theories. As shown in Figure 13, in saturation, the load impedance of the peak PA is about 0.85 R OPT , which is close to the theoretical value. The load modulation trajectories of the carrier PA also illustrate a larger OBO range compared to that of traditional DPAs. The load modulation trajectories of the proposed DPA are closer to the real axis, which means higher efficiency can be achieved, compared to that of the traditional DPA.

Experiment and Results Analysis
In order to demonstrate the actual performance of the designed DPA circuit, a DPA was fabricated based on the circuit schematic designed in the previous section. Figure 14 is a photograph of the fabricated DPA. The small signal characteristics S-parameter are firstly tested. The simulated and measured S-parameters are plotted in Figure 15.

Continuous Wave Testing
Performances of the designed DPA were tested using continuous wave signals. Measured output power, drain efficiency and gain are plotted in Figures 16 and 17. Seen from Figure 16, it can

Experiment and Results Analysis
In order to demonstrate the actual performance of the designed DPA circuit, a DPA was fabricated based on the circuit schematic designed in the previous section. Figure 14 is a photograph of the fabricated DPA. The small signal characteristics S-parameter are firstly tested. The simulated and measured S-parameters are plotted in Figure 15.

Experiment and Results Analysis
In order to demonstrate the actual performance of the designed DPA circuit, a DPA was fabricated based on the circuit schematic designed in the previous section. Figure 14 is a photograph of the fabricated DPA. The small signal characteristics S-parameter are firstly tested. The simulated and measured S-parameters are plotted in Figure 15.

Continuous Wave Testing
Performances of the designed DPA were tested using continuous wave signals. Measured output power, drain efficiency and gain are plotted in Figures 16 and 17. Seen from Figure 16, it can

Experiment and Results Analysis
In order to demonstrate the actual performance of the designed DPA circuit, a DPA was fabricated based on the circuit schematic designed in the previous section. Figure 14 is a photograph of the fabricated DPA. The small signal characteristics S-parameter are firstly tested. The simulated and measured S-parameters are plotted in Figure 15.

Continuous Wave Testing
Performances of the designed DPA were tested using continuous wave signals. Measured output power, drain efficiency and gain are plotted in Figures 16 and 17. Seen from Figure 16, it can

Continuous Wave Testing
Performances of the designed DPA were tested using continuous wave signals. Measured output power, drain efficiency and gain are plotted in Figures 16 and 17. Seen from Figure 16, it can be observed that the saturated output power is 43.4-43.7 dBm, and the saturated drain efficiency is 70.5-70.8% in the frequency range of 3.4-3.6 GHz, while gain is between 10.7 dB and 10 dB. Figure 17 shows that drain efficiency at the 6 dB power back-off is 62.4-64.3%. At the 10 dB power back-off, drain efficiency can be larger than 50% (50.3-52.6%).
Sensors 2020, 20, x FOR PEER REVIEW 12 of 15 be observed that the saturated output power is 43.4-43.7 dBm, and the saturated drain efficiency is 70.5-70.8% in the frequency range of 3.4-3.6 GHz, while gain is between 10.7 dB and 10 dB. Figure 17 shows that drain efficiency at the 6 dB power back-off is 62.4-64.3%. At the 10 dB power back-off, drain efficiency can be larger than 50% (50.3-52.6%).   In order to allow comparisons with previous reports on symmetrical extended efficiency range DPAs, Table 1 lists the performance reported in the relevant literature and the DPA designed in this paper. Except for reference [27,28], the OBO obtained by this work was larger than that of the listed papers. In fact, the drain efficiency at the OBO is a lot smaller than some listed papers, such as [17,19,21]. Compared with [27,28], the drain efficiency in this work is better than that of reference [27,28], with 10 dB OBO achieved. Moreover, it should be noted that the operating frequency is 3.5 GHz, which is higher than others reported in the literature. It is clear that the proposed DPA has higher operating frequency and OBO, making this DPA more suitable for 5G communication applications. The realized DPA has a high efficiency range of up to 10 dB, which is conducive to the wider development and application of DPAs in 5G communications. be observed that the saturated output power is 43.4-43.7 dBm, and the saturated drain efficiency is 70.5-70.8% in the frequency range of 3.4-3.6 GHz, while gain is between 10.7 dB and 10 dB. Figure 17 shows that drain efficiency at the 6 dB power back-off is 62.4-64.3%. At the 10 dB power back-off, drain efficiency can be larger than 50% (50.3-52.6%).   In order to allow comparisons with previous reports on symmetrical extended efficiency range DPAs, Table 1 lists the performance reported in the relevant literature and the DPA designed in this paper. Except for reference [27,28], the OBO obtained by this work was larger than that of the listed papers. In fact, the drain efficiency at the OBO is a lot smaller than some listed papers, such as [17,19,21]. Compared with [27,28], the drain efficiency in this work is better than that of reference [27,28], with 10 dB OBO achieved. Moreover, it should be noted that the operating frequency is 3.5 GHz, which is higher than others reported in the literature. It is clear that the proposed DPA has higher operating frequency and OBO, making this DPA more suitable for 5G communication applications. The realized DPA has a high efficiency range of up to 10 dB, which is conducive to the wider development and application of DPAs in 5G communications. In order to allow comparisons with previous reports on symmetrical extended efficiency range DPAs, Table 1 lists the performance reported in the relevant literature and the DPA designed in this paper. Except for reference [27,28], the OBO obtained by this work was larger than that of the listed papers. In fact, the drain efficiency at the OBO is a lot smaller than some listed papers, such as [17,19,21]. Compared with [27,28], the drain efficiency in this work is better than that of reference [27,28], with 10 dB OBO achieved. Moreover, it should be noted that the operating frequency is 3.5 GHz, which is higher than others reported in the literature. It is clear that the proposed DPA has higher operating frequency and OBO, making this DPA more suitable for 5G communication applications. The realized DPA has a high efficiency range of up to 10 dB, which is conducive to the wider development and application of DPAs in 5G communications.

20 MHz 9.5 dB LTE Testing
In order to characterize the linearity of the implemented DPA, the adjacent channel ratio (ACLR) was tested by using an LTE signal with a bandwidth of 20 MHz and peak-to average ratio of 9.5 dB. The measured ACLR with an average output power of 34.0 dBm is plotted in Figure 18. It can be observed that the ACLR is better than −29.4 dBc at 3.5 GHz. After adopting digital pre-distortion technology (DPD), the ACLR value is better than −53.6 dBc.

Conclusions
This paper proposes a Doherty power amplifier with a large high-efficiency range. Theories of DPAs with CDS included are derived, in which a new way was found for extending the efficiency range of DPAs, through selecting proper load impedance of the peak PA. An extended efficiency range DPA is successfully designed and fabricated by using two equal transistors based on the proposed theories. Measurement results show that the designed DPA can deliver over 43 dBm output power with drain efficiency of about 70% in saturation. Furthermore, at the 10 dB power back-off level, the drain efficiency is greater than 50%. More importantly, all these properties are obtained when the operating frequency is 3.5 GHz. These features indicate that the designed PA could be successfully applied in 5G communications in terms of operating frequency, high efficiency range, and linearity.

Conclusions
This paper proposes a Doherty power amplifier with a large high-efficiency range. Theories of DPAs with C DS included are derived, in which a new way was found for extending the efficiency range of DPAs, through selecting proper load impedance of the peak PA. An extended efficiency range DPA is successfully designed and fabricated by using two equal transistors based on the proposed theories. Measurement results show that the designed DPA can deliver over 43 dBm output power with drain efficiency of about 70% in saturation. Furthermore, at the 10 dB power back-off level, the drain efficiency is greater than 50%. More importantly, all these properties are obtained when the operating frequency is 3.5 GHz. These features indicate that the designed PA could be successfully applied in 5G communications in terms of operating frequency, high efficiency range, and linearity.