Small-Area Radiofrequency-Energy-Harvesting Integrated Circuits for Powering Wireless Sensor Networks

This study presents a radiofrequency (RF)-energy-harvesting integrated circuit (IC) for powering wireless sensor networks with a wireless transmitter with an industrial, scientific, and medical (ISM) of 915 MHz. The proposed IC comprises an RF-direct current (DC) rectifier, an over-voltage protection circuit, a low-power low-dropout (LDO) voltage regulator, and a charger control circuit. In the RF-DC rectifier circuit, a six-stage Dickson voltage multiplier circuit is used to improve the received RF signal to a DC voltage by using native MOS with a small threshold voltage. The over-voltage protection circuit is used to prevent a high-voltage breakdown phenomenon from the RF front-end circuit, particularly for near-field communication. A low-power LDO regulator is designed to provide stable voltage by using zero frequency compensation and a voltage-trimming feedback. Charging current is amplified N times by using a current mirror to rapidly and stably charge a battery in the proposed charger control circuit. The obtained results revealed that the maximum power conversion efficiency of the proposed RF-energy-harvesting IC was 40.56% at an input power of −6 dBm, an output voltage of 1.5 V, and a load of 30 kΩ. A chip area of the RF-energy-harvesting IC was 0.58 × 0.49 mm2, including input/output pads, and power consumption was 42 μW.


Introduction
Energy harvesting for supplying power to low-power electronic devices has recently become mainstream research. The lifetime of a battery can be extended using a developed self-sustainable power supply. Bito et al. designed a flexible wearable radiofrequency (RF) energy harvester for off-the-shelf two-way talk radios of 2 W using inkjet printing technology, and E-and H-field energy harvesters were verified using a light-emitting diode and microcontroller communication module [1]. Tian et al. presents an integrated solution for a flexible direct current (DC)-DC converter by embedding a flexible polyimide printed circuit board and an inductor made of flexible ferrite-polymer composite in a wire [2]. A wearable RF-energy-harvesting device, which comprises a U-shaped dipole antenna, matching network, RF-DC converter, and DC-DC converter, was presented in [3] for supplying power to smart jewelry. This design converts a 915-MHz RF signal into a constant DC output voltage of 3.1 V at an input power of −6 dBm, which is suitable for supplying power to a fitness monitor pendant RF Energy Harvesting IC The following section elucidates the circuit topology of the designed RF-energy-harvesting IC. Sections 3 and 4 present the simulated and measured results and conclusions, respectively. Figure 2 shows a functional diagram of the RF-energy-harvesting IC, which receives RF energy from the receiving antenna, and this energy charges energy storage devices. Thus, the proposed IC is used as a backup stable power source. An off-chip matching network from MuRata Manufacturing Co. Ltd. was used to guarantee maximum power transfer. The RF-DC rectifier received the transferred RF energy from a matching network and converted this energy into DC voltage. An overvoltage protection circuit was then designed to protect the RF-DC rectifier when the output voltage of the designed rectifier was higher than the breakdown voltage [19]. A stable voltage of 1.5 V is passed through the low-power LDO circuit and sent to the charging control circuit for charging storage devices such as a battery.

Matching Network
Because of an antenna impedance of 50 Ω, the input impedance of the matching network must be matched to 50 Ω. This matching circuit is used to not only guarantee maximum power transfer but also obtain maximum conversion efficiency. If the matching network includes capacitor C and inductor L, maximum power transformation is obtained from an antenna to a load. Source impedance Ra must be equal to the conjugate input impedance Zin of the matching network [20]. The maximum output power PL,max can be expressed as follows: where Va is the peak voltage of the antenna. Ia and Zin are the input current and input impedance of the matching network, respectively.
In this study, the impedance of the antenna and the input impedance of the RF-DC rectifier were 50 Ω and 240.4 -j473.9 Ω, respectively. The impedance of the matching network must be equal to 50 Ω [21]. Simulations were performed with ADS software and component datasheet provided from MuRata Company, and inductor L, labeled as LQG15HS_02, and capacitor C, labeled as GRM15, were used to complete the matching network. Moreover, authors paid more attention toward self-resonant frequencies (SRFs) for selecting a suitable inductor. The operating frequency of the matching network must be lower than the SRF of the selected inductor. The larger the inductor is, the smaller the SRF is. For example, the minimum SRFs were 1000 and 800 MHz for L ≤ 47 μH and L ≥ 56 μH, respectively. If input power was set to −10 dBm at an operating frequency of 915 MHz, a suitable inductor lower than 47 μH was selected. The following section elucidates the circuit topology of the designed RF-energy-harvesting IC. Sections 3 and 4 present the simulated and measured results and conclusions, respectively. Figure 2 shows a functional diagram of the RF-energy-harvesting IC, which receives RF energy from the receiving antenna, and this energy charges energy storage devices. Thus, the proposed IC is used as a backup stable power source. An off-chip matching network from MuRata Manufacturing Co. Ltd. was used to guarantee maximum power transfer. The RF-DC rectifier received the transferred RF energy from a matching network and converted this energy into DC voltage. An over-voltage protection circuit was then designed to protect the RF-DC rectifier when the output voltage of the designed rectifier was higher than the breakdown voltage [19]. A stable voltage of 1.5 V is passed through the low-power LDO circuit and sent to the charging control circuit for charging storage devices such as a battery.

RF-DC Rectifier
For an N-stage rectifier, a pair of a metal-oxide-semiconductor field-effect transistor [MOSFET (MP)] and capacitor (CP) can be considered as a rectifier with a small ripple voltage across Cp. An averaged output voltage of the (p + 1) th stage can be expressed as follows:

ON-Chip
Power Path

RF-DC Rectifier
For an N-stage rectifier, a pair of a metal-oxide-semiconductor field-effect transistor [MOSFET (MP)] and capacitor (CP) can be considered as a rectifier with a small ripple voltage across Cp. An averaged output voltage of the (p + 1) th stage can be expressed as follows: where VO(p), VO(p+1), and Vboost are the output voltage of the p th stage (present voltage), output voltage of the (p + 1) th stage (next voltage), and incremental voltage of each stage [22], respectively. Approximation in charge computation was used to provide the incremental voltage Vboost as follows: ⁄ Figure 2. Functional diagram of RF-energy-harvesting IC.

Matching Network
Because of an antenna impedance of 50 Ω, the input impedance of the matching network must be matched to 50 Ω. This matching circuit is used to not only guarantee maximum power transfer but also obtain maximum conversion efficiency. If the matching network includes capacitor C and inductor L, maximum power transformation is obtained from an antenna to a load. Source impedance R a must be equal to the conjugate input impedance Z in of the matching network [20]. The maximum output power P L,max can be expressed as follows: where V a is the peak voltage of the antenna. I a and Z in are the input current and input impedance of the matching network, respectively. In this study, the impedance of the antenna and the input impedance of the RF-DC rectifier were 50 Ω and 240.4 -j473.9 Ω, respectively. The impedance of the matching network must be equal to 50 Ω [21]. Simulations were performed with ADS software and component datasheet provided from MuRata Company, and inductor L, labeled as LQG15HS_02, and capacitor C, labeled as GRM15, were used to complete the matching network. Moreover, authors paid more attention toward self-resonant frequencies (SRFs) for selecting a suitable inductor. The operating frequency of the matching network must be lower than the SRF of the selected inductor. The larger the inductor is, the smaller the SRF is. For example, the minimum SRFs were 1000 and 800 MHz for L ≤ 47 µH and L ≥ 56 µH, respectively. If input power was set to −10 dBm at an operating frequency of 915 MHz, a suitable inductor lower than 47 µH was selected.

RF-DC Rectifier
For an N-stage rectifier, a pair of a metal-oxide-semiconductor field-effect transistor [MOSFET (M P )] and capacitor (C P ) can be considered as a rectifier with a small ripple voltage across C p . An averaged output voltage of the (p + 1) th stage can be expressed as follows: where V O(p) , V O(p+1), and V boost are the output voltage of the p th stage (present voltage), output voltage of the (p + 1) th stage (next voltage), and incremental voltage of each stage [22], respectively. Approximation in charge computation was used to provide the incremental voltage V boost as follows: where V' in , V tn , I' Oeff , µ n, and C ox are an effective voltage amplitude, the threshold voltage of an NMOS transistor, effective loading current, electron mobility, and a gate oxide capacitor, respectively. W and L are the width and length of the MOSFET, respectively. I' Oeff and V' in can be given as follows: where I 0 , I S0 , V T , λ sub , C t , C par , and V in are the initial loading current, saturation current, thermal voltage, channel length modulation coefficient, total capacitance value of all capacitors, parasitic capacitance at each stage, and peak amplitude of an input signal of a voltage rectifier, respectively. If the body effect is ignored, the output voltage of the N-stage rectifier is as follows: According to the simulation results, many rectifiers are used for achieving the maximum efficiency. For example, 2-, 4-, 6-, 8-, 10-, and 16-stages are designed with respect to different loading currents or peak voltages [22]. For a rapid charging mechanism and stable power source at an operating frequency of 917 MHz, this study adopted a 6-stage voltage rectifier with a small threshold voltage of 0.45 V. Figure 3 shows a single-ended 6-stage Dickson voltage multiplier, which was published in [22]. It includes 6 diode-connected MOSFETs (M 1 -M 6 ) and 6 capacitors (C 1 -C 5 and C L ). All transistors and capacitors are identical. A bottom plate, which is marked using a bold line, exhibited a large parasitic capacitance. It is grounded to reduce loss or is connected to the input terminal RF in , which is fed from the matching network. According to the simulation results, many rectifiers are used for achieving the maximum efficiency. For example, 2-, 4-, 6-, 8-, 10-, and 16-stages are designed with respect to different loading currents or peak voltages [22]. For a rapid charging mechanism and stable power source at an operating frequency of 917 MHz, this study adopted a 6-stage voltage rectifier with a small threshold voltage of 0.45 V. Figure 3 shows a single-ended 6-stage Dickson voltage multiplier, which was published in [22]. It includes 6 diode-connected MOSFETs (M1-M6) and 6 capacitors (C1-C5 and CL). All transistors and capacitors are identical. A bottom plate, which is marked using a bold line, exhibited a large parasitic capacitance. It is grounded to reduce loss or is connected to the input terminal RFin, which is fed from the matching network. If the input signal of the voltage rectifier was sinusoidal with RFin = Vincos 2πft, where Vin and f are respectively the peak amplitude and operating frequency, the DC output voltage Vdc could be obtained for a charge transfer with a load capacitor CL. The capacitor is sufficiently large to store the transferred charge and to reduce the output ripple voltage [22].
If the voltage multiplier was in a steady state, RFin was greater than or equal to zero for 0 ≤ t ≤ π/4 and 3π/4 ≤ t ≤ π, and RFin was less than or equal to zero for π/4 ≤ t ≤ 3π/4 in the first time cycle T (= 1/f). RFin charged the capacitor C1 through the MOSFET M1 for RFin ≤ 0, and a steady voltage of Vin − VTH was then stored in C1 by reducing a threshold voltage VTH. Voltage was subsequently changed to Vin + (Vin − VTH) across the capacitor C1 for RFin ≥ 0. M2 was the conducting MOSFET, and the voltage of C2 was charged to 2 × (Vin − VTH) by reducing a threshold voltage VTH of M2. In the second time cycle (2T), RFin charged the capacitor C2 to Vin + 2 × (Vin − VTH) for RFin ≤ 0, and a steady voltage of 3 × (Vin − VTH) was passed through M3 and stored in C3. For RFin ≥ 0, the voltage of C3 was abruptly changed to Vin + 3 × (Vin − VTH), and M4 was the conducting MOSFET. A steady voltage of 4 × (Vin − VTH) was generated across the capacitor C4. After the third time cycle (3T) was completed, a steady voltage of 6 × (Vin − VTH) was generated without a body effect across the load capacitor CL. The ideal output DC voltage Vdc could be expressed as follows: Equation (7) indicates that the larger the threshold voltage VTH is, the smaller the DC output voltage Vdc is. Threshold voltage VTH is highly correlational to a semiconductor process. A conventional CMOS has an inherent threshold voltage of approximately 0.45 V for the standard TSMC 0.18 process, whereas a low threshold voltage of 28 mV was obtained using a conventional MOS. The conventional MOS was used to not only develop a new RF-DC rectifier but also to enhance power efficiency, particularly for an ultra-low input power of less than −10 dBm. Figure 4 presents an over-voltage protection circuit used to prevent the occurrence of a highvoltage breakdown phenomenon during NFC [19]. The output DC voltage Vdc of the RF-DC rectifier was connected to the proposed protection circuit, and two PMOSs (M1 -M2) and two NMOSs (M8 -M9) were diode-connected. Two bias voltages VA and VB could be expressed as follows: If the input signal of the voltage rectifier was sinusoidal with RF in = V in cos 2πft, where V in and f are respectively the peak amplitude and operating frequency, the DC output voltage V dc could be obtained for a charge transfer with a load capacitor C L . The capacitor is sufficiently large to store the transferred charge and to reduce the output ripple voltage [22].

Over-Voltage Protection Circuit
If the voltage multiplier was in a steady state, RF in was greater than or equal to zero for 0 ≤ t ≤ π/4 and 3π/4 ≤ t ≤ π, and RF in was less than or equal to zero for π/4 ≤ t ≤ 3π/4 in the first time cycle T (= 1/f ). RF in charged the capacitor C 1 through the MOSFET M 1 for RF in ≤ 0, and a steady voltage of V in − V TH was then stored in C 1 by reducing a threshold voltage V TH . Voltage was subsequently changed to V in + (V in − V TH ) across the capacitor C 1 for RF in ≥ 0. M 2 was the conducting MOSFET, and the voltage of C 2 was charged to 2 × (V in − V TH ) by reducing a threshold voltage V TH of M 2 . In the second time cycle (2T), RF in charged the capacitor C 2 to V in + 2 × (V in − V TH ) for RF in ≤ 0, and a steady voltage of 3 × (V in − V TH ) was passed through M 3 and stored in C 3 . For RF in ≥ 0, the voltage of C 3 was abruptly changed to V in + 3 × (V in − V TH ), and M4 was the conducting MOSFET. A steady voltage of 4 × (V in − V TH ) was generated across the capacitor C 4 . After the third time cycle (3T) was completed, a steady voltage of 6 × (V in − V TH ) was generated without a body effect across the load capacitor C L . The ideal output DC voltage Vdc could be expressed as follows: Equation (7) indicates that the larger the threshold voltage V TH is, the smaller the DC output voltage V dc is. Threshold voltage V TH is highly correlational to a semiconductor process. A conventional CMOS has an inherent threshold voltage of approximately 0.45 V for the standard TSMC 0.18 process, whereas a low threshold voltage of 28 mV was obtained using a conventional MOS. The conventional MOS was used to not only develop a new RF-DC rectifier but also to enhance power efficiency, particularly for an ultra-low input power of less than −10 dBm. Figure 4 presents an over-voltage protection circuit used to prevent the occurrence of a high-voltage breakdown phenomenon during NFC [19]. The output DC voltage V dc of the RF-DC rectifier was connected to the proposed protection circuit, and two PMOSs (M 1 -M 2 ) and two NMOSs (M 8 -M 9 ) were diode-connected. Two bias voltages V A and V B could be expressed as follows:

Over-Voltage Protection Circuit
where V ODi , V tpi , and V tni are the overdrive voltage of the i th MOSFET, threshold voltage of the i th PMOS, and threshold voltage of the i th NMOS. Under a common-mode operation, the two bias voltages were identical (i.e., V A = V B ). The DC output voltage of the RF-DC rectifier can be expressed as follows: Furthermore, the two bias voltages V A and V B could be derived from resistors (R 1 − R 2 , R ds1 − R ds2 , and R ds8 − R ds9 ). Thus, the following can be derived: where R dsi was the conduction impedance of the i th diode-connected MOSFET, which is expressed as (g mi + g mbi ) −1 with the transistor transconductance g mi and body effect transconductance g mbi . R 1 and R 2 are constant resistors. The larger the bias current I Ri of the i th resistor is, the larger the transconductance g mi is and the smaller the conduction resistor R dsi is. If the output DC voltage V dc of the RF-DC rectifier was higher than the aforementioned voltage [Equation (11)], the bias voltage V A was larger than the bias voltage V B because of the reduced conduction impedance R dsi with the large resistor current I Ri . The difference between V A and V B was amplified, and the differential output voltage V O was used to control the conduction current I O of the output transistor M O . The larger the dc voltage V dc is, the larger the conduction current I O is. Thus, a stable DC output voltage ranged from 1.69 V to 1.76 V with an input power (P in ) ranging from −14 dBm to +10 dBm. Please note that the voltage variations of two biased voltages, V A and V B , will be suppressed in the PVT (process, supply voltage, and temperature) variation. For example, if the resistor R 1 is reduced with PVT variation, the bias current I R1 is enlarged. Then both conduction resistors, R ds1 and R ds2 , are decreased by the large bias current I R1 . As a result, three resistors, R ds1 , R ds2 and R 1 , are reduced simultaneously to suppress the impact of PVT variation.

Low-Voltage Low-Dropout Regulator
Because of an input voltage with inference and input power limitation, a low-voltage and low-power LDO regulator is required for supplying a stable and clean voltage to the next stage. The designed LDO regulator was used for regulating the output variation in the over-voltage protection circuit and for providing a stable voltage V dd of 1.5 V to the charger control circuit. Figure 5 shows the proposed low-voltage LDO regulator, which includes a reference voltage, a current source, an error amplifier, a pass transistor, a feedback network, frequency compensation, and a load. A CMOS reference voltage V ref was generated and inputted to the positive terminal (+) of an error amplifier (EA). The negative terminal (−) of the EA was connected to the feedback network. A comparison between the reference voltage V ref and a feedback value indicates that the voltage difference between the positive and negative terminals was amplified as an output voltage of the EA, which was connected to a pass transistor for providing a stable supply voltage V dd by controlling the load current flow through the pass transistor [23].  Figure 5. Proposed low-voltage LDO regulator with a reference voltage, a current source, an error amplifier, a pass transistor, a feedback network, frequency compensation, and a load. Figure 6 shows the complete circuit of the adopted CMOS reference voltage [24]. The supplied voltage Vdc could be maintained at a possible voltage of 0.7 V when all transistors operated in the subthreshold region. A compensation capacitor CC was added between the drain of MN1 and ground (GND) to improve circuit stability by increasing the phase margin. Assume that I2 = 100 × I1, WMP2 = 100 × WMP1, and WMN2 = 100 × WMN1. The voltage of node X was equal to that of node Y (i.e., VX = VY).   Figure 5. Proposed low-voltage LDO regulator with a reference voltage, a current source, an error amplifier, a pass transistor, a feedback network, frequency compensation, and a load. Figure 6 shows the complete circuit of the adopted CMOS reference voltage [24]. The supplied voltage Vdc could be maintained at a possible voltage of 0.7 V when all transistors operated in the subthreshold region. A compensation capacitor CC was added between the drain of MN1 and ground (GND) to improve circuit stability by increasing the phase margin. Assume that I2 = 100 × I1, WMP2 = 100 × WMP1, and WMN2 = 100 × WMN1. The voltage of node X was equal to that of node Y (i.e., VX = VY).  Figure 6 shows the complete circuit of the adopted CMOS reference voltage [24]. The supplied voltage V dc could be maintained at a possible voltage of 0.7 V when all transistors operated in the subthreshold region. A compensation capacitor C C was added between the drain of M N1 and ground (GND) to improve circuit stability by increasing the phase margin. Assume that I 2 = 100 × I 1 , W MP2 = 100 × W MP1 , and W MN2 = 100 × W MN1 . The voltage of node X was equal to that of node Y (i.e., V X = V Y ).
Thus, the drain-source voltage of M P2 (V DS,MP2 ) was equal to that of M P3 (V DS,MP3 ). Two bias currents (I 2 and I 3 ) were identical without channel length modulations of M P2 and M P3 . If two NMOSFETs operated in the subthreshold region, the voltage difference across the resistor R 1 is given as follows: where n and V T are the subthreshold region swing parameter and thermal voltage, respectively. The n is a constant and V T is a parameter independent of the process. Thus, process variations do not influence V R1 . V GS, MNi and (W/L) MNi are the gate-source voltage and the ratio of width to length for the transistor M Ni , respectively. Equation (13) indicates that a temperature coefficient (TC) is positive for the resistor's voltage V R1 . Voltage reference V ref can be written as follows: where V R1 and V R2 are voltage differences across resistors R 1 and R 2 , respectively, and V GS,MN2 is the gate-source voltage of the transistor M N2 with a negative TC. A positive TC was combined with a negative TC in an integrated circuit to obtain the desired reference voltage V ref with zero temperature dependence [24]. Thus, the drain-source voltage of MP2 (VDS,MP2) was equal to that of MP3 (VDS,MP3). Two bias currents (I2 and I3) were identical without channel length modulations of MP2 and MP3. If two NMOSFETs operated in the subthreshold region, the voltage difference across the resistor R1 is given as follows: where n and VT are the subthreshold region swing parameter and thermal voltage, respectively. The n is a constant and VT is a parameter independent of the process. Thus, process variations do not influence VR1. VGS, MNi and (W/L)MNi are the gate-source voltage and the ratio of width to length for the transistor MNi, respectively. Equation (13) indicates that a temperature coefficient (TC) is positive for the resistor's voltage VR1.
Voltage reference Vref can be written as follows: where VR1 and VR2 are voltage differences across resistors R1 and R2, respectively, and VGS,MN2 is the gate-source voltage of the transistor MN2 with a negative TC. A positive TC was combined with a negative TC in an integrated circuit to obtain the desired reference voltage Vref with zero temperature dependence [24].   Figure 7 shows the complete circuit of a low-voltage LDO regulator. The EA was a CMOS twostage amplifier, which was designed to regulate the supplied output voltage Vdc of the low-voltage LDO regulator by controlling the gate voltage of the pass transistor Verr. The first stage had a pchannel differential input pair with an n-channel current mirror active load for a high gain AV1. The second stage is generally configured as a simple common source stage to allow maximum output swings with gain AV2 [25]. Bias currents were copied through the current source by controlling the Figure 6. Complete circuit of the adopted CMOS reference voltage. Figure 7 shows the complete circuit of a low-voltage LDO regulator. The EA was a CMOS two-stage amplifier, which was designed to regulate the supplied output voltage V dc of the low-voltage LDO regulator by controlling the gate voltage of the pass transistor V err . The first stage had a p-channel differential input pair with an n-channel current mirror active load for a high gain A V1 . The second stage is generally configured as a simple common source stage to allow maximum output swings with gain A V2 [25]. Bias currents were copied through the current source by controlling the resistor R 3 . The voltage swing at V err was equal to V dc − |V OD,MP6 | − V OD,MN6 with overdrive voltages, V OD,MP6 and V OD,MN6 , of MP6 and MN6, respectively. The overall voltage gain A V can be derived as follows: where g m,MPi and r ds,MPi are the transconductance and conduction resistance of the i th PMOS, respectively. g m,MNi and r ds,MNi are the transconductance and conduction resistance of the i th NMOS, respectively. Zero frequency ω z can be modified by placing a resistor R z in series with the compensation capacitor C Z [26]. If R z ≥ (g m,MN6 ) −1 , then ω z ≤ 0. Zero may be moved into the left-half plane for cancelling the first nondominant pole ω p2 . The compensation resistance R Z is then given as follows: where C 1 and C 2 are total capacitances at node E before C Z was added and that at node V err , respectively. Moreover, the increasing C Z moves the dominant pole to a lower frequency without affecting the second pole. This effect ensures that the designed amplifier is more stable [25]. The simulated results indicate that DC gain, phase margin, and unit-gain bandwidth were 50 dB, 60 • , and 1.57 MHz, respectively, at a supplied voltage of 1.7 V and quiescent current of 223.22 nA. The feedback network was a voltage-trimming network and comprised four diode-connected PMOSs (M P10 -M P13 ) and an adjustable voltage, V A , which is generally connected to a voltage of 1.4 V. Three PMOSs were designed to complete coarse adjustment, whereas the NMOS M P10 was used to perform fine-tuning by controlling the adjustable voltage V A . To stabilize the LDO regulator, phase characteristics were adjusted such that a phase shift was less than 180 • at gain crossover. Frequency compensation is completed by connecting a resistor R F in series with a filter capacitor C F . The loop gain was zero at s z = −(R F C F ) −1 .   Figure 8 presents the charge control circuit, which was used to control the charge in the battery by using the supplied output voltage V dd of the LDO regulator. The control circuit comprised a differential pair (Q 1 -Q 3 ), current mirror (Q 4 -Q 5 ), and comparator (Comp) to prevent the overcharging of the battery. Channel length modulation and body effect were assumed negligible, and the differential pair operated in a saturation region. The battery was charged using a constant current, which was generated using Q 1 and Q 2 with two bias voltages (V B1 and V B2 ). When the battery voltage V bat was lower than the reference voltage V ref , the output voltage of the comparator increased to a high level (1) and Q 3 was turned off. Two constant currents of Q 1 and Q 4 simultaneously flowed into Q 2 . The conduction current of Q 5 was amplified N times with (W/L) 5 = N×(W/L) 4 when it was passed through the current mirror Q 4 -Q 5. This large current rapidly charged the battery. If V bat was higher than V ref , the output voltage of the comparator was low (0) and Q 3 was turned off. Two constant currents of Q 1 and Q 3 simultaneously flowed into Q 2 . Moreover, Q 4 and Q 5 were turned off, and the battery was not further charged.  Figure 9 presents the simulated output voltage of the RF-DC rectifier by using a signal analyzer (EXA N9010A) at a distance of 10.0 cm between the antenna and rectifier. The operating frequency was 915 MHz, and the equivalent load was 1 MΩ. The simulation results revealed a minimum output voltage of 0.746 V at an input power Pin of −20 dBm, and a maximum output voltage of 21.693 V at Pin = +20 dBm. The proposed RF-energy-harvesting chip requires the over-voltage protection circuit to prevent the breakdown phenomenon, which is generated by high output voltages, particularly for NFC. Figure 10 shows the simulated DC output voltages of the RF-DC rectifier with over-voltage protection, which were limited from 1.773 V to 1.809 V with respect to the input power Pin from −13 dBm to +20 dBm. Figure 11 presents the simulated PCE of the RF-DC rectifier with over-voltage protection, which is termed the rectifier PCE. It was approximately 43.601% at an input power of −7 dBm. PCE is defined as that in [26]:  Figure 9 presents the simulated output voltage of the RF-DC rectifier by using a signal analyzer (EXA N9010A) at a distance of 10.0 cm between the antenna and rectifier. The operating frequency was 915 MHz, and the equivalent load was 1 MΩ. The simulation results revealed a minimum output voltage of 0.746 V at an input power P in of −20 dBm, and a maximum output voltage of 21.693 V at P in = +20 dBm. The proposed RF-energy-harvesting chip requires the over-voltage protection circuit to prevent the breakdown phenomenon, which is generated by high output voltages, particularly for NFC. Figure 10 shows the simulated DC output voltages of the RF-DC rectifier with over-voltage protection, which were limited from 1.773 V to 1.809 V with respect to the input power P in from −13 dBm to +20 dBm. Figure 11 presents the simulated PCE of the RF-DC rectifier with over-voltage protection, which is termed the rectifier PCE. It was approximately 43.601% at an input power of −7 dBm. PCE is defined as that in [26]:

Simulated and Measured Results
from 1.2 V to 1.5 V, to charge the battery with the charging current of 16 μA. When the battery voltage was charged to 1.4 V at 2.002 ms, the charging current decreased sharply, thereby reducing the charging speed. Finally, the voltage of the battery increased to 1.50 V with zero charging current. Figure 14 shows the simulated battery voltage and charging current of the charger control circuit. The maximum power efficiency of the charge control circuit was 84.835% at an input power Pin of +20 dBm.   was charged to 1.4 V at 2.002 ms, the charging current decreased sharply, thereby reducing the charging speed. Finally, the voltage of the battery increased to 1.50 V with zero charging current. Figure 14 shows the simulated battery voltage and charging current of the charger control circuit. The maximum power efficiency of the charge control circuit was 84.835% at an input power Pin of +20 dBm.    The proposed LDO regulator provides a stable output voltage of 1.5 V and a load current of 30 µA to the next stage-charge control circuit. When the input voltage varied from 1.7 V to 2.0 V and the reference voltage was 1.4 V, the LDO regulator performed with a quiescent current of 317 nA, and a maximum power efficiency of 84.835% was obtained at an input power P in of −10 dBm. Figure 12 shows the simulated line regulation of the proposed LDO regulator. When the input voltage was varied from 1.7 V to 2.0 V, the output voltage changed from 1.5 V to 1.5108 V, and a line regulation of 36 mV/V was obtained. Figure 13 presents the simulated load regulation of the proposed LDO regulator. As the output current varied from 0.0 µA to 10.0 µA, the output voltage changed from 1.499952 V to 1.499968 V. A load regulation of 1.6 mV/mA was then obtained [27].        The charge control circuit was inputted with a pulse waveform, which is gradually ramped up from 1.2 V to 1.5 V, to charge the battery with the charging current of 16 µA. When the battery voltage was charged to 1.4 V at 2.002 ms, the charging current decreased sharply, thereby reducing the charging speed. Finally, the voltage of the battery increased to 1.50 V with zero charging current. Figure 14 shows the simulated battery voltage and charging current of the charger control circuit. The maximum power efficiency of the charge control circuit was 84.835% at an input power P in of +20 dBm. When all functional blocks were verified, the RF-energy-harvesting chip could be implemented using the standard TSMC 0.18 μm 1P6M CMOS process. Figure 15 shows the layout of the proposed RF-energy-harvesting IC, which comprised the RF-DC rectifier, over-voltage protection circuit, CMOS voltage reference, LDO regulator, and charge control circuit. The over-voltage protection circuit, low-voltage LDO regulator, and charge control circuit of the RF-DC rectifier required 33 μW, 5 μW, and 4 μW, respectively, to charge the battery to 24 μW. The simulation results revealed that charging current was 16 μA at N = 55, and the over-voltage protection mechanism was started at 2.002 by setting the output voltage of the over-voltage protection circuit, output voltage of the charger control circuit, and reference voltage at 1.7 V, 1.5 V, and 1.4 V, respectively. Figure 16 shows the simulated total power conversion efficiency of the proposed RF-energy-harvesting IC, which was termed the system PCE. The maximum system PCE was 29.873% at an input power Pin of −12 dBm. The maximum rectifier PCE was reduced to the same value at Pin = −12 dBm by integrating all designed circuits into a single chip ( Figure 11). Table 1 summarizes the performance and compares it with that of other RF-DC rectifiers. The simulated maximum rectifier PCE in this study was superior to the PCEs of previously published RF-DC rectifiers. Table 2 presents the simulated specifications of the proposed RF-energy-harvesting IC.  When all functional blocks were verified, the RF-energy-harvesting chip could be implemented using the standard TSMC 0.18 µm 1P6M CMOS process. Figure 15 shows the layout of the proposed RF-energy-harvesting IC, which comprised the RF-DC rectifier, over-voltage protection circuit, CMOS voltage reference, LDO regulator, and charge control circuit. The over-voltage protection circuit, low-voltage LDO regulator, and charge control circuit of the RF-DC rectifier required 33 µW, 5 µW, and 4 µW, respectively, to charge the battery to 24 µW. The simulation results revealed that charging current was 16 µA at N = 55, and the over-voltage protection mechanism was started at 2.002 by setting the output voltage of the over-voltage protection circuit, output voltage of the charger control circuit, and reference voltage at 1.7 V, 1.5 V, and 1.4 V, respectively. Figure 16 shows the simulated total power conversion efficiency of the proposed RF-energy-harvesting IC, which was termed the system PCE. The maximum system PCE was 29.873% at an input power P in of −12 dBm. The maximum rectifier PCE was reduced to the same value at P in = −12 dBm by integrating all designed circuits into a single chip ( Figure 11). Table 1 summarizes the performance and compares it with that of other RF-DC rectifiers. The simulated maximum rectifier PCE in this study was superior to the PCEs of previously published RF-DC rectifiers. Table 2 presents the simulated specifications of the proposed RF-energy-harvesting IC. When all functional blocks were verified, the RF-energy-harvesting chip could be implemented using the standard TSMC 0.18 μm 1P6M CMOS process. Figure 15 shows the layout of the proposed RF-energy-harvesting IC, which comprised the RF-DC rectifier, over-voltage protection circuit, CMOS voltage reference, LDO regulator, and charge control circuit. The over-voltage protection circuit, low-voltage LDO regulator, and charge control circuit of the RF-DC rectifier required 33 μW, 5 μW, and 4 μW, respectively, to charge the battery to 24 μW. The simulation results revealed that charging current was 16 μA at N = 55, and the over-voltage protection mechanism was started at 2.002 by setting the output voltage of the over-voltage protection circuit, output voltage of the charger control circuit, and reference voltage at 1.7 V, 1.5 V, and 1.4 V, respectively. Figure 16 shows the simulated total power conversion efficiency of the proposed RF-energy-harvesting IC, which was termed the system PCE. The maximum system PCE was 29.873% at an input power Pin of −12 dBm. The maximum rectifier PCE was reduced to the same value at Pin = −12 dBm by integrating all designed circuits into a single chip ( Figure 11). Table 1 summarizes the performance and compares it with that of other RF-DC rectifiers. The simulated maximum rectifier PCE in this study was superior to the PCEs of previously published RF-DC rectifiers. Table 2 presents the simulated specifications of the proposed RF-energy-harvesting IC.   The matching network was completed with off-chip components to have an input impedance of approximately 50 Ω. Figure 17 shows the matching network, which was designed to obtain not only maximum power transfer but also maximum conversion efficiency. The E5071C network analyzer was used to measure the input impedance against various input powers. Moreover, multiple sets of matching circuits were designed to ensure that each set of the matching circuit exhibited an input return loss (S11) of less than −25 dB. For example, an input impedance of 51.464 -j × 1.3071 could be achieved with an input return loss (S11) of −34.271 dB by putting a parallel inductance (L) of 7.5 nH and a series capacitance (c) of 22 pF on a printed circuit board (PCB). Figure 18 shows the measured input return loss in the Z-smith chart at an input power and RF frequency of 0 dBm and 915.0000 MHz, respectively.  The matching network was completed with off-chip components to have an input impedance of approximately 50 Ω. Figure 17 shows the matching network, which was designed to obtain not only maximum power transfer but also maximum conversion efficiency. The E5071C network analyzer was used to measure the input impedance against various input powers. Moreover, multiple sets of matching circuits were designed to ensure that each set of the matching circuit exhibited an input return loss (S 11 ) of less than −25 dB. For example, an input impedance of 51.464 -j × 1.3071 could be achieved with an input return loss (S 11 ) of −34.271 dB by putting a parallel inductance (L) of 7.5 nH and a series capacitance (c) of 22 pF on a printed circuit board (PCB). Figure 18 shows the measured input return loss in the Z-smith chart at an input power and RF frequency of 0 dBm and 915.0000 MHz, respectively.          Table 3 summarizes the results for the designed RF-DC rectifier with the over-voltage protection circuit. Because the distance between the Powercast transmitter and test PCB was provided, the input power Pin (dBm), input return loss S11 (dB), and DC output voltage Vdc (V) were measured after the input impedance Zin (Ω) and its corresponding matching circuits [L (nH) and C (pF)] were completed. The results showed that the DC output voltage Vdc varied from 0.291 V to 1.725 V with respect to the distance from 5.45 m to 0.55 m. The measured output voltages were lower than the simulated results. A stable charging voltage Vdd can be obtained through the LDO regulator. Figure 21 shows the measured DC output voltage Vdc of the designed RF-DC rectifier with the over-voltage protection circuit with respect to the input power Pin from −20 dBm to +10 dBm. Please note that the measured   Table 3 summarizes the results for the designed RF-DC rectifier with the over-voltage protection circuit. Because the distance between the Powercast transmitter and test PCB was provided, the input power Pin (dBm), input return loss S11 (dB), and DC output voltage Vdc (V) were measured after the input impedance Zin (Ω) and its corresponding matching circuits [L (nH) and C (pF)] were completed. The results showed that the DC output voltage Vdc varied from 0.291 V to 1.725 V with respect to the distance from 5.45 m to 0.55 m. The measured output voltages were lower than the simulated results. A stable charging voltage Vdd can be obtained through the LDO regulator. Figure 21 shows the measured DC output voltage Vdc of the designed RF-DC rectifier with the over-voltage protection circuit with respect to the input power Pin from −20 dBm to +10 dBm. Please note that the measured DC output voltages were limited from 1.682 V to 1.725 V with respect to the input power from −2  Table 3 summarizes the results for the designed RF-DC rectifier with the over-voltage protection circuit. Because the distance between the Powercast transmitter and test PCB was provided, the input power P in (dBm), input return loss S 11 (dB), and DC output voltage V dc (V) were measured after the input impedance Z in (Ω) and its corresponding matching circuits [L (nH) and C (pF)] were completed. The results showed that the DC output voltage V dc varied from 0.291 V to 1.725 V with respect to the distance from 5.45 m to 0.55 m. The measured output voltages were lower than the simulated results. A stable charging voltage V dd can be obtained through the LDO regulator. Figure 21 shows the measured DC output voltage Vdc of the designed RF-DC rectifier with the over-voltage protection circuit with respect to the input power P in from −20 dBm to +10 dBm. Please note that the measured DC output voltages were limited from 1.682 V to 1.725 V with respect to the input power from −2 dBm to +10 dBm in Figure 21. Table 3. Measured input power P in (dBm), input return loss S 11 (dB), and output DC voltage V dc (V) with respect to distance (m) between the transmitter and test PCB, input impedance Z in (Ω) and its corresponding matching circuits [L (nH) and C (pF)] for the RF-DC rectifier with the over-voltage protection circuit.

Distance (m)
Z in (    Finally, the simulated rectifier PCE was 43.601% at an input power P in of −7 dBm, and the simulated system PCE was 29.873% at an input power P in and a load resistor of −12 dBm and 1 MΩ, respectively. The limitation of system integration is the reduction of the PCE from 43.601% to 29.873%. The improvement of the system PCE is a crucial concern. This study focused on increasing the system PCE by changing the load resistor from 20 kΩ to 38 kΩ. Figure 22 exhibits the measured system PCE with respect to the input power P in (dBm) and load resistor. The larger the load resistor is, the smaller the input power is. A large load resistor reduces load current, whereas it increases charging current I bat for the abrupt charging of the battery. This phenomenon provides the maximum system PCE at a low input power. A trade-off was observed between the load resistor and the maximum system PCE. Moreover, the results indicate that the largest system PCE of 40.556% was observed at a load resistor of 30 kΩ and an input power P in of −6 dBm.   Table 4 shows the measured electrical characterizations of the proposed RF-energy-harvesting IC, which includes the power consumption, power delivery, and other electrical characterization facts. Table 5 summarizes the performance and compares the performance with that of other RF-DC rectifiers and RF-energy-harvesting ICs. The maximum rectifier PCE obtained in this study was superior to that in [30], and the maximum PCE of the RF-energy-harvesting IC was superior to that in [31]. Several RF-DC rectifiers have been studied in the past few years; however, studies on system integration, such as RF-energy-harvesting ICs, have been rare. Furthermore, the IC proposed in this study exhibited low power consumption and a small chip area. It is possible to decrease the labor cost significantly by eliminating the future maintenance efforts to replace batteries. At close range, this proposed IC can be used to trickle charge for low power devices including GPS, tracking tags, wearable sensors, and consumer electronics. At long range, this transmitted power can be used for battery-based or battery-free remote sensors for factory automation, structural health monitoring, and industrial control. In future work, the power conversion efficiencies (PCEs) of the rectifier and RF-energy harvesting chip can be improved by reducing the energy consumption of each proposed circuit.   Table 4 shows the measured electrical characterizations of the proposed RF-energy-harvesting IC, which includes the power consumption, power delivery, and other electrical characterization facts. Table 5 summarizes the performance and compares the performance with that of other RF-DC rectifiers and RF-energy-harvesting ICs. The maximum rectifier PCE obtained in this study was superior to that in [30], and the maximum PCE of the RF-energy-harvesting IC was superior to that in [31]. Several RF-DC rectifiers have been studied in the past few years; however, studies on system integration, such as RF-energy-harvesting ICs, have been rare. Furthermore, the IC proposed in this study exhibited low power consumption and a small chip area. It is possible to decrease the labor cost significantly by eliminating the future maintenance efforts to replace batteries. At close range, this proposed IC can be used to trickle charge for low power devices including GPS, tracking tags, wearable sensors, and consumer electronics. At long range, this transmitted power can be used for battery-based or battery-free remote sensors for factory automation, structural health monitoring, and industrial control. In future work, the power conversion efficiencies (PCEs) of the rectifier and RF-energy harvesting chip can be improved by reducing the energy consumption of each proposed circuit.

Conclusions
This study proposed an auxiliary power integrated chip (IC) to supply power to the WSN with a Power cast transmitter of ISM 915 MHz. The RF-energy-harvesting IC was designed and fabricated using the standard TSMC 0.18 µm 1P6M CMOS process. The externally matched capacitors and inductors were manufactured in the matching network by MuRata Company. On integrating the externally matched components with the designed RF-energy-harvesting IC, the simulated results showed that the maximum PCEs of the rectifier and harvesting IC were 43.6% and 29.873%, respectively, at an ISM band of 915 MHz, an input power of −7 dBm, and a load of 1 MΩ. The output voltage of the RF-DC rectifier with the over-voltage protection circuit was limited from 1.773 V to 1.809 V with the varying input power from −10 dBm to +20 dBm. A stable voltage of 1.5 V was supplied to the charge control circuit passing through the LDO circuit. Measurements validated that the designed RF-energy-harvesting IC works successfully. The output voltage V dc varied from 0.291 V to 1.725 V with respect to the distance from 5.45 m to 0.55 m. The large load resistor reduced load current; however, it sharply increased the charging current to charge the battery abruptly. This phenomenon provided the maximum system PCE at low input power. A trade-off was observed between the load resistor and the maximum system PCE. Furthermore, the maximum rectifier PCE of this study was superior to that in [30], and the maximum PCE of the RF-energy-harvesting IC was superior to that in [31]. Measurements indicate that the IC used in this study exhibited low power consumption and a small chip area. The proposed energy harvesting IC can be used in both ambient source and dedicated source [34]. Another possibility offered by the use of microelectronic substrates is on-chip photovoltaic generation with integrated photodiodes [35,36].
Author Contributions: This study was completed by four authors. Y.-J.L. and J.-Y.S. designed and implemented the proposed chip; C.-K.C. completed the system integration and measurements; and G.-M.S. analyzed the data and wrote the paper.