A 10-Bit 300 kS/s Reference-Voltage Regulator Free SAR ADC for Wireless-Powered Implantable Medical Devices

This paper presents a reference-voltage regulator free successive-approximation-register analog-to-digital converters (SAR ADC) with self-timed pre-charging for wireless-powered implantable medical devices. Assisted by a self-timed pre-charging technique, the proposed SAR ADC eliminates the need for a power-hungry reference-voltage regulator and area-consuming decoupling capacitor while maintaining insensitivity to the supply voltage fluctuation. Fabricated with a 0.18-µm complementary metal–oxide–semiconductor (CMOS) technology, the proposed SAR ADC achieves a Signal To Noise And Distortion Ratio (SNDR) of 53.32 dB operating at 0.8 V with a supply voltage fluctuation of 50 mVpp and consumes a total power of 2.72 µW at a sampling rate of 300 kS/s. Including the self-timed pre-charging circuits, the total figure-of-merit (FOM) is 23.9 fJ/conversion-step and the total area occupied is 0.105 mm2.


Introduction
As one of the typical health monitoring applications, wireless implantable medical devices are powered via wireless power transfer, which is shown in Figure 1. It is mandatory to include a rectifier to convert the coupled AC power into DC power. Even with advanced rectifiers, such as the reconfigurable resonant regulating rectifier (R 3 rectifier), the ripple of the rectified voltage can still be measured in tens of mV [1]. For conventional SAR ADCs adopted in such systems [2][3][4][5][6][7][8][9], a dedicated regulator is needed to stabilize the reference voltage against the ADC core. However, the regulator consumes significant power [2][3][4]. Besides, decoupling capacitors of a few hundred pF or larger values are needed to maintain the stable operation of the regulator [10]. As it is preferred to have decoupling capacitors on chips in wireless implantable medical devices for system miniaturization, the increase in silicon area and hence, cost are inevitable.
In the past, most designs focused on optimizing the power and area of the sub-blocks in the SAR ADC core [5][6][7][8], while only a few studies aimed to optimize the reference-voltage regulator [2][3][4]11]. It was found that if the power consumption of the reference-voltage regulator is included, the FOM of ADC degrades from 100 fJ/c-s to 1000 fJ/c-s [2] or from 25 fJ/c-s to 738 fJ/c-s [3]. In a previous study [4], a SAR ADC with energy-efficient reference generation was proposed, in which power saving was realized by applying a duty-cycle technique in the reference generator. However, an always-on low dropout regulator is needed to drive the ADC core, which leads to quiescent current and dropout voltage. The power dissipated by the regulator accounts for more than 30% of the total In the past, most designs focused on optimizing the power and area of the sub-blocks in the SAR ADC core [5][6][7][8], while only a few studies aimed to optimize the reference-voltage regulator [2][3][4]11]. It was found that if the power consumption of the reference-voltage regulator is included, the FOM of ADC degrades from 100 fJ/c-s to 1000 fJ/c-s [2] or from 25 fJ/c-s to 738 fJ/c-s [3]. In a previous study [4], a SAR ADC with energy-efficient reference generation was proposed, in which power saving was realized by applying a duty-cycle technique in the reference generator. However, an always-on low dropout regulator is needed to drive the ADC core, which leads to quiescent current and dropout voltage. The power dissipated by the regulator accounts for more than 30% of the total power consumption of the SAR ADC. Besides, a large decoupling capacitor is needed to maintain the stable operation of the regulator In this paper, we present a reference-voltage regulator free SAR ADC using self-timed pre-charging for wireless-powered implantable medical devices. It eliminates the power-hungry reference-voltage regulator to reduce the overall power consumption of the SAR ADC. Furthermore, the need for a large on-chip decoupling capacitor is eliminated, which helps to reduce the silicon area. The proposed design achieves good SNDR under the conditions of supply voltage fluctuation. Taking into account the power and area of the reference-voltage regulator, the proposed SAR ADC achieves better FOM with a small area compared to several existing SAR ADC designs.

Proposed Reference-Voltage Regulator Free SAR ADC
In SAR ADC, any disturbance or error in the reference voltage will cause the digitized output codes to deviate from the correct value with errors. Consequently, it introduces large amounts of noise and decreases the SNDR of the ADC. As discussed previously, in wireless-powered implantable medical devices, the output voltage of the rectifier contains large ripples and cannot be used directly as the reference voltage in conventional SAR ADC. Therefore, in the typical wireless-powered implantable medical devices, a dedicated regulator with decoupling capacitor is used to provide a stable reference voltage for charging the digital-to-analog converter (DAC) capacitors, which dramatically increases the power consumption and required area.

System Architecture
In order to eliminate the need for the reference-voltage regulator and the decoupling capacitor, we propose a SAR ADC with self-timed pre-charging, which is shown in Figure 2. It consists of a current pre-charging circuit, a charge detector and a 10-bit conventional charge-sharing SAR ADC [9] using asynchronous SAR logic. The most significant bit (MSB) uses 32-unit capacitors, while the 5 least significant bits (LSBs) use 1 unit capacitor each. The rising edge of fs will trigger the PreC signal to increase in order to perform pre-charging. When the voltage crosses the Vref, a Cross signal is generated by the detector and it will pull down the PreC signal to end the pre-charging. Furthermore, the logic low of PreC will set the Cross to high logic. The internal clock fclk for In this paper, we present a reference-voltage regulator free SAR ADC using self-timed pre-charging for wireless-powered implantable medical devices. It eliminates the power-hungry reference-voltage regulator to reduce the overall power consumption of the SAR ADC. Furthermore, the need for a large on-chip decoupling capacitor is eliminated, which helps to reduce the silicon area. The proposed design achieves good SNDR under the conditions of supply voltage fluctuation. Taking into account the power and area of the reference-voltage regulator, the proposed SAR ADC achieves better FOM with a small area compared to several existing SAR ADC designs.

Proposed Reference-Voltage Regulator Free SAR ADC
In SAR ADC, any disturbance or error in the reference voltage will cause the digitized output codes to deviate from the correct value with errors. Consequently, it introduces large amounts of noise and decreases the SNDR of the ADC. As discussed previously, in wireless-powered implantable medical devices, the output voltage of the rectifier contains large ripples and cannot be used directly as the reference voltage in conventional SAR ADC. Therefore, in the typical wireless-powered implantable medical devices, a dedicated regulator with decoupling capacitor is used to provide a stable reference voltage for charging the digital-to-analog converter (DAC) capacitors, which dramatically increases the power consumption and required area.

System Architecture
In order to eliminate the need for the reference-voltage regulator and the decoupling capacitor, we propose a SAR ADC with self-timed pre-charging, which is shown in Figure 2. It consists of a current pre-charging circuit, a charge detector and a 10-bit conventional charge-sharing SAR ADC [9] using asynchronous SAR logic. The most significant bit (MSB) uses 32-unit capacitors, while the 5 least significant bits (LSBs) use 1 unit capacitor each. The rising edge of f s will trigger the PreC signal to increase in order to perform pre-charging. When the voltage crosses the V ref , a Cross signal is generated by the detector and it will pull down the PreC signal to end the pre-charging. Furthermore, the logic low of PreC will set the Cross to high logic. The internal clock f clk for asynchronous SAR logic is generated by the comparator [4]. During the sampling period, the input signal is sampled onto the sampling capacitors Cs. At the same time, the DAC capacitors are pre-charged with a current source. Controlled by a charge detector, the current source will be turned off when the charge reaches a pre-set value Qset, which is called self-timed pre-charging. During the conversion period, according to the results from the comparator, the charge in the DAC capacitors is added to or subtracted from Cs. Therefore, if the Vref fluctuates during sampling periods, the charge in the DAC capacitors will also fluctuate. The common mode part of charge variation may cause an error, but it can be removed by calibration, which also occurs in conventional ADCs. However, the differential part is not constant and cannot be removed by calibration. This will cause an error and SNDR degradation if the differential part is larger than the LSB charge (2.5 fC in this design). Figure 3a shows the pre-charging process with different charging currents (i.e., Ich1 and Ich2). In Figure 3a, we assume that the charge detector is ideal with the response time being zero. Although Ich1 and Ich2 are different, the same charge is obtained through different charging times (i.e., T1 and T2). However, in practice, the charge detector has a response time or delay. For wireless-powered medical devices, the delay is affected by the supply voltage fluctuation. As illustrated in Figure 3b, with a small difference in the supply voltage, the delay will be td + δ/2 and td − δ/2, respectively, where td is the basic delay of the charge detector and δ is a delay difference caused by the supply voltage fluctuation. The delay difference induces a difference in the charge (i.e., ∆Q), which can be expressed as: where ∆CMQ is the common part of charge variation and ∆DQ is the differential part. As mentioned previously, the common part of charge variation may cause an error but it can be removed by During the sampling period, the input signal is sampled onto the sampling capacitors C s . At the same time, the DAC capacitors are pre-charged with a current source. Controlled by a charge detector, the current source will be turned off when the charge reaches a pre-set value Q set , which is called self-timed pre-charging. During the conversion period, according to the results from the comparator, the charge in the DAC capacitors is added to or subtracted from C s . Therefore, if the V ref fluctuates during sampling periods, the charge in the DAC capacitors will also fluctuate. The common mode part of charge variation may cause an error, but it can be removed by calibration, which also occurs in conventional ADCs. However, the differential part is not constant and cannot be removed by calibration. This will cause an error and SNDR degradation if the differential part is larger than the LSB charge (2.5 fC in this design). Figure 3a shows the pre-charging process with different charging currents (i.e., I ch1 and I ch2 ). In Figure 3a, we assume that the charge detector is ideal with the response time being zero. Although I ch1 and I ch2 are different, the same charge is obtained through different charging times (i.e., T 1 and T 2 ). However, in practice, the charge detector has a response time or delay. For wireless-powered medical devices, the delay is affected by the supply voltage fluctuation. As illustrated in Figure 3b, with a small difference in the supply voltage, the delay will be t d + δ/2 and t d − δ/2, respectively, where t d is the basic delay of the charge detector and δ is a delay difference caused by the supply voltage fluctuation. The delay difference induces a difference in the charge (i.e., ∆ Q ), which can be expressed as: where ∆ CMQ is the common part of charge variation and ∆ DQ is the differential part. As mentioned previously, the common part of charge variation may cause an error but it can be removed by calibration, which also occurs in conventional ADC. However, the differential part is not constant and cannot be removed by calibration. In order to not affect the performance, the differential part ∆ DQ needs to be less than the LSB charge in the design. For the pre-charging scheme, a large pre-charging current is used to shorten the pre-charging time to achieve a sufficient sampling rate. However, this larger current is more sensitive to supply voltage fluctuation, thus causing large charge variation, which is shown in Figure 3b. This can be explained as follows. With a current source as shown in Figure 2, the charging current (i.e., I ch ) can be expressed as: where K and V th are the transconductance parameter and threshold voltage of the PMOS, respectively.
To determine I ch 's sensitivity to VDD, the derivative of I ch is obtained with respect to VDD in Equations (2) and (3). This gives: Sensors 2018, 18, x FOR PEER REVIEW 4 of 10 calibration, which also occurs in conventional ADC. However, the differential part is not constant and cannot be removed by calibration. In order to not affect the performance, the differential part ∆DQ needs to be less than the LSB charge in the design. For the pre-charging scheme, a large pre-charging current is used to shorten the pre-charging time to achieve a sufficient sampling rate. However, this larger current is more sensitive to supply voltage fluctuation, thus causing large charge variation, which is shown in Figure 3b. This can be explained as follows. With a current source as shown in Figure 2, the charging current (i.e., Ich) can be expressed as: where K and Vth are the transconductance parameter and threshold voltage of the PMOS, respectively. To determine Ich's sensitivity to VDD, the derivative of Ich is obtained with respect to VDD in Equations (2) and (3). This gives: (4) Figure 3. Self-timed pre-charging (a) ideal detector; (b) non-ideal detector using one pre-charging phase with large current; (c) non-ideal detector using one pre-charging phase with small current; and (d) non-ideal detector using two pre-charging phases.
From Equation (4), it can be seen that with a smaller (VDD−Vg−Vth) or current Ich, the current's sensitivity to VDD is smaller, which results in a smaller charge variation (see Figure 3c). However, this smaller pre-charging current needs longer charging time and this limits the sampling rate of the ADC.
To achieve a sufficient sampling rate while ensuring a small charge variation (less than 1 LSB charge), we proposed a pre-charging scheme with two charging phases, which is shown in   Figure 3. Self-timed pre-charging (a) ideal detector; (b) non-ideal detector using one pre-charging phase with large current; (c) non-ideal detector using one pre-charging phase with small current; and (d) non-ideal detector using two pre-charging phases.
From Equation (4), it can be seen that with a smaller (VDD−V g −V th ) or current I ch , the current's sensitivity to VDD is smaller, which results in a smaller charge variation (see Figure 3c). However, this smaller pre-charging current needs longer charging time and this limits the sampling rate of the ADC.
To achieve a sufficient sampling rate while ensuring a small charge variation (less than 1 LSB charge), we proposed a pre-charging scheme with two charging phases, which is shown in Figure 3d. During the first charging phase, the DAC capacitors are quickly charged with a large charging current (i.e., I chL ) and constant charging time (i.e., T c ). In the second charging phase, a small charging current (i.e., I chS ) is used to complete the rest of charging and is turned off when the charge reaches the pre-set value Q set . By using the two-phase pre-charging scheme, the charge variation is reduced and the charging time is also shortened.

Circuit Implementation Details
To save power consumption, a 2-transistor (2T) voltage reference [12] is adopted. A native N-channel metal oxide semiconductor FET (NMOS) and a high threshold NMOS are used to generate a V ref with 400 mV, which is shown in Figure 2. The value of the sampling capacitor C s used is 3.2 pF. With a maximum signal swing of roughly 800 mV peak-to-peak differential, the LSB charge of this ADC can be calculated as: Figure 4 shows the schematic of the charge detector used for controlling the self-timed pre-charging. It consists of two stages. The first stage amplifies the input signals and converts the voltage difference between V cap and V ref to a single-ended output. The output of the first stage will trigger the second stage when V cap crosses V ref . To minimize the power consumption, the first stage operates only during the pre-charging phase, which occurs when PreC is actively high. The simulation shows that the delay of the charge detector varies from 418.3 ns to 410.8 ns when the supply voltage is changed from 0.775 V to 0.825 V. In the second charging phase, a small charging current (i.e., IchS) is used to complete the rest of charging and is turned off when the charge reaches the pre-set value Qset. By using the two-phase pre-charging scheme, the charge variation is reduced and the charging time is also shortened.

Circuit Implementation Details
To save power consumption, a 2-transistor (2T) voltage reference [12] is adopted. A native N-channel metal oxide semiconductor FET (NMOS) and a high threshold NMOS are used to generate a Vref with 400 mV, which is shown in Figure 2. The value of the sampling capacitor Cs used is 3.2 pF. With a maximum signal swing of roughly 800 mV peak-to-peak differential, the LSB charge of this ADC can be calculated as: Figure 4 shows the schematic of the charge detector used for controlling the self-timed pre-charging. It consists of two stages. The first stage amplifies the input signals and converts the voltage difference between Vcap and Vref to a single-ended output. The output of the first stage will trigger the second stage when Vcap crosses Vref. To minimize the power consumption, the first stage operates only during the pre-charging phase, which occurs when PreC is actively high. The simulation shows that the delay of the charge detector varies from 418.3 ns to 410.8 ns when the supply voltage is changed from 0.775 V to 0.825 V. The schematic of the current source used for pre-charging is shown in Figure 5. The reference current, Iref, is equal to the difference of the threshold voltage between MN1 and MN2 divided by the value of resistor R, which is independent of the supply. The output currents, IchL and IchS, are generated from Iref through the current mirror. The IchL is used as the first phase charging current and is about 14 µA. The IchS is used as the second phase charging current and is about 200 nA. The values of IchL and IchS are determined through extensive simulation by considering both the charge variation and pre-charging time. The simulation shows that when VDD is larger than 0.6 V, the sensitivity of IchL and IchS to VDD are 19 µA/V and 36 nA/V, respectively. With a smaller current, the sensitivity is much lower, which verified the previous analysis presented in Section 2.1. To save power and area, the beta-multiplier reference also generates Vbdet for the first stage amplifier in the charge detector. The schematic of the current source used for pre-charging is shown in Figure 5. The reference current, I ref , is equal to the difference of the threshold voltage between MN1 and MN2 divided by the value of resistor R, which is independent of the supply. The output currents, I chL and I chS , are generated from I ref through the current mirror. The I chL is used as the first phase charging current and is about 14 µA. The I chS is used as the second phase charging current and is about 200 nA. The values of I chL and I chS are determined through extensive simulation by considering both the charge variation and pre-charging time. The simulation shows that when VDD is larger than 0.6 V, the sensitivity of I chL and I chS to VDD are 19 µA/V and 36 nA/V, respectively. With a smaller current, the sensitivity is much lower, which verified the previous analysis presented in Section 2.1. To save power and area, the beta-multiplier reference also generates V bdet for the first stage amplifier in the charge detector. The simulation also shows that the IchS varies from 203.9 nA to 205.7 nA when the supply voltage varies from 0.775 V to 0.825 V. Using these values together with the delay variation of charge detector (from 418.3 ns to 410.8 ns), the charge variation can be calculated from Equation (1). The calculated common part of the charge variation is 84.9 fC. Even though the common part is large, as discussed previously, it only causes a gain error and the error can be easily removed through calibration. Due to the implementation of the two-phase pre-charging scheme, the differential part is only 0.4 fC, which is negligible when compared to the 1-LSB charge (~2.5 fC). The simulation shows that the two-phase pre-charging time varies from 1.1 µs to 2.3 µs when the supply voltage varies from 0.9 V to 0.7 V. This pre-charging time is sufficiently short for a 300 kS/s sampling rate.

Measurement Results
The proposed reference-voltage regulator free SAR ADC has been implemented and fabricated with a 0.18-µm CMOS technology. The chip micrograph is shown in Figure 6. Core1 is the proposed SAR ADC with an area of 0.105 mm 2 . Core2 is the conventional SAR ADC where all the circuits are the same as Core1 except that the self-timed pre-charging circuits are not included and the reference voltage is directly obtained from an external supply. Core2 occupies 0.088 mm 2 .  The simulation also shows that the I chS varies from 203.9 nA to 205.7 nA when the supply voltage varies from 0.775 V to 0.825 V. Using these values together with the delay variation of charge detector (from 418.3 ns to 410.8 ns), the charge variation can be calculated from Equation (1). The calculated common part of the charge variation is 84.9 fC. Even though the common part is large, as discussed previously, it only causes a gain error and the error can be easily removed through calibration. Due to the implementation of the two-phase pre-charging scheme, the differential part is only 0.4 fC, which is negligible when compared to the 1-LSB charge (~2.5 fC). The simulation shows that the two-phase pre-charging time varies from 1.1 µs to 2.3 µs when the supply voltage varies from 0.9 V to 0.7 V. This pre-charging time is sufficiently short for a 300 kS/s sampling rate.

Measurement Results
The proposed reference-voltage regulator free SAR ADC has been implemented and fabricated with a 0.18-µm CMOS technology. The chip micrograph is shown in Figure 6. Core1 is the proposed SAR ADC with an area of 0.105 mm 2 . Core2 is the conventional SAR ADC where all the circuits are the same as Core1 except that the self-timed pre-charging circuits are not included and the reference voltage is directly obtained from an external supply. Core2 occupies 0.088 mm 2 . The simulation also shows that the IchS varies from 203.9 nA to 205.7 nA when the supply voltage varies from 0.775 V to 0.825 V. Using these values together with the delay variation of charge detector (from 418.3 ns to 410.8 ns), the charge variation can be calculated from Equation (1). The calculated common part of the charge variation is 84.9 fC. Even though the common part is large, as discussed previously, it only causes a gain error and the error can be easily removed through calibration. Due to the implementation of the two-phase pre-charging scheme, the differential part is only 0.4 fC, which is negligible when compared to the 1-LSB charge (~2.5 fC). The simulation shows that the two-phase pre-charging time varies from 1.1 µs to 2.3 µs when the supply voltage varies from 0.9 V to 0.7 V. This pre-charging time is sufficiently short for a 300 kS/s sampling rate.

Measurement Results
The proposed reference-voltage regulator free SAR ADC has been implemented and fabricated with a 0.18-µm CMOS technology. The chip micrograph is shown in Figure 6. Core1 is the proposed SAR ADC with an area of 0.105 mm 2 . Core2 is the conventional SAR ADC where all the circuits are the same as Core1 except that the self-timed pre-charging circuits are not included and the reference voltage is directly obtained from an external supply. Core2 occupies 0.088 mm 2 . The proposed SAR ADC uses a single power supply of 0.8 V. To demonstrate its insensitivity to supply voltage fluctuation, a sinusoidal fluctuation with an amplitude range of 0-200 mVpp is added to the supply voltage. The frequencies of the sinusoidal fluctuation are set to 134.2 kHz and 13.56 MHz, which are widely used carrier frequencies in wireless power transfer [1]. Figure 7 shows which are widely used carrier frequencies in wireless power transfer [1]. Figure 7 shows a 32,768-point fast Fourier transform (FFT) plot for a 127.56-kHz input signal sampled at 300 kS/s under a sinusoidal fluctuation of 50 mV pp and 134.2 kHz. The corresponding effective number of bits (ENOB) of the proposed SAR ADC (i.e., Core1) and conventional SAR ADC (i.e., Core2) are 8.56 bits and 5.61 bits, respectively. Figure 8 shows the SNDR versus the amplitude of the sinusoidal fluctuation. When the amplitude of sinusoidal fluctuation increases from 0 to 200 mV pp , the SNDR decreases by 4.91 dB and 5.05 dB for sinusoidal fluctuations of 134.2 kHz and 13.56 MHz, respectively. As indicated in Figure 9, the measured differential non linearity (DNL) and integral non linearity (INL) are +1.14/−0.77 LSB and +1.96/−1.92 LSB, respectively.  The measured total power consumption of the proposed SAR ADC (i.e., Core1), including the self-timed pre-charging circuits, is 2.72 µW at 300 kS/s and the corresponding FOM is 23.9 fJ/c-s. If the gain error is calibrated on the chip, the FOM will be increased by about 25% due to the power consumed by the multiplier (power consumption estimated based on reference [13]   The measured total power consumption of the proposed SAR ADC (i.e., Core1), including the self-timed pre-charging circuits, is 2.72 µW at 300 kS/s and the corresponding FOM is 23.9 fJ/c-s. If the gain error is calibrated on the chip, the FOM will be increased by about 25% due to the power consumed by the multiplier (power consumption estimated based on reference [13]   The measured total power consumption of the proposed SAR ADC (i.e., Core1), including the self-timed pre-charging circuits, is 2.72 µW at 300 kS/s and the corresponding FOM is 23.9 fJ/c-s. If the gain error is calibrated on the chip, the FOM will be increased by about 25% due to the power consumed by the multiplier (power consumption estimated based on reference [13]  The measured total power consumption of the proposed SAR ADC (i.e., Core1), including the self-timed pre-charging circuits, is 2.72 µW at 300 kS/s and the corresponding FOM is 23.9 fJ/c-s.
If the gain error is calibrated on the chip, the FOM will be increased by about 25% due to the power consumed by the multiplier (power consumption estimated based on reference [13]). Under the same testing conditions, the measured power consumption of the conventional SAR ADC (i.e., Core2) is 2.52 µW. Therefore, the power dissipation of the self-timed pre-charging circuits is around 0.2 µW. This accounts for only 7.3% of the total power consumption of ADC, while a reference-voltage regulator typically consumes at least 30% of [4] or even several times [2,3] the power consumption of ADC.
The comparisons between the proposed SAR ADC and other existing SAR ADCs fabricated with similar technology nodes are provided in Table 1. With a supply voltage fluctuation of 50 mV pp , the proposed design has a similar SNDR to other designs. We noted that the power consumption of the ADC core reported in references [5][6][7][8] do not consider the reference-voltage regulator. Hence, for fair comparison, we provided the estimated power consumed in these reference-voltage regulators in Table 1. The quiescent current of the regulators are estimated using the regulator FOM formula (i.e., FOM reg ), which was defined in [10] as: where C d is the decoupling capacitor, ∆ vout is 1 LSB, I Q is the regulators' quiescent current and I ref is the current used to charge DAC capacitors. Assuming that all the designs have the same C d and FOM reg value as in reference [4] (i.e., C d /FOM reg = 1.43 µF/ns), the quiescent current of the reference-voltage regulator for each design can be calculated using the above formula. Besides, we assume a dropout voltage of 200 mV as calculated in reference [4]. Based on the quiescent current and the dropout voltage, the total power consumption of regulator for each design can be calculated as: P Vre f reg. = I Q × VDD + I re f × V dropout (7)  [5][6][7][8] are estimated based on the regulator used in reference [4] with the assumption that they have the same regulator FOM reg defined in reference [10] and the same dropout voltage.
As shown in Table 1, the proposed self-timed pre-charging SAR ADC achieves a better FOM than the other designs when taking into account the reference-voltage regulator. Including the self-timed pre-charging circuits, the area of the proposed design is similar to that of the other designs without the reference-voltage regulator. Moreover, the decoupling capacitor is not required in our design, which helps to further reduce the total area and cost. Without the reference-voltage regulator, our design finally achieves an ENOB of 8.56 bits, which is adequate for medical devices [5,6,8].

Conclusions
In this paper, a SAR ADC with self-timed pre-charging is proposed to eliminate the reference-voltage regulator and decoupling capacitor for wireless-powered implantable medical devices as they dramatically increase power consumption and required area. Fabricated with a 0.18-µm CMOS technology, the proposed self-timed pre-charging SAR ADC achieves a SNDR of 53.32 dB at 0.8 V with a supply voltage fluctuation of 50 mV pp while consuming a total power of 2.72 µW at a sampling rate of 300 kS/s. Including the self-timed pre-charging circuits, the total FOM is 23.9 fJ/c-s and the total area is 0.105 mm 2 .