A Design of Small Area, 0.95 mW, 612–1152 MHz Open Loop Injection-Locked Frequency Multiplier for IoT Sensor Applications

This paper presents a 612–1152 MHz Injection-Locked Frequency Multiplier (ILFM). The proposed ILFM is used to send an input signal to a receiver in only the I/Q mismatch calibration mode. Adopting a Phase-Locked Loop (PLL) to calibrate the receiver places a burden on this system because of the additional area and power consumption that is required. Instead of the PLL, to satisfy high-frequency, low-jitter and low-area requirements, a Ring Oscillator is adopted in the system. The free-running frequency of the ILFM is automatically and digitally calibrated to reflect the frequency of the injected signal from the harmonics of the reference clock. To control the frequency of the ILFM, the load current is digitally tuned with a 6-bit digital control signal. The proposed ILFM locks to the target frequency using a digitally controlled Frequency Locked Loop (FLL). This chip is fabricated using 1-poly 6-metal 0.18 µm CMOS and has achieved the wide tuning range of 612–1152 MHz. The power consumption is 0.95 mW from a supply voltage of 1.8 V. The measured phase noise of the ILFM is −108 dBc/Hz at a 1 MHz offset.


Introduction
Recently, the Internet of Things (IoT) has been applied to many applications, such as sensor networks and wearable devices. In these applications, low power consumption and small chip area are required to increase battery life and reduce system cost. Therefore, Integrated Chip (IC)s for IoT sensors should be designed to meet these requirements. Low-Intermediate Frequency (IF) receiver architectures have become popular for low-power applications. These structures offer advantages over Zero-IF architectures in terms of the DC-Offset calibration and flicker noise [1]. In low-IF architectures, the down-converted complex baseband signal is represented by two real In-phase and Quadrature-phase (I/Q) signals. Analog parameter variations in the local oscillators, mixer and filters result in gain and phase errors between I/Q paths. Due to these errors, image leaks into the signal band during the down-conversion process. Therefore, the low-IF receiver has a low image rejection ratio (IRR), as shown in Figure 1 [2].
Methods for solving image problems by compensating I/Q mismatch are presented in References [2][3][4][5][6]. During the I/Q mismatch calibration phase, the Injection-Locked Frequency Multiplier (ILFM) block generates the same frequency as the RF signal before receiving the RF signal through the antenna, as shown Figure 1. Since the I/Q signals in the low-IF receiver structure flow to the I/Q signal in the band pass filter (BPF), the I/Q mismatch of the BPF input becomes dominant. Therefore, it is effective to add I/QMC (I/Q Mismatch Calibrator) to compensate for the mismatch of I/Q signals before the BPF. Figure 2 shows a block diagram of the whole low IF using ILFM and I/QMC.  A subharmonic ILFM has been considered as a promising solution to generate low phase noise and high-frequency clocks using a limited silicon area and power consumption budget. However, previous ILFMs are highly sensitive to process, voltage and temperature (PVT) variations. Recently, several papers have been published that suggest some approaches to overcome this problem [7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25]. In References [10][11][12][13], the structure using the most basic single-loop PLL or DLL is used. However, this structure cannot prevent the real-time frequency drift that occurs through supply voltage and temperature variations. In References [14][15][16][17][18][19], a dual-loop structure with a main oscillator and a replica oscillator structure is used to improve the disadvantages of single-loop structure. However, the previous ILFM had the disadvantage of having a large chip area and large power consumption due to its complex structure. In Section 2, the pros and cons of prior works are described and analyzed in detail. In this paper, we propose an ILFM with small chip area and low power consumption using Frequency Locked Loop (FLL). Figure 3a is the block diagram of an ILFM structure with a PLL, and Figure 3b shows the timing diagram. As shown in Figure 3a,b, ILFM injects the reference clock into a Voltage Controlled Oscillator (VCO) and the injection signal realigns the output phase of the free-running VCO. Therefore, low phase noise performance is acquired [7]. This phase-realignment mechanism with the reference clock allows the ILFM to have low-jitter performance. Although the ILFM have many advantages, there are critical requirements for good phase noise performance. It can be achieved only when the target frequency of the ILFM is very close to the free-running frequency of the VCO. Therefore, a good phase noise performance of the ILFM might not be guaranteed, especially for a Ring Oscillator of which the free-running frequency is highly sensitive to PVT variation. In addition, if the frequency of the Ring Oscillator is out of the lock range of ILFM due to the PVT variation, ILFM cannot achieve the injection locking [8]. Therefore, ILFM typically requires an effective PVT calibrator or calibration methods to mitigate the sensitivity of performance to the PVT variation. Figure 3c shows the phase noise graph of the ILFM when the VCO frequency is close to the ILFM target frequency. On the other hand, Figure 3d is the phase noise graph of ILFM when the frequency of VCO changes due to the PVT variation. If there is a frequency error, the in-band phase noise performance is degraded, and the magnitude of reference spurious tone is increased [9]. Conventional methods for overcoming PVT variations are shown in Figure 4a,b [9]. The most popular PVT calibration method is to use a PLL. Figure 4a shows a conventional ILFM structure with single-loop PLL [10][11][12]. The PLL is used to calibrate static PVT variation of the frequency of VCO. However, the structure cannot prevent the real-time frequency drift that occurs through supply voltage and temperature variations. This is because the structure has a PLL loop path and an injection path. A timing problem arises because the two paths operate independently [13]. To overcome this timing issue, an ILFM with two separate loops has been proposed. Figure 4b shows a dual-loop structure with the main oscillator and a replica oscillator [14][15][16][17][18][19][20]. The structure is proposed to resolve the timing problem of PLL based ILFM. The structure has two VCOs which are a main VCO and a replica VCO. The replica VCO is not injection-locked to prevent instantaneous frequency drift. The advantage of this method is that it can be calibrated with a frequency offset and PVT variation of the main VCO in real time using the replica VCO. However, if the mismatch occurs between main VCO and replica VCO, the structure cannot calibrate PVT variation. In addition, the implementation is difficult because it consists of two loops, and there is a disadvantage in that the die area and power consumption are doubled compared to a single structure [13]. Figure 4c shows the ILFM structure of an open loop type with FLL. Figure 4c can reduce the power consumption by turning off the FLL block after F OUT reaching the target frequency using FLL, and the chip area is small because only a simple FLL circuit is used.  Figure 5a shows a block diagram of the proposed ILFM. The proposed ILFM is composed of a Ring Oscillator, an Injection Generator, and FLL. Generally, the clock signal is required for calibration or other purposes in the transceiver or digital block. If the PLL is used to generate a clock signal, it will cause a burden on this system due to the additional area and power consumption. A Ring Oscillator is adopted instead of PLL to satisfy the high frequency and low area.

Proposed Injection-Locked Frequency Multiplier (ILFM) with Frequency Tracking
The Ring Oscillator generates a frequency which is close to the target frequency (f TARGET ). If the output frequency of the ILFM (f ILFM ) is near to the f TARGET , it is precisely locked to f TARGET by the harmonics of the reference clock frequency (f ref ), 36 MHz [7].
where f ILFM is the output frequency of ILFM, and the multiplication factor M can be changed through the current control of the Delay Cell. Figure 5b shows a schematic of the Delay Cell with an injection switch. The Delay Cell is composed of four inverters, a 6-bit Current Bank, and injection switches. A Ring Oscillator is proposed to acquire f TARGET , as shown in Figure 5a. The Current Bank is designed to adjust the frequency using Frequency Calibration Logic. Thus, it is possible to reduce PVT variations and improve phase noise. The injection switches of M injt , and M injb are attached to the nodes of V on and V op , respectively. Figure 6 shows the Frequency Calibration Logic of ILFM. It is composed of a 12-bit Counter, a finite-state machine (FSM), a Digital Comparator, a Coarse Tuning Controller, and a Fine Tuning Controller. Since the ILFM has a locked f TARGET from the Injection Generator, the free-running frequency must be close to the f TARGET . Therefore, the role of the Coarse Tuning Controller is to set the frequency close to f TARGET , by calibrating the free-running frequency of the Ring Oscillator. The role of the Fine Tuning Controller is to lock the ILFM to the f TARGET by controlling the delay (∆T) of the injection generator. When the frequency calibration logic is started, the 12-bit counter counts the current frequency of the Ring Oscillator. The counted value CNT ILFM <11:0> is delivered to the digital comparator. Then, CNT ILFM <11:0> is compared to the reference number, REF<11:0>, which is determined from Equations (2) and (3) based on the f TARGET .
where T_EN CNT is the value of the interval in which the EN CNT signal is High. f ref is the reference clock frequency (36 MHz), and f TARGET is the target frequency.    Figure 7b is a timing diagram of the FSM in the Frequency Calibration Logic. A 12-bit Counter is used to calculate the output frequency of the ILFM. It operates in an asynchronous way when a counter-enabled signal (EN CNT ) is high and is periodically reset by the counter reset signal (RST CNT ) generated by the FSM. The FSM determines the timing of the calibration by generating the decision clock (CLK TUNE ) and a comparison clock (CLK COMP ) using the CLK REF signal [21]. If the value of CNT ILFM <11:0> is higher than REF<11:0>, the DN is generated by the Coarse Tuning Controller and Fine Tuning Controller. On the other hand, if the value of CNT ILFM <11:0> is lower than REF<11:0>, UP is generated. The calibration time is minimized by applying the binary search algorithm. Therefore, I CONT <5:0> is determined by the Coarse Tuning Controller after this loop has been operated six times. The fine tuning works in the same way as the coarse tuning, and the D CONT <3:0> values are determined when fine tuning is in progress. The D CONT <3:0> output determines the injection pulse width of the Injection Generator. The output frequency of the Ring Oscillator is sensitive to a PVT corner variation [7]. Figure 8a shows the simulation result of the frequency variation of the ILFM that is changed by the PVT variation. When frequency calibration logic is not used, the output frequency of the ILFM changes from 766 MHz to 948 MHz depending on the corner condition.
On the other hand, Figure 8b shows the simulation result when the proposed Frequency Calibration Logic is used, and the output frequency of ILFM is exactly calibrated to target frequency (846 MHz) at all PVT corner conditions.  Figure 9 shows a chip microphotograph of the ILFM. The proposed design is fabricated in a 0.18 µm CMOS process and the layout size of the entire ILFM including Ring Oscillator, Injection Generator and FLL is 0.54 mm × 0.12 mm.  Figure 10 shows the transient simulation results when the target frequency of the ILFM is set as 864 MHz. In Figure 10, the output (V op ) of Ring Oscillator and its frequency are plotted. The FLL tracks the target frequency using a successive approximation register (SAR) logic method. As it is shown in the flow chart in Figure 7a, during the FLL operation period, the frequency achieves the target frequency. After both of the DONE Coarse and DONE Fine signals change to 'H', the CLK REF signal is injected and injection locked to the target frequency.  Figure 11 shows the measurement results of the free-running frequency of the Ring Oscillator. The frequency of the ILFM is measured by changing I CONT <5:0> in the ILFM external control mode using a Keysight spectrum analyzer E4440A (Keysight, Santa Rosa, CA, USA). The frequency range of the Ring Oscillator can be adjusted with the Least Significant Bit (LSB) units of about 13 MHz and has a frequency range from 0.58 GHz to 1.41 GHz. Figure 12 shows the measured injection-locked full range of ILFM. It is measured using a Keysight spectrum analyzer E4440A. The output frequency of the ILFM ranges from 612 MHz to 1152 MHz, corresponding to 17 and 32 times 36 MHz, respectively. The ILFM can lock to N times the reference clock within the injection-locked range.   Figure 13a,b show the measured frequency variation of the ILFM that is changed by the supply voltage and temperature variation. It is measured using a Keysight spectrum analyzer E4440A. Figure 13a shows the result of spectrum measurement of ILFM without frequency calibration. When the voltage and the temperature change, the free-running frequency of the Ring Oscillator changes by about ±100MHz. Therefore, the output of the ILFM generates a large reference spurious tone, and the phase noise performance is not good. On the other hand, as Figure 13b shows, when the proposed Frequency Calibration Logic is used, the output frequency of ILFM is exactly calibrated to target frequency (846 MHz) at the supply voltage and temperature corner conditions.  Figure 14 shows the measured phase noise of the proposed ILFM using a Keysight signal source analyzer E5052A. When the short pulse is injected into the Ring Oscillator, the phase noise is −108 dBc/Hz at 1 MHz offset and the measured RMS jitter of the ILFM is 6.34 ps. When the ILFM is locked by injection, the phase noise is reduced more than the free-running noise. Furthermore, with the effect of the injection, in-band phase noise is also reduced. Table 1 shows the comparison with published papers [22][23][24]. The proposed paper is designed to generate a RF signal to the RF frontend for calibration purpose before the RF signal input from the antenna. The RF signals for calibrating I/Q mismatch do not require ultra-low jitter performance. The reference spur is generated by the ILFM, and it is attenuated by the baseband filter. The performance of the proposed paper with the highest priority is the reduction of the silicon area and current consumption. The definition of FOM is defined as follows: where Jitter rms , 1 s, and P diss are the RMS jitter value of ILFM output, 1 s, and the power consumption, respectively [23].

Conclusions
This paper presents a 612-1152 MHz Injection-Locked Frequency Multiplier (ILFM). The proposed ILFM is used to send an input signal to the receiver only in the I/Q mismatch calibration mode. Adopting a PLL to calibrate the receiver places a burden on this system because additional area and power consumption are required. Instead of the PLL, to satisfy high-frequency, low-jitter and low-area requirements, a Ring Oscillator is adopted in the system. The free-running frequency of the ILFM is automatically and digitally calibrated to reflect the frequency of the injected signal from the harmonics of the reference clock. To control the frequency of the ILFM, the load current is digitally tuned with a 6-bit digital control signal. The proposed ILFM locks to the target frequency using a digitally controlled FLL. The proposed ILFM is designed for I/Q mismatch calibration in sub-GHz RF receivers. The advantage of this chip is the minimized area and current consumption that result from adopting a simple FLL logic. The FOM of this ILFM is not as good as the reference paper due to its low power consumption. However, in this application, area and power consumption are more important than RMS jitter performance. The reference spurious is filtered by the baseband filter stage. This chip is fabricated using 1-poly 6-metal 0.18 µm CMOS and has achieved the wide tuning range of 612~1152 MHz. The power consumption is 0.95 mW from a supply voltage of 1.8 V. The measured phase noise of the ILFM is −108 dBc/Hz at a 1 MHz offset.