A Compact Operational Amplifier with Load-Insensitive Stability Compensation for High-Precision Transducer Interface

High-resolution electronic interface circuits for transducers with nonlinear capacitive impedance need an operational amplifier, which is stable for a wide range of load capacitance. Such operational amplifier in a conventional design requires a large area for compensation capacitors, increasing costs and limiting applications. In order to address this problem, we present a gain-boosted two-stage operational amplifier, whose frequency response compensation capacitor size is insensitive to the load capacitance and also orders of magnitude smaller compared to the conventional Miller-compensation capacitor that often dominates chip area. By exploiting pole-zero cancellation between a gain-boosting stage and the main amplifier stage, the compensation capacitor of the proposed operational amplifier becomes less dependent of load capacitance, so that it can also operate with a wide range of load capacitance. A prototype operational amplifier designed in 0.13-μm complementary metal–oxide–semiconductor (CMOS) with a 400-fF compensation capacitor occupies 900-μm2 chip area and achieves 0.022–2.78-MHz unity gain bandwidth and over 65∘ phase margin with a load capacitance of 0.1–15 nF. The prototype amplifier consumes 7.6 μW from a single 1.0-V supply. For a given compensation capacitor size and a chip area, the prototype design demonstrates the best reported performance trade-off on unity gain bandwidth, maximum stable load capacitance, and power consumption.


Introduction
The internet of things (IoT) is a new paradigm, which connects any physical objects embedded with ambient computational intelligence to each other such that these objects can recognize others and exchange collected data [1][2][3]. With the advent of the Internet of Things, there has been an increasing demand on the transducers that are able to perform diverse functions such as sensors, actuators, and radio frequency identification tags, for a wide variety of applications including communication, imaging, display, finance, data centers, transportation, health-care, and biomedical devices [4][5][6][7][8][9][10].
In this paper, we present a gain-boosted two-stage operational amplifier, whose compensation capacitance size is less sensitive of load capacitance compared to the previously reported operational amplifiers. Compared to the PSS amplifier, rather than decreasing the first-stage gain [42], the proposed amplifier alternating-current-couples the first-stage and adds a gain-boosting stage to the second-stage input, which provides a higher flexibility in frequency compensation and also allows low-power operation and a higher unity-gain frequency. The compensation capacitor size of a prototype operational amplifier is up to four orders of magnitude smaller than the load capacitance. By combing the conventional Miller compensation with a pole-zero cancellation technique, compared to the previously reported high-gain operational amplifiers, the proposed operational amplifier allows the smallest compensation capacitor size for a given load capacitance [38][39][40][41][42][43].
The remainder of this paper is organized as follows. Section 2 reviews the previously known operational amplifier stability compensation techniques. Section 3 presents the operation and architectural analysis of the proposed operational amplifier with a novel stability compensation technique. The detailed circuit implementation and pole-zero cancellation analysis are given in Section 4. Simulation results and performance comparison with the present state-of-the-art are presented in Section 5. Concluding remarks are stated in Section 6.

Conventional Miller Compensation
Miller compensation, which has been extensively used in integrated operational amplifiers, deals with stability issues in frequency response by introducing capacitor C f in series with resistance R f between the input and output stage. Figure 1a illustrates the architecture of a two-stage amplifier using conventional Miller compensation [25,44]. Its transfer function from the input V in to the output V out is where the dominant pole ω p1 , second pole ω p2 and zero ω z are given as the pole splitting that the output pole is transfered to the second pole is achieved by the Miller compensation [25,44]. The zero can be moved to left half plane by increasing the compensating resistance value R f . Assuming that intrinsic capacitance C A is much smaller than load capacitance C L and compensation capacitance C f , the unity gain frequency ω u is g m1 /C f , results in To avoid the unity gain frequency higher than ω p2 , which may cause stability issues, the compensating capacitance must be designed larger than C L g m1 /g m2 . Therefore, the conventional Miller compensation topology meets tremendous challenges in driving large capacitive load with a limited footprint.  Figure 1. (a) Conventional Miller frequency compensation [25]. (b) Ahuja frequency compensation [26].
(Diagrams were redrawn with simplification in order to facilitate the comparison among different compensation techniques.)

Ahuja Compensation
An improved compensation technique was introduced by Ahuja. It utilizes the current transformer providing virtual ground to eliminate feed-forward path in Miller compensation [26], as shown in Figure 1b. The dominant pole ω p1 is lightly changed from (3) to while the second pole ω p2 now is which is higher than (4) [27]. The unity gain frequency ω u is still given by g m1 /C f . As a result, the ratio between the second pole ω p2 and unity gain frequency ω u is augmented to Compared to the conventional Miller compensation, a smaller compensating capacitance is required to drive a same load capacitance for a given phase margin. It copes better with heavy capacitive load [26,45]. However, this reduction is still heavily restricted by the capacitive load.

Conventional Feedforward Compensation
The feedforward compensation technique is introduced to obtain high-frequency performance by implementing pole-zero cancellation [46,47]. Its principle in a folded-cascode amplifier is illustrated in Figure 1c. Assuming poles are widely spread, the positions of zeros and poles are approximately given by where , and the r o is the output impedance of this amplifier [27]. For the amplifier without C f , the zero is much higher than the second pole as C BD2 is normally much smaller than the capacitors of the second pole. By inserting the feedforward capacitance C f , the zero ω z shifts to lower frequency and is practical to cancel the second pole ω p2 . However, due to the parasitic capacitances, mismatch between the zero and the second pole always exists. It should be noted that the second pole also shifts to lower position, because of C f , even though with a minor degree. Consequently, a relatively large C f is needed to alleviate this mismatch. This limitation can be relieved by adding a resistance R f in series with C f [27].

Pseudo Single-Stage Amplifier
The single-stage amplifier only have one high-impedance node at its output, that is why it can drive a large load capacitance without any stability issues. For the pseudo single-stage amplifier, an introduced intermediate resistance R m is paralleled with first-stage output impedance r o1 , as shown in Figure 1d, it significantly reduces the output impedance of first stage. Its dominant pole ω p1 and second pole ω p2 are obtained as because of the small R m , the second pole is much higher than the dominant pole [42]. This two-stage amplifier has a frequency response similar to a single-stage amplifier without compensation capacitance. However, this topology is implemented at the expense of insufficient DC voltage gain. This problem can be alleviated by adding a gain booster to the schematic. In summary, there are mainly two problems existing in these previous frequency compensation topologies. First, the size of compensation capacitor is tightly limited by the load capacitance. Specifically, for a 1-nF load capacitance, the compensation capacitance needed to address stability issues is conventionally larger than 10 pF, which occupies a large proportion of the chip area. In addition, these techniques are required to be optimized based on the single specific load capacitance. As a result, the wide range of load capacitance cannot be driven. In next section, a novel two-stage operational amplifier is introduced to solve these two problems by combing Miller compensation and pole-zero cancellation.

Proposed Architecture
The proposed operational amplifier architecture is illustrated in Figure 2. It consists of a main amplifier, a gain booster, and a Class-B output stage. In the main amplifier, the first stage transconductance g m1 is alternating-current (AC) coupled to the second stage transconductance g m2 through the capacitor C m , the voltage gain at point A is generated by the gain booster. The transfer function from the input where g ma and g mb are the transconductance, r oa1 and r oa2 are the output impedance, of the first and second stage of gain booster, respectively. r o1 is the output impedance of the first stage, and R m is the inter-stage load impedance, in main amplifier. Because of the Miller effect, the impedance of C f in series with R f is amplified by [1 + g mb (r oa2 ||R m )], where g mb (r oa2 ||R m ) is the DC voltage gain of the second stage of gain booster. The voltage gain between A and B is where r o2 is the output impedance of the second stage of main amplifier. Therefore, the overall transfer function from the input V in to the output V out is obtained as where g mB and r oB is the transconductance and output impedance of the Class-B output stage, respectively. Compared to other capacitors in this function, C B is much smaller and negligible. This function is approximated to where Note that ω pg is the dominant pole introduced by the gain booster, and ω zg is the zero of the gain booster. ω p1 is the amplifier output node pole, and ω p2 is the pole from node A, and g mB is the transconductance of the Class-B output stage. Figure 3 illustrates the frequency response of the proposed amplifier. The DC gain is boosted by g ma r oa1 . The gain booster not only increases the DC gain of the main amplifier, but also moves the dominant pole from ω p1 to ω pg , which is independent of C L , as shown in Equation (19). However, the extra pole from the gain booster output node reduces the overall phase margin. The Miller compensation by C f and R f in the gain booster alleviates this problem. The zero of the gain booster ω zg is designed to cancel the output node pole, ω p1 , by choosing a suitable C f and R f . The pole-zero cancellation enable the proposed work to drive a wide range of load capacitance. The compensation capacitor size comparison between the pseudo single-stage (PSS) amplifier amplifier and this work is given in Table 1. Compared to a PSS amplifier, by taking advantage of Miller compensation, the proposed amplifier reduces the compensation capacitor size by ten times while providing the same DC gain and unity gain bandwidth (UGBW).

PSS Amplifier [42]
This Work Note: The same second pole location and unity-gain bandwidth (UGBW) are assumed.
The stability of the operational amplifier is dominated by its phase margin, which is the difference between the phase and 180 • at the unity-gain cut-off frequency. For a two-pole system, assuming poles are widely spread, its phase margin (PM) is given as where the ω p1 and the ω p2 are the dominant and second pole respectively, the ω u is the unity gain frequency. For the proposed work, the phase margin is primarily determined by the pole from the node A, ω p2 , as shown in (21), which is not affected by the load capacitance C L . The capacitance at node A is much smaller than the compensation capacitance and load capacitance. The gain booster and R m raise the second pole location from 1/( where C A is approximately but less than (C 1 + C 2 ) and C m is designed to be much larger than C 1 and C 2 . Then the ratio between the second pole and the unity gain frequency is increased, which broadens the phase margin. Compared to the design without g m1 , the proposed amplifier moves ω p2 higher from 1/( . The comparison about frequency response bode plots among this work, the PSS amplifier [42] and the design without g m1 is shown in Figure 4. With same compensation and load capacitance, this work achieves a larger phase margin and wider unity gain bandwidth.  While the two-stage amplifier implementing conventional Miller compensation has a second pole determined by the load capacitance, as shown in Equation (4), the dominant and second pole of this work. which are shown in EquationS (19) and (21), are both independent of the load capacitance. As a result, this work can maintain a sufficient phase margin with various load capacitance, and this frequency compensation topology is less sensitive to the load capacitance compared to the conventional Miller compensation. Figure 5 shows the circuit of the proposed operational amplifier. Its transistor size is shown in Table 2. The composite cascode [48] is used as input stage in both the main amplifier and the gain booster in order to obtain sufficient DC voltage gain. Compared to the single transistor with doubled length, the composite pair can provide higher gain. A previous work indicated that the voltage gain exceeding 80 dB per stage can be achieved by the composite cascode configuration with transistors operating in weak or moderate inversion domain [49]. A Class-B output stage is implemented to provide a fast settling time by improving the amplifier slew rate.  Figure 5. Schematic of the proposed gain-boosted two-stage operational amplifier with load-insensitive stability compensation. Design parameters of the proposed amplifier are shown in Table 3. The inter-stage load resistance R m can be realized by a negative feedback loop as

Circuit Implementation
where the g mv is the transconductance of M 16 and M 17 , and the g mf is the transconductance of M 12 and M 13 [42]. The R m is optimized though choosing suitable g mv and g mf to make the second pole ω p2 much higher than unity gain frequency to obtain sufficient phase margin. R f is replaced by floating tunable CMOS resistors to reduce the chip area [50]. The bias circuit for this work is illustrated in Figure A1 and Table A1.

Pole-Zero Cancellation and Sensitivity Analysis
In order to drive a wide range of load capacitance, ω zg is designed to cancel ω p1 with a load capacitance in-between 0.1 nF and 15 nF, as shown in Figure 6. the ω zg is designed lower than the output node pole ω p1 with minimum load capacitance, which is 0.1 nF. With the increase of load capacitance, the ω p1 gets lower and the precise pole-zero cancellation occurs. Then as the load capacitance further increases, the ω p1 get smaller than the ω zg , and the precise pole-zero cancellation condition is broken, as a result, the phase margin become worse. To prevent a large degradation in the amplifier phase margin, the zero is designed to cancel the ω p1 with 1-nF load capacitance. Since a precise pole-zero cancellation is difficult to realize, especially when the load capacitance has a large variation, the pole-zero doublet of ω p1 and ω zg may degrade the settling time.  The effect of Miller compensation capacitance variation on the precise pole-zero cancellation is illustrated in Figure 7. The variation on C f causes a change on both zero and pole introduced by the gain booster, then the unity gain frequency is also changed, while the second pole is fixed. For a +10% change, both ω zg and ω bg is decreased by 10%, while the ratio between second pole and unity gain frequency is enlarged result in wider phase margin. In contrast, for a −10% variation, both ω zg and ω bg in increased by 10%, and phase margin is degenerated. The change on the unity gain frequency is approximately obtained as where a is the variation on C f . Because the unity gain frequency ω u is much higher than ω p1 , which is 1/(C f R f ), compared to ω u , ∆ω u is negligible. Consequently, the pole-zero cancellation is insensitive to the variation on Miller compensation capacitance.

Common-Mode Rejection Ratio Analysis
The common-mode rejection ratio (CMRR) of the differential amplifier reflects its ability of rejecting identical signal components on both inputs. The CMRR is defined as where A DM is the differential-mode gain and A CM is the common-mode gain. It determines the attenuation applied to the noise from environment. The high CMRR is crucial for the instruments which usually work in noisy environment. For the proposed amplifier, its common-mode rejection ratio at low frequency is typically determined by the first stage of the gain booster. Assuming that the intrinsic gain of the transistor g m r o is much larger than one, the differential-mode gain of this stage is approximately obtained as A DM,gb1 g m25 (g m27 r o27 r o25 || g m29 r o29 r o31 ), (26) while its common-mode gain is approximated as Then the CMRR of the proposed work at DC is which is close to the simulated CMRR of 109 dB.

Simulation Results and Discussion
The proposed amplifier is designed using a 130-nm CMOS technology with a total area of 0.00090 mm 2 . Its layout is shown in Figure 8. The proposed amplifier without bias circuit occupies 0.00073-mm 2 chip area. The total stability compensation area is 100 µm 2 .
The stability simulation with 0.05-17 nF load capacitance over Miller compensation capacitances variations are shown in Figures 9 and 10 and Tables 4 and 5. For the prototype amplifier, the maximum phase margin is achieved when load capacitance C L is 2.5 nF, which is 91 • . The phase margin larger than 70 • with a load capacitance of 0.2-12 nF and it becomes less than 65 • when the load capacitance exceeds the 0.1-15-nF range. With the 30% variation on Miller compensation capacitance, the largest change in phase margin is less than 8% and demonstrates a good tolerance on process variation.      The simulated frequency response with a 2.5-nF load capacitance is shown in Figure 11, demonstrating 130-kHz unity-gain frequency and over 100-dB gain at DC. The frequency response of the amplifier without the gain booster is separately simulated, which is labeled as g m1 + g m2 , showing a significant DC gain drop as expected from the AC coupling between g m1 and g m2 . In addition, the frequency response of the amplifier without the first stage of the main amplifier (g m1 ) is also simulated, which is labeled as GB + g m2 , showing 16 • degradation in the phase margin. It also shows that the first stage transconductance allows the overall amplifier to provide a sufficient gain at the frequencies higher than 50 kHz. Figure 12 shows the comparison of simulated frequency response among this work, the pseudo single-stage (PSS) amplifier and the design without C m using total compensation capacitance of 400-fF. Because the 400-fF compensation capacitance is far from sufficient for the PSS amplifier to implement pole-zero cancellation, its phase margin is degenerated severely. Figure 11. Simulated frequency response of the proposed amplifier with 2.5-nF load capacitance. Figure 12. Comparison of simulated frequency response among this work, the PSS amplifier [42] and the design without C m with 2.5-nF load capacitance and 400-fF total compensation capacitance. Figure 13 illustrates the simulated frequency response of the proposed amplifier with 0.1-nF, 1-nF and 15-nF load capacitances, respectively. The precise pole-zero cancellation occurs when load capacitance is 1 nF. The frequency response for 0.1-nF load capacitance shows that the pole of the gain booster, ω gz is lower than the output node pole ω p1 , while ω gz is higher than ω p1 when load capacitance is 15 nF. The broken pole-zero cancellation reflected in Figure 13 accords with the analysis in previous section. The simulated common-mode rejection ratio (CMRR) is given in Figure 14, which is 109 dB at DC. At low frequency, the high CMRR is mainly contributed by the first stage of the gain booster, which is a differential composite cascode amplifier, since the first and second stage of the main amplifier are AC coupled by C m . With the increase of frequency, the first stage of the main amplifier begins to make a difference to the CMRR. Owing to this, the proposed work obtains a sufficient CMRR at high frequency.   Figure 15, a step response simulation with various load capacitance is shown in Figure 16, and the simulated 1% settling time with variation on Miller compensation capacitor C f is shown in Figure 17. The 1% settling time is damaged due to exceeding-80 • phase margin when driving 1-7-nF load capacitance. With the diminution of C f , the phase margin decreases, then the 1% settling time is improved.  The input common-mode range (ICMR) and output swing of the proposed amplifier are shown in Figure 18. The input common range is from 0.49 V to 0.64 V, and the output bias voltage swings between 0.34 V and 0.68 V. Considering that the Class-B output stage may cause the distortion of output signal, the simulated total harmonic distortion (THD) with 40-mVpp differential input when load capacitance is 0.1 nF, 1 nF and 15 nF is shown in Figure 19. The largest total harmonic distortion is −114 dB, while the DC voltage gain is 103 dB.  Monte Carlo simulations with 50 samples for DC gain, unity gain bandwidth and phase margin with 1-nF load capacitance are shown in Figure 20. The median performance of 97.5-dB gain, 293.5-kHz unity gain frequency, and 87.4 • phase margin is obtained with a standard deviation of 10.7 dB, 82.2 kHz, and 16.8 • . Considering the limited number of samples, the median performance of the Monte Carlo simulation well matches the simulation results with typical case model. Figure 20c shows that the prototype remains stable with 2σ variation. In addition, the corner simulation performed with one σ process variation presents 110.3-dB gain, 329.9-kHz unity gain bandwidth and 82 • phase margin at high side and 95.5-dB gain, 227.3-kHz unity gain band width and 93 • phase margin at low side, which also matches the statistical distributions from the Monte Carlo simulation. Table 6 compares the simulated performance of the prototype design with the state-of-the-art. Compared to previous works, this work utilizes the smallest compensation capacitance, which is 400 fF, and demonstrates the highest ratio between load capacitance and total compensation capacitance, which is 37,500. In addition, it also presents the best reported performance trade-off on the unity gain bandwidth, load capacitance, and power consumption for a given chip area, as shown in Figure 21.  FoM L = (SlewRate · C L )/Power FoM S = (UGBW · C L )/Power [37]. LC-FoM L = (SlewRate · C L )/(Power · C T ) LC-FoM S = (UGBW · C L )/(Power · C T ) [41]. FoM 1 = (SlewRate · C L )/(Power · ChipArea) FoM 2 = (UGBW · C L )/(Power · ChipArea) [51].

Conclusions
Transducers with nonlinear capacitive input impedance need an operational amplifier, which is stable for a wide range of load capacitance. Such an operational amplifier in a conventional design requires a large area for compensation capacitors, increasing costs and limiting applications. In order to address this problem, we present a gain-boosted two-stage operational amplifier, whose frequency response compensation is less sensitive to the load capacitance compared to the conventional Miller frequency compensation. The proposed amplifier cancels the output node pole of the main amplifier stage by the zero of the gain booster, so that a sufficient phase margin can be achieved without using a large compensation capacitor. A prototype CMOS amplifier designed with the proposed architecture uses two-to-four orders of magnitude smaller compensation capacitor compared to the load capacitance. This advantage in the compensation capacitor area requirement extends the applications of the proposed operational amplifier beyond the transducer interface circuits and may benefit general analog integrated circuit applications. The prototype CMOS operational amplifier demonstrates the highest performance trade-off to date when considering unity-gain bandwidth, load capacitance, power consumption, and chip area, which can enable an a compact low-cost transducer interface with unprecedentedly high resolution for emerging applications. It should be also noted that the proposed operational amplifier design technique can be used not only with monolithically integrated transducer interface circuits but also with transducer interface circuits assembled by discrete off-the-shelf components.

Abbreviations
The following abbreviations are used in this manuscript: The bias circuit implemented in this work is illustrated in Figure A1 and Table A1. I 1 is the supply independent biasing current, which is 50 nA when V DD is 1 V.  Figure A1. Bias circuit for the proposed work. Table A1. Transistors size of the bias circuit.