An Over 90 dB Intra-Scene Single-Exposure Dynamic Range CMOS Image Sensor Using a 3.0 μm Triple-Gain Pixel Fabricated in a Standard BSI Process †

To respond to the high demand for high dynamic range imaging suitable for moving objects with few artifacts, we have developed a single-exposure dynamic range image sensor by introducing a triple-gain pixel and a low noise dual-gain readout circuit. The developed 3 μm pixel is capable of having three conversion gains. Introducing a new split-pinned photodiode structure, linear full well reaches 40 ke−. Readout noise under the highest pixel gain condition is 1 e− with a low noise readout circuit. Merging two signals, one with high pixel gain and high analog gain, and the other with low pixel gain and low analog gain, a single exposure dynamic rage (SEHDR) signal is obtained. Using this technology, a 1/2.7”, 2M-pixel CMOS image sensor has been developed and characterized. The image sensor also employs an on-chip linearization function, yielding a 16-bit linear signal at 60 fps, and an intra-scene dynamic range of higher than 90 dB was successfully demonstrated. This SEHDR approach inherently mitigates the artifacts from moving objects or time-varying light sources that can appear in the multiple exposure high dynamic range (MEHDR) approach.


Introduction
High image quality in low light conditions is highly appreciated in many applications, such as security, surveillance, automotive, and IPC applications, to name a few. On the other hand, high sensitivity to low-light objects is also required in these applications. In low light conditions, image sensors are usually operated in a high gain mode, and image quality suffers from low signal saturation due to the limited dynamic range. Many approaches have been introduced in order to expand the image sensor dynamic range while keeping low light image quality, including multiple exposure [1][2][3][4], logarithmic compression [5,6], knee compression [7], multiple column gain readout [8], and more [9,10].

Dual Gain Readout Sequence
To obtain a linearized high dynamic range signal, the same photodiode signal is read out twice with different pixel gains. Figure 2 shows a pixel operation timing for the dual pixel gain readout. Firstly, RST, BIN1 and BIN2 switches are all turned on to initialize voltage of the vertical binning node and the charge detection node. After the RST switch is turned off, a low pixel gain (LPG) offset signal is sampled as RST SH (Low pixel gain). Next, BIN1 and BIN2 switches are turned off, and high pixel gain (HPG) offset, RST (High pixel gain) is sampled. A first charge transfer pulse is applied on the transfer gate, TG; then, the HPG signal, SIG SH (High pixel gain) is sampled. LPG signal is obtained after BIN1 and BIN2 are turned on again, and sampled as SIG SH (Low pixel gain). Before the LPG signal readout, the second transfer pulse is applied to the TG gate so that remaining charge in the photodiode is transferred to the charge detection node in case of high light conditions. When BIN1 and BIN2 switches are turned on again, offset charge in the charge detection node is recombined to the same condition as the RST SH (Low pixel gain); therefore, correlated double sampling (CDS) is realized for LPG signal readout as well as the HPG. When the BIN2 switch is turned off (dotted line in Figure 2) during the signal readout period, the pixel operates in the middle pixel gain (MPG) condition.

Charge detection node
Binning node

Dual Gain Readout Sequence
To obtain a linearized high dynamic range signal, the same photodiode signal is read out twice with different pixel gains. Figure 2 shows a pixel operation timing for the dual pixel gain readout. Firstly, RST, BIN1 and BIN2 switches are all turned on to initialize voltage of the vertical binning node and the charge detection node. After the RST switch is turned off, a low pixel gain (LPG) offset signal is sampled as RST SH (Low pixel gain). Next, BIN1 and BIN2 switches are turned off, and high pixel gain (HPG) offset, RST (High pixel gain) is sampled. A first charge transfer pulse is applied on the transfer gate, TG; then, the HPG signal, SIG SH (High pixel gain) is sampled. LPG signal is obtained after BIN1 and BIN2 are turned on again, and sampled as SIG SH (Low pixel gain). Before the LPG signal readout, the second transfer pulse is applied to the TG gate so that remaining charge in the photodiode is transferred to the charge detection node in case of high light conditions. When BIN1 and BIN2 switches are turned on again, offset charge in the charge detection node is re-combined to the same condition as the RST SH (Low pixel gain); therefore, correlated double sampling (CDS) is realized for LPG signal readout as well as the HPG. When the BIN2 switch is turned off (dotted line in Figure 2) during the signal readout period, the pixel operates in the middle pixel gain (MPG) condition.

Figure 2.
Pixel and switch control timing sequence for dual gain pixel readout with a combination of LPG mode and the HPG mode. When BIN2 switch timing is changed to the dotted line, the middle pixel gain MPG signal is obtained.

High Linear Full Well (LFW) Photodiode
A conventional pinned photodiode (PPD [19]) structure, the proposed photodiode structure and a conventional split-pinned diode structure are shown in Figure 3a-c, respectively. In the presented structure, Figure 3b, a P-type layer is formed in the center of PPD, like a P-type pixel isolation layer. Because of the narrow photodiode effect, the split photodiode structure is effective for maintaining a low Vpin when the LFWC is increased by additional dosage for the N-type photodiode. The conventional split photodiode structure [20], which has 2 sets of PPDs and a transfer gate and one floating diffusion node per pixel, is shown in Figure 3c for comparison. The stratified PPD structure [21], which has vertically stacked P-type layers, is considered a reference of this type of PPD structure.   Figure 3a for both the conventional PPD and the presented one. In the simple P + /N step junction model, the depletion layer width Wd in PPD is expressed as Equation (1), where ε is the semiconductor dielectric constant, Vpin the pinning voltage when the PPD is fully depleted, Nd the N dopant concertation, and φbi the built-in potential.
Equation (1) suggests that the Wd (fully depleted region) becomes narrower in the presented structure in Figure 3b due to the additional P-type layer between the split PPDs. Thus, the Vpin to fully deplete the PPD can be lower than for the conventional structure shown in Figure 3a, even with the

High Linear Full Well (LFW) Photodiode
A conventional pinned photodiode (PPD [19]) structure, the proposed photodiode structure and a conventional split-pinned diode structure are shown in Figure 3a-c, respectively. In the presented structure, Figure 3b, a P-type layer is formed in the center of PPD, like a P-type pixel isolation layer. Because of the narrow photodiode effect, the split photodiode structure is effective for maintaining a low V pin when the LFWC is increased by additional dosage for the N-type photodiode. The conventional split photodiode structure [20], which has 2 sets of PPDs and a transfer gate and one floating diffusion node per pixel, is shown in Figure 3c for comparison. The stratified PPD structure [21], which has vertically stacked P-type layers, is considered a reference of this type of PPD structure.

High Linear Full Well (LFW) Photodiode
A conventional pinned photodiode (PPD [19]) structure, the proposed photodiode structure and a conventional split-pinned diode structure are shown in Figure 3a-c, respectively. In the presented structure, Figure 3b, a P-type layer is formed in the center of PPD, like a P-type pixel isolation layer. Because of the narrow photodiode effect, the split photodiode structure is effective for maintaining a low Vpin when the LFWC is increased by additional dosage for the N-type photodiode. The conventional split photodiode structure [20], which has 2 sets of PPDs and a transfer gate and one floating diffusion node per pixel, is shown in Figure 3c for comparison. The stratified PPD structure [21], which has vertically stacked P-type layers, is considered a reference of this type of PPD structure.   Figure 3a for both the conventional PPD and the presented one. In the simple P + /N step junction model, the depletion layer width Wd in PPD is expressed as Equation (1), where ε is the semiconductor dielectric constant, Vpin the pinning voltage when the PPD is fully depleted, Nd the N dopant concertation, and φbi the built-in potential.
Equation (1) suggests that the Wd (fully depleted region) becomes narrower in the presented structure in Figure 3b due to the additional P-type layer between the split PPDs. Thus, the Vpin to fully deplete the PPD can be lower than for the conventional structure shown in Figure 3a, even with the    Figure 3a for both the conventional PPD and the presented one. In the simple P + /N step junction model, the depletion layer width W d in PPD is expressed as Equation (1), where ε is the semiconductor dielectric constant, V pin the pinning voltage when the PPD is fully depleted, N d the N dopant concertation, and ϕ bi the built-in potential. LFWC with the same Vpin as that of the conventional PPD. Figure 5 shows the PPD width dependence of the pinned potential and the peak potential depth, as obtained by a 2D device simulation. The results show that the location of the potential peak shifts deeper and the peak potential increases as the PPD width is increased. This suggests that it is difficult to boost LFWC with a large PPD by increasing the N dopant without changing Vpin or supplying voltage. This is a benefit of the presented PPD structure, which only uses a narrow PPD width.   A photo-electron conversion plot for this pixel is shown in Figure 6. A linear full well capacity (LFWC) of 40 ke − and a full well capacity (FWC) of 45 ke − were obtained with good linearity. In this paper, LFWC is defined as signal electrons measured at the shot noise peak point. Above LFWC, random noise decreases because of pixel saturation. Also, FWC is defined as signal electrons corresponding to PD saturation. Equation (1) suggests that the W d (fully depleted region) becomes narrower in the presented structure in Figure 3b due to the additional P-type layer between the split PPDs. Thus, the V pin to fully deplete the PPD can be lower than for the conventional structure shown in Figure 3a, even with the same N dopant, N d . This means that the proposed structure allows N d to be increased in order to boost LFWC with the same V pin as that of the conventional PPD. Figure 5 shows the PPD width dependence of the pinned potential and the peak potential depth, as obtained by a 2D device simulation. The results show that the location of the potential peak shifts deeper and the peak potential increases as the PPD width is increased. This suggests that it is difficult to boost LFWC with a large PPD by increasing the N dopant without changing V pin or supplying voltage. This is a benefit of the presented PPD structure, which only uses a narrow PPD width. same N dopant, Nd. This means that the proposed structure allows Nd to be increased in order to boost LFWC with the same Vpin as that of the conventional PPD. Figure 5 shows the PPD width dependence of the pinned potential and the peak potential depth, as obtained by a 2D device simulation. The results show that the location of the potential peak shifts deeper and the peak potential increases as the PPD width is increased. This suggests that it is difficult to boost LFWC with a large PPD by increasing the N dopant without changing Vpin or supplying voltage. This is a benefit of the presented PPD structure, which only uses a narrow PPD width.   A photo-electron conversion plot for this pixel is shown in Figure 6. A linear full well capacity (LFWC) of 40 ke − and a full well capacity (FWC) of 45 ke − were obtained with good linearity. In this paper, LFWC is defined as signal electrons measured at the shot noise peak point. Above LFWC, random noise decreases because of pixel saturation. Also, FWC is defined as signal electrons corresponding to PD saturation. A photo-electron conversion plot for this pixel is shown in Figure 6. A linear full well capacity (LFWC) of 40 ke − and a full well capacity (FWC) of 45 ke − were obtained with good linearity. In this paper, LFWC is defined as signal electrons measured at the shot noise peak point. Above LFWC, random noise decreases because of pixel saturation. Also, FWC is defined as signal electrons corresponding to PD saturation.

Sensor Architecture
Top architecture of the image sensor is shown in Figure 7. Odd column pixels and even column pixels have individual TG control lines TG1a/TG1b and TG2a/TG2b, so that even and odd column pixels are read out serially, which allows us to assign one signal chain for two pixel columns. The column signal chain consists of an amplifier array, a 13 bit successive approximation register (SAR) ADC array and column memory. The column amplifier has two separated signal input paths, which enables two independent CDS operations with different gains. In combination with the multiple-gain pixel and the dual-gain column amplifier, flexible control with a wide gain ratio is available. For the LPG readout, an amplifier gain of either 1× or 2× can be chosen, and for the HPG readout, amplifier gains of 1×, 2×, 4×, 8× are selectable.

Sensor Architecture
Top architecture of the image sensor is shown in Figure 7. Odd column pixels and even column pixels have individual TG control lines TG1a/TG1b and TG2a/TG2b, so that even and odd column pixels are read out serially, which allows us to assign one signal chain for two pixel columns.

Sensor Architecture
Top architecture of the image sensor is shown in Figure 7. Odd column pixels and even column pixels have individual TG control lines TG1a/TG1b and TG2a/TG2b, so that even and odd column pixels are read out serially, which allows us to assign one signal chain for two pixel columns. The column signal chain consists of an amplifier array, a 13 bit successive approximation register (SAR) ADC array and column memory. The column amplifier has two separated signal input paths, which enables two independent CDS operations with different gains. In combination with the multiple-gain pixel and the dual-gain column amplifier, flexible control with a wide gain ratio is available. For the LPG readout, an amplifier gain of either 1× or 2× can be chosen, and for the HPG readout, amplifier gains of 1×, 2×, 4×, 8× are selectable. The column signal chain consists of an amplifier array, a 13 bit successive approximation register (SAR) ADC array and column memory. The column amplifier has two separated signal input paths, which enables two independent CDS operations with different gains. In combination with the multiple-gain pixel and the dual-gain column amplifier, flexible control with a wide gain ratio is After A/D conversion, the two sets of signals are fed to an on-chip digital processor, yielding a high dynamic range 16 bit linear signal. Finally, the 16 bit linear signals or compressed 12 bit signals are output through 4-lane MIPI or SLVS interface. The image sensor is capable of operating at 120 fps in a normal signal readout mode, or 60 fps in the SEHDR mode.

Fabrication and Characterization Results
The sensor is fabricated in a 65 nm BSI CMOS image sensor process, and assembled in a 48-pin PLCC package as shown in Figure 8. After A/D conversion, the two sets of signals are fed to an on-chip digital processor, yielding a high dynamic range 16 bit linear signal. Finally, the 16 bit linear signals or compressed 12 bit signals are output through 4-lane MIPI or SLVS interface. The image sensor is capable of operating at 120 fps in a normal signal readout mode, or 60 fps in the SEHDR mode.

Fabrication and Characterization Results
The sensor is fabricated in a 65 nm BSI CMOS image sensor process, and assembled in a 48-pin PLCC package as shown in Figure 8.
Photo conversion characteristics in the normal mode are shown in Figure 9. Pixel conversion gains in the HPG condition, the MPG condition and the LPG condition were measured as 152 μV/e − , 38 μV/e − and 21 μV/e − , respectively. Using the MPG as reference for a base pixel gain, the pixel gain ratio is 4.0:1:0.57.    After A/D conversion, the two sets of signals are fed to an on-chip digital processor, yielding a high dynamic range 16 bit linear signal. Finally, the 16 bit linear signals or compressed 12 bit signals are output through 4-lane MIPI or SLVS interface. The image sensor is capable of operating at 120 fps in a normal signal readout mode, or 60 fps in the SEHDR mode.

Fabrication and Characterization Results
The sensor is fabricated in a 65 nm BSI CMOS image sensor process, and assembled in a 48-pin PLCC package as shown in Figure 8.
Photo conversion characteristics in the normal mode are shown in Figure 9. Pixel conversion gains in the HPG condition, the MPG condition and the LPG condition were measured as 152 μV/e − , 38 μV/e − and 21 μV/e − , respectively. Using the MPG as reference for a base pixel gain, the pixel gain ratio is 4.0:1:0.57.     at the highest gain setting of 1.1 e − . The ADC window was set at 40 ke − , so that maximum dynamic range of 91 dB was obtained. The number of signal electrons at the conjunction point of the HPG signal and the LPG signal was about 800 e − .
The signal exhibits linear characteristics in the whole range from lower than 1e -to the saturation level, suggesting that the charge transfer error from the photodiode to the charge detection node is smaller than 1 e − , and therefore that the sensor shows excellent low light linearity.
Random noise, pixel FPN and column FPN are also plotted in Figure 10. Column FPN in low exposure conditions is lower than 1/20 of the random noise, and one can hardly see it. When the amplifier gain is changed at the conjunction point, excess noise and excess FPN are generated due to its circuit operation, and the excess random noise affects SNR by −8 dB. Except for the excess noise, random noise characteristics follow the shot noise model of S -0.5 throughout the whole range, where S is averaged signal. In comparison to the MEHDR scheme, no significant noise at the conjunction point is seen. When we suppose 1:1/32 integration time ratio in the MEHDR scheme, shot noise degrades about 15 dB at the conjunction point as illustrated by the dotted line in the figure. This is one of benefits of the SEHDR scheme, because no signal charges are lost. The photo response non-uniformity (PRNU) of the sensor is lower than 0.5%, which suggests that the process variations of the gate capacitance and parasitic metal capacitance are small enough to be used for pixel capacitance. Figure 11a,b shows images captured in the conventional MEHDR mode and in the SEHDR mode reported in this paper, respectively. Motion artifacts and LED flicker artifacts are clearly suppressed in the single-exposure image. The signal exhibits linear characteristics in the whole range from lower than 1e − to the saturation level, suggesting that the charge transfer error from the photodiode to the charge detection node is smaller than 1 e − , and therefore that the sensor shows excellent low light linearity.
Random noise, pixel FPN and column FPN are also plotted in Figure 10. Column FPN in low exposure conditions is lower than 1/20 of the random noise, and one can hardly see it. When the amplifier gain is changed at the conjunction point, excess noise and excess FPN are generated due to its circuit operation, and the excess random noise affects SNR by −8 dB. Except for the excess noise, random noise characteristics follow the shot noise model of ∝S −0.5 throughout the whole range, where S is averaged signal. In comparison to the MEHDR scheme, no significant noise at the conjunction point is seen. When we suppose 1:1/32 integration time ratio in the MEHDR scheme, shot noise degrades about 15 dB at the conjunction point as illustrated by the dotted line in the figure. This is one of benefits of the SEHDR scheme, because no signal charges are lost.
The photo response non-uniformity (PRNU) of the sensor is lower than 0.5%, which suggests that the process variations of the gate capacitance and parasitic metal capacitance are small enough to be used for pixel capacitance. Figure 11a,b shows images captured in the conventional MEHDR mode and in the SEHDR mode reported in this paper, respectively. Motion artifacts and LED flicker artifacts are clearly suppressed in the single-exposure image.

Conclusions
An image sensor that has an SEHDR feature was reported. By introducing a triple-conversion gain pixel and a dual-gain readout scheme, the sensor is able to cover an intra-scene dynamic range wider than 87 dB in MPG + HCG mode, and 91 dB in LPG + HCG mode. Because of there being no signal loss in high light conditions, there is no significant SNR drop at the conjunction point. In addition, the SEHDR scheme mitigates moving artifacts or flicker artifact in high dynamic range image applications. Specs and performance are summarized in Table 1.

Conclusions
An image sensor that has an SEHDR feature was reported. By introducing a triple-conversion gain pixel and a dual-gain readout scheme, the sensor is able to cover an intra-scene dynamic range wider than 87 dB in MPG + HCG mode, and 91 dB in LPG + HCG mode. Because of there being no signal loss in high light conditions, there is no significant SNR drop at the conjunction point. In addition, the SEHDR scheme mitigates moving artifacts or flicker artifact in high dynamic range image applications. Specs and performance are summarized in Table 1. Author Contributions: Isao Takayanagi convinced first generation architecture, supervised whole design of the device and wrote manuscript. Norio Yoshimura managed overall design project, created analog architecture and designed analog circuit. Kazuya Mori conceived the photodiode architecture, handled device simulation and pixel characterization, and wrote manuscript of the pixel part. Shinichiro Matsuo led overall logic design tasks including timing definition, module definition, digital top architecture and design verification. Shunsuke Tanaka handled process design and optical design. Hirofumi Abe supervised top level layout and package design. Naoto Yasuda integrated analog layout, and handled layout verification. Kenichiro Ishikawa handled sensor characterization, analysis and basic data acquisition. Shunsuke Okura conceived pixel configuration and operation schemes. Shinji Ohsawa supervised overall characterization, debug, analysis, and data acquisition for the manuscript. Toshinori Otaka analyzed SEHDR performance and optimized pixel operating condition.

Conflicts of Interest:
The authors declare no conflict of interest.