Resonance Frequency Readout Circuit for a 900 MHz SAW Device

A monolithic resonance frequency readout circuit with high resolution and short measurement time is presented for a 900 MHz RF surface acoustic wave (SAW) sensor. The readout circuit is composed of a fractional-N phase-locked loop (PLL) as the stimulus source to the SAW device and a phase-based resonance frequency detecting circuit using successive approximation (SAR). A new resonance frequency searching strategy has been proposed based on the fact that the SAW device phase-frequency response crosses zero monotonically around the resonance frequency. A dedicated instant phase difference detecting circuit is adopted to facilitate the fast SAR operation for resonance frequency searching. The readout circuit has been implemented in 180 nm CMOS technology with a core area of 3.24 mm2. In the experiment, it works with a 900 MHz SAW resonator with a quality factor of Q = 130. Experimental results show that the readout circuit consumes 7 mW power from 1.6 V supply. The frequency resolution is 733 Hz, and the relative accuracy is 0.82 ppm, and it takes 0.48 ms to complete one measurement. Compared to the previous results in the literature, this work has achieved the shortest measurement time with a trade-off between measurement accuracy and measurement time.


Introduction
The surface acoustic wave (SAW) sensor is a promising multi-functional sensor for pressure [1], mass [2] and temperature [3] measurement in Internet-of-everything (IoE), labs-on-a-chip, biomedical applications [4][5][6][7][8][9]. A SAW device is composed of a piezoelectric substrate and inter-digital transducers (IDT) deposited on the substrate [10]. A resonance frequency readout circuit is required to convert the sensor resonance frequency, which is correlated to the specific physical parameter of the SAW device under measurement, into digital numbers for further processing. Many of the recently published MEMS resonance sensors operate with frequencies in the MHz range [11][12][13][14][15][16], while some others work at a few GHz [17,18]. In this work, the resonance frequency readout circuit has been designed for a 900 MHz one-port SAW device presented in [19] which has a trade-off between the power consumption and the sensitivity consistency. The one-port SAW device in the experiment was fabricated on a LiNbO 3 /SiO 2 /Si substrate based on the ion implantation and the wafer bonding. The first step is to implant He + ions into a LiNbO 3 wafer. Then a SiO 2 layer is deposited on a Si wafer. The two prepared wafers are cleaned and bonded together and the bonded pair is heated. Finally, a thin layer of single-crystal LiNbO 3 is split off from the original LiNbO 3 wafer and stays on the surface of the SiO 2 /Si structure. A further annealing step is used to increase the bonding strength. Finally, a chemical-mechanical polishing (CMP) process is adopted to smooth the surface of With a SAW resonator as the load, the driving amplifier shows the parallel resonance at the frequency fp and the series resonance at the frequency fs. As shown in Figure 2, the driving amplifier's amplitude-frequency response has a peak around fp and a notch around fs. With a measurement circuit with limited voltage resolution, it is desired to choose the parallel resonance for the magnitude measurement. Hence the readout circuit in this work is designed to measure the parallel resonance frequency, and the "resonance frequency" f0 in the remaining part of this paper refers to the parallel resonance frequency fp. In this work, a phase-based new architecture is proposed to optimize the measurement time and frequency resolution at the same time, and its block diagram is shown in Figure 3. A fractional-N PLL with high frequency resolution is employed as the frequency generator. The sensor serves as the load of the output driving circuit (driver). The base of this method is the phase difference Δφ between the driver input and output signals, which is zero around the SAW device resonance frequency f0, as illustrated in Figure 4.  With a SAW resonator as the load, the driving amplifier shows the parallel resonance at the frequency fp and the series resonance at the frequency fs. As shown in Figure 2, the driving amplifier's amplitude-frequency response has a peak around fp and a notch around fs. With a measurement circuit with limited voltage resolution, it is desired to choose the parallel resonance for the magnitude measurement. Hence the readout circuit in this work is designed to measure the parallel resonance frequency, and the "resonance frequency" f0 in the remaining part of this paper refers to the parallel resonance frequency fp. In this work, a phase-based new architecture is proposed to optimize the measurement time and frequency resolution at the same time, and its block diagram is shown in Figure 3. A fractional-N PLL with high frequency resolution is employed as the frequency generator. The sensor serves as the load of the output driving circuit (driver). The base of this method is the phase difference Δφ between the driver input and output signals, which is zero around the SAW device resonance frequency f0, as illustrated in Figure 4.  In this work, a phase-based new architecture is proposed to optimize the measurement time and frequency resolution at the same time, and its block diagram is shown in Figure 3. A fractional-N PLL with high frequency resolution is employed as the frequency generator. The sensor serves as the load of the output driving circuit (driver). The base of this method is the phase difference ∆ϕ between the driver input and output signals, which is zero around the SAW device resonance frequency f 0 , as illustrated in Figure 4. With a SAW resonator as the load, the driving amplifier shows the parallel resonance at the frequency fp and the series resonance at the frequency fs. As shown in Figure 2, the driving amplifier's amplitude-frequency response has a peak around fp and a notch around fs. With a measurement circuit with limited voltage resolution, it is desired to choose the parallel resonance for the magnitude measurement. Hence the readout circuit in this work is designed to measure the parallel resonance frequency, and the "resonance frequency" f0 in the remaining part of this paper refers to the parallel resonance frequency fp. Figure 2. Frequency response of a driving amplifier when loaded by a one-port SAW device (upper part: amplitude-frequency response, lower part: phase-frequency response).
In this work, a phase-based new architecture is proposed to optimize the measurement time and frequency resolution at the same time, and its block diagram is shown in Figure 3. A fractional-N PLL with high frequency resolution is employed as the frequency generator. The sensor serves as the load of the output driving circuit (driver). The base of this method is the phase difference Δφ between the driver input and output signals, which is zero around the SAW device resonance frequency f0, as illustrated in Figure 4.   The phase curve in Figure 4 is actually an enlarged view of Figure 2 around the parallel resonance frequency f p . ∆ϕ is the phase difference between the input and output of the SAW driver. The phase difference is monotonic and crosses zero right at the resonance frequency. The task of the resonance frequency readout is then to find the frequency that gives ∆ϕ = 0, and this is where the SAR algorithm comes in. The flow chart of the SAR algorithm is shown in the lower part of Figure 4. The frequency searching starts from an initial frequency range [f low , f high ], and the PLL/SAW driver output frequency is set to (f low + f high )/2 at beginning. If this frequency gives ∆ϕ < 0, then the next frequency range will be [f low , (f low + f high )/2]. Otherwise, the next frequency range will be [(f low + f high )/2, f high ]. This operation is repeated until the frequency searching range is less than the wanted frequency resolution ∆f min . As an example, Figure 4 shows how a three-step search goes. The idea of phase difference measurement for sensor readout can also be found in [27]. The key contribution of this work is that the phase difference is directly measured using the circuits presented in this paper, while in [27] the phase difference was measured using an indirect time-based method, which requires more measurement time. The phase curve in Figure 4 is actually an enlarged view of Figure 2 around the parallel resonance frequency fp. Δφ is the phase difference between the input and output of the SAW driver. The phase difference is monotonic and crosses zero right at the resonance frequency. The task of the resonance frequency readout is then to find the frequency that gives Δφ = 0, and this is where the SAR algorithm comes in. The flow chart of the SAR algorithm is shown in the lower part of Figure 4. The frequency searching starts from an initial frequency range [flow, fhigh], and the PLL/SAW driver output frequency is set to (flow + fhigh)/2 at beginning. If this frequency gives Δφ < 0, then the next frequency range will be [flow, (flow + fhigh) /2]. Otherwise, the next frequency range will be [(flow + fhigh) /2, fhigh]. This operation is repeated until the frequency searching range is less than the wanted frequency resolution Δfmin. As an example, Figure 4 shows how a three-step search goes. The idea of phase difference measurement for sensor readout can also be found in [27]. The key contribution of this work is that the phase difference is directly measured using the circuits presented in this paper, while in [27] the phase difference was measured using an indirect time-based method, which requires more measurement time. . The basic principle of the proposed architecture (upper part: the resonance frequency f0 corresponds to Δφ close to 0 in the phase-frequency response, the lower part: the flow chart to find the resonance frequency f0).

Circuit Architecture
The detailed block diagram of the readout circuit is shown in Figure 5. The left down part is the phase difference detecting circuit. A fractional-N PLL is used to generate the RF excitation. Both the input and output signals of the SAW driver are around GHz range. There are three critical parts in the readout circuit. The first one is the binary phase difference detecting circuit, which judges the sign of Δφ. The second one is the logic circuit, which controls the PLL output frequency to search for the resonance frequency with the SAR strategy. The third one is the fractional-N PLL as a stimulus source. The SAR operation starts between two frequencies fhigh and flow, which can guarantee to cover the resonance frequency, and in this design fhigh and flow are set to 816 MHz and 1008 MHz, respectively. Since the PLL fractional divider has finite resolution, the searching will stop if the frequency searching range reaches the least significant bit (LSB) step size of the PLL output frequency. The readout circuit frequency resolution is actually mostly determined by the PLL frequency setting resolution. . The basic principle of the proposed architecture (upper part: the resonance frequency f 0 corresponds to ∆ϕ close to 0 in the phase-frequency response, the lower part: the flow chart to find the resonance frequency f 0 ).

Circuit Architecture
The detailed block diagram of the readout circuit is shown in Figure 5. The left down part is the phase difference detecting circuit. A fractional-N PLL is used to generate the RF excitation. Both the input and output signals of the SAW driver are around GHz range. There are three critical parts in the readout circuit. The first one is the binary phase difference detecting circuit, which judges the sign of ∆ϕ. The second one is the logic circuit, which controls the PLL output frequency to search for the resonance frequency with the SAR strategy. The third one is the fractional-N PLL as a stimulus source. The SAR operation starts between two frequencies f high and f low , which can guarantee to cover the resonance frequency, and in this design f high and f low are set to 816 MHz and 1008 MHz, respectively. Since the PLL fractional divider has finite resolution, the searching will stop if the frequency searching range reaches the least significant bit (LSB) step size of the PLL output frequency. The readout circuit frequency resolution is actually mostly determined by the PLL frequency setting resolution. The VCO output frequency in the PLL is two times the SAW device resonance frequency, such that the quadrature signals can be easily generated. In Figure 5, the input frequency to the SAW device is denoted as fRF, and the PLL output frequency is then 2fRF. The PLL output frequency is divided by 2 to generate the quadrature signals P90RF = cos (2πfRFt) and P0RF = sin (2πfRFt). P90RF is sent to the SAW driver loaded by the SAW device (the "SAW + DRV" block in Figure 5). Compared to its input signal, the driver output has a phase difference denoted as Δφ. The input signal and the output signal of the driver can be written as If roughly assume fRF = 1 GHz and Δφ = 1°, the time difference between VRF1 and VRF2 is only 2.78 ps. It is definitely non-trivial to measure this tiny time difference. Frequency division is of no use here because the phase difference Δφ is also divided which is not desired. In this work, the down-mixers MIX1 and MIX2 are adopted to hold the value of Δφ while greatly reducing the input signal frequency of the phase difference detecting circuit. Both VRF1 and VRF2 are down-converted to the intermediate frequency (IF). If the desired IF frequency is fIF, another frequency signal VLF with a frequency equal to fRF-fIF is generated and sent to MIX1 and MIX2.
( ) The output signals of MIX1 and MIX2 are given as follows Both mixers' output signals pass through a low-pass filter (LPF), and the generated IF signals VIF1 and VIF2 are given as It is clearly seen that the phase difference Δφ between VRF1 and VRF2 is converted to the same phase difference between the IF signals VIF1 and VIF2. Again take Δφ = 1° as a numerical example. If the IF frequency fIF is 200 kHz, after down-conversion, the time difference between VIF1 and VIF2 is now 13.9 ns, and this time difference can be easily measured. In this design, the IF signal time difference is detected by a digital bang-bang phase detector (BBPD) afterwards. The VCO output frequency in the PLL is two times the SAW device resonance frequency, such that the quadrature signals can be easily generated. In Figure 5, the input frequency to the SAW device is denoted as f RF , and the PLL output frequency is then 2f RF . The PLL output frequency is divided by 2 to generate the quadrature signals P90 RF = cos (2πf RF t) and P0 RF = sin (2πf RF t). P90 RF is sent to the SAW driver loaded by the SAW device (the "SAW + DRV" block in Figure 5). Compared to its input signal, the driver output has a phase difference denoted as ∆ϕ. The input signal and the output signal of the driver can be written as If roughly assume f RF = 1 GHz and ∆ϕ = 1 • , the time difference between V RF1 and V RF2 is only 2.78 ps. It is definitely non-trivial to measure this tiny time difference. Frequency division is of no use here because the phase difference ∆ϕ is also divided which is not desired. In this work, the down-mixers MIX1 and MIX2 are adopted to hold the value of ∆ϕ while greatly reducing the input signal frequency of the phase difference detecting circuit. Both V RF1 and V RF2 are down-converted to the intermediate frequency (IF). If the desired IF frequency is f IF , another frequency signal V LF with a frequency equal to f RF -f IF is generated and sent to MIX1 and MIX2.
The output signals of MIX1 and MIX2 are given as follows Both mixers' output signals pass through a low-pass filter (LPF), and the generated IF signals V IF1 and V IF2 are given as It is clearly seen that the phase difference ∆ϕ between V RF1 and V RF2 is converted to the same phase difference between the IF signals V IF1 and V IF2 . Again take ∆ϕ = 1 • as a numerical example.
If the IF frequency f IF is 200 kHz, after down-conversion, the time difference between V IF1 and V IF2 is now 13.9 ns, and this time difference can be easily measured. In this design, the IF signal time difference is detected by a digital bang-bang phase detector (BBPD) afterwards.
The signal V LF with frequency f RF -f IF is generated using a quadrature mixer as shown in the right part of Figure 5. The IF quadrature divider first generate the quadrature signals P90 IF = cos (2πf IF t) and P0 IF = sin (2πf IF t). In this design, f IF = 200 kHz. V LF is then generated by mixing P90 RF /P0 RF and P90 IF /P0 IF as follows.

Performance Analysis
If a B-bit fractional divider (DIV) is used in the PLL in Figure 5, the frequency resolution of the f RF output is The factor 2 in the numerator is due to the extra divide-by-2 divider DIV2 between the fractional divider DIV and the SAW drive. It is desired to slow down the IF signals signal to make the time difference large enough for measurement, but it will increase the measurement time inevitably. Hence it is important to find the lowest IF frequency allowed. Take the BBPD into consideration and the IF signal cycle period T IF is constrained by the minimum phase shift.
in which ∆t PD represents the minimum time difference that the BBPD can tell correctly, in other word, the deadzone. The minimum phase difference can be derived as (8) in which ϕ(f ) is a function of frequency which describes the phase-frequency response of the SAW device as shown in Figure 4. To find the value of the partial derivative, an equivalent parallel RLC resonance circuit is used to analogy the sensor around the resonance frequency. The phase difference is given by The partial derivative around f 0 can be expressed by the Q factor as Combine (6)- (8) and (10), and the minimum IF signal cycle period limited by the BBPD is For a B-bit fractional divider, it takes B searching steps to get the final result using SAR. Consequently, T MEAS is limited by B•T IF,min , which can written as Another limiting factor on T MEAS is the PLL settling time. T MEAS should be no shorter than the PLL settling time times B. The PLL settling time is limited by the PLL bandwidth BW PLL , and the bandwidth is usually a fraction of its reference frequency f REF . Here we assume that time of each searching step is α times the reference clock cycle period 1/f REF . T MEAS limited by the PLL is given by For a regular PLL design, f REF is about tens times BW PLL [28], and therefore α will not exceed 100.
In order to satisfy the restrictions of both the BBPD and the PLL settling time, the minimum measurement time is givens as To find the optimal design parameters, a measurement figure of merit FoM is defined to relate the measurement time T MEAS and the frequency measurement resolution ∆f min . Obviously, it is wanted to have a small FoM.
With (6) and (15), we have To show Q M of the proposed architecture quantitatively, some numbers from the real circuit with the proposed circuit are used. The reference frequency f REF is 24 MHz, the SAW resonance frequency is about 900 MHz, and its Q factor is 130. ∆t PD is obtained from the worst case (SS corner, 80% power supply, 85 • C) simulation, which is 50 ps. With these values in hand, we can plot the measurement quality factor FoM constrained by the PLL settling time and the phase detector versus the bits number of the PLL fractional divider, as shown in Figure 6. The FoM limit of the previous work [11][12][13][14][15][16][17][18] is also shown in Figure 6.
For a regular PLL design, fREF is about tens times BWPLL [28], and therefore α will not exceed 100.
In order to satisfy the restrictions of both the BBPD and the PLL settling time, the minimum measurement time is givens as To find the optimal design parameters, a measurement figure of merit FoM is defined to relate the measurement time TMEAS and the frequency measurement resolution Δfmin. Obviously, it is wanted to have a small FoM.
With (6) and (15), we have To show QM of the proposed architecture quantitatively, some numbers from the real circuit with the proposed circuit are used. The reference frequency fREF is 24 MHz, the SAW resonance frequency is about 900 MHz, and its Q factor is 130. ΔtPD is obtained from the worst case (SS corner, 80% power supply, 85 °C) simulation, which is 50 ps. With these values in hand, we can plot the measurement quality factor FoM constrained by the PLL settling time and the phase detector versus the bits number of the PLL fractional divider, as shown in Figure 6. The FoM limit of the previous work [11][12][13][14][15][16][17][18] is also shown in Figure 6. As shown in Figure 6, the intersection of the FoM curve limited by the PLL and that limited by the phase detector suggests an optimal divider bits number. The optimal point can also be found by As shown in Figure 6, the intersection of the FoM curve limited by the PLL and that limited by the phase detector suggests an optimal divider bits number. The optimal point can also be found by solving The optimal FoM is determined by f 0 , Q, ∆t PD and α, among which the only circuit design parameter is α. For α = 100, which is the upper limit from the previous discussion, B opt is 18, and the best FoM of the proposed architecture is only 0.02. As a contrast, the previous work [11][12][13][14][15][16][17][18] has a FoM limit of 1. To sum up, the proposed architecture can achieve a trade-off between the measurement time and frequency resolution, by shrinking their product smaller than that of the previous work.

Circuit Implementation
The proposed architecture as shown in Figure 5 has been designed and fabricated in a 180 nm CMOS technology. The circuit implementation details and the key design considerations will be given in this section.

Connection Parasitics between the SAW Device
To implement a compact sensor, the reported resonance frequency readout circuit will be connected to the SAW device using bonding wires, as shown in Figure 7. The SAW driving circuit in the readout chip is a simple differential amplifier with its output nodes connected to two pads. Two bonding wires tie the pads on the CMOS chip and the IDT on the SAW chip together.
The optimal FoM is determined by f0, Q, ΔtPD and α, among which the only circuit design parameter is α. For α = 100, which is the upper limit from the previous discussion, Bopt is 18, and the best FoM of the proposed architecture is only 0.02. As a contrast, the previous work [11][12][13][14][15][16][17][18] has a FoM limit of 1. To sum up, the proposed architecture can achieve a trade-off between the measurement time and frequency resolution, by shrinking their product smaller than that of the previous work.

Circuit Implementation
The proposed architecture as shown in Figure 5 has been designed and fabricated in a 180 nm CMOS technology. The circuit implementation details and the key design considerations will be given in this section.

Connection Parasitics between the SAW Device
To implement a compact sensor, the reported resonance frequency readout circuit will be connected to the SAW device using bonding wires, as shown in Figure 7. The SAW driving circuit in the readout chip is a simple differential amplifier with its output nodes connected to two pads. Two bonding wires tie the pads on the CMOS chip and the IDT on the SAW chip together. The direct measurement on the SAW device shows that its equivalent parallel RLC model has the parallel capacitance Cp, parallel inductance Lp, and parallel resistance Rp equal to 6.32 pF, 43.1 nH and 254 Ω, respectively, and the Q value without the parasitics reaches 163.
To build the behavior model for the SAW device, the SAW device is directly bonded on the printed circuit board (PCB) and connected to a network analyzer for port characteristic measurement. Then the S-parameter (S11) file obtained in this way is included in the simulation testbench of the driving circuit, and the result is shown in Figure 8. The parallel resonance frequency is about 898 MHz. The slope at the resonance frequency is 16.5 µdeg/Hz approximately, and the Q factor is about 130, according to Equation (10). Note that the parasitic effect has already been taken into consideration in this Q value. The direct measurement on the SAW device shows that its equivalent parallel RLC model has the parallel capacitance Cp, parallel inductance Lp, and parallel resistance R p equal to 6.32 pF, 43.1 nH and 254 Ω, respectively, and the Q value without the parasitics reaches 163.
To build the behavior model for the SAW device, the SAW device is directly bonded on the printed circuit board (PCB) and connected to a network analyzer for port characteristic measurement. Then the S-parameter (S 11 ) file obtained in this way is included in the simulation testbench of the driving circuit, and the result is shown in Figure 8. The parallel resonance frequency is about 898 MHz. The slope at the resonance frequency is 16.5 µdeg/Hz approximately, and the Q factor is about 130, according to Equation (10). Note that the parasitic effect has already been taken into consideration in this Q value. It has been confirmed through simulation that the parasitics effects of the bonding pads and wires can be safely ignored.
(1) The driving amplifier output capacitance and the bonding pad parasitic capacitance are actually relatively small compared to the SAW device parallel capacitance Cp, and they cause the resonance frequency to shift about −20 kHz. This frequency shift is almost constant in the effective measurement range. It can be calibrated out without affecting the linearity of the resonance frequency detection.
(2) The parasitic resistance causes the qualify factor Q to drop from about 163 to 130. This decrease in Q may have some effect in the measurement time according to Equation (11). Again, this effect can be easily compensated for by slightly increasing the PLL reference frequency fREF, if needed.

Fractional-N PLL
The block diagram of the fractional-N PLL is shown in Figure 9. A type II third-order charge pump PLL [29,30] with the LC-VCO centered at 1800 MHz is employed in the proposed readout circuit. The reference frequency is chosen to be 24 MHz, and the division ratio of the fractional divider DIV is between 18 and 19. The total division ratio is between 72 and 76, which means that RF signals VRF1 and VRF2 have a frequency that ranges from 864 to 912 MHz, which is actually the measurement range of the readout circuit. A single loop, third order delta sigma modulator (DSM) is used to get the fractional division ratio. It has 16-bit input (B = 16, which is close to the Bopt given by (17)) and 5-bit signed output, and the frequency resolution is about 732.42 Hz according to (6). Transient simulations are performed to obtain the measurement time of each searching step limited by the PLL settling time, and it shows that 40 µs turns to be a very safe value with a simulated PLL settling time of ~12.5 µs.  It has been confirmed through simulation that the parasitics effects of the bonding pads and wires can be safely ignored.
(1) The driving amplifier output capacitance and the bonding pad parasitic capacitance are actually relatively small compared to the SAW device parallel capacitance Cp, and they cause the resonance frequency to shift about −20 kHz. This frequency shift is almost constant in the effective measurement range. It can be calibrated out without affecting the linearity of the resonance frequency detection.
(2) The parasitic resistance causes the qualify factor Q to drop from about 163 to 130. This decrease in Q may have some effect in the measurement time according to Equation (11). Again, this effect can be easily compensated for by slightly increasing the PLL reference frequency f REF , if needed.

Fractional-N PLL
The block diagram of the fractional-N PLL is shown in Figure 9. A type II third-order charge pump PLL [29,30] with the LC-VCO centered at 1800 MHz is employed in the proposed readout circuit. The reference frequency is chosen to be 24 MHz, and the division ratio of the fractional divider DIV is between 18 and 19. The total division ratio is between 72 and 76, which means that RF signals V RF1 and V RF2 have a frequency that ranges from 864 to 912 MHz, which is actually the measurement range of the readout circuit. A single loop, third order delta sigma modulator (DSM) is used to get the fractional division ratio. It has 16-bit input (B = 16, which is close to the B opt given by (17)) and 5-bit signed output, and the frequency resolution is about 732.42 Hz according to (6). Transient simulations are performed to obtain the measurement time of each searching step limited by the PLL settling time, and it shows that 40 µs turns to be a very safe value with a simulated PLL settling time of~12.5 µs. It has been confirmed through simulation that the parasitics effects of the bonding pads and wires can be safely ignored.
(1) The driving amplifier output capacitance and the bonding pad parasitic capacitance are actually relatively small compared to the SAW device parallel capacitance Cp, and they cause the resonance frequency to shift about −20 kHz. This frequency shift is almost constant in the effective measurement range. It can be calibrated out without affecting the linearity of the resonance frequency detection.
(2) The parasitic resistance causes the qualify factor Q to drop from about 163 to 130. This decrease in Q may have some effect in the measurement time according to Equation (11). Again, this effect can be easily compensated for by slightly increasing the PLL reference frequency fREF, if needed.

Fractional-N PLL
The block diagram of the fractional-N PLL is shown in Figure 9. A type II third-order charge pump PLL [29,30] with the LC-VCO centered at 1800 MHz is employed in the proposed readout circuit. The reference frequency is chosen to be 24 MHz, and the division ratio of the fractional divider DIV is between 18 and 19. The total division ratio is between 72 and 76, which means that RF signals VRF1 and VRF2 have a frequency that ranges from 864 to 912 MHz, which is actually the measurement range of the readout circuit. A single loop, third order delta sigma modulator (DSM) is used to get the fractional division ratio. It has 16-bit input (B = 16, which is close to the Bopt given by (17)) and 5-bit signed output, and the frequency resolution is about 732.42 Hz according to (6). Transient simulations are performed to obtain the measurement time of each searching step limited by the PLL settling time, and it shows that 40 µs turns to be a very safe value with a simulated PLL settling time of ~12.5 µs.

Mixer and I/Q Generator
There are two kinds of mixers used in the proposed circuit. The first one is the quadrature mixer [31], which provides the V LF signal as shown in Figure 5. Its circuit is shown in Figure 10. The annotation "HF" in Figure 10 represents the P90 RF and P0 RF as shown in Figure 5, while "LF" stands for the P90 IF and P0 IF signals.

Mixer and I/Q Generator
There are two kinds of mixers used in the proposed circuit. The first one is the quadrature mixer [31], which provides the VLF signal as shown in Figure 5. Its circuit is shown in Figure 10. The annotation "HF" in Figure 10 represents the P90RF and P0RF as shown in Figure 5, while "LF" stands for the P90IF and P0IF signals. For RF signals P90RF and P0RF, two current mode logic (CML) latches are used as shown in Figure 11b. P90RF and P0RF mix up with P90IF and P0IF according to (5). The output of the quadrature mixer is In this design, fRF and fIF are chosen to be 900 MHz and 200 kHz, respectively. Equation (20) shows that the actual VLF is not a single tone signal. Figure 10. Quadrature mixer to generate V LF . The inputs signal LF and HF are both quadrature differential, and the output is differential.
P90 IF and P0 IF have a frequency of 200 kHz in this design, and they are generated using the digital circuit as shown in Figure 11a. Hence these two signals have square waveforms and can be expanded in Fourier series as Sensors 2017, 17, 2131 10 of 20

Mixer and I/Q Generator
There are two kinds of mixers used in the proposed circuit. The first one is the quadrature mixer [31], which provides the VLF signal as shown in Figure 5. Its circuit is shown in Figure 10. The annotation "HF" in Figure 10 represents the P90RF and P0RF as shown in Figure 5, while "LF" stands for the P90IF and P0IF signals. Figure 10. Quadrature mixer to generate VLF. The inputs signal LF and HF are both quadrature differential, and the output is differential. For RF signals P90RF and P0RF, two current mode logic (CML) latches are used as shown in Figure 11b. P90RF and P0RF mix up with P90IF and P0IF according to (5). The output of the quadrature mixer is In this design, fRF and fIF are chosen to be 900 MHz and 200 kHz, respectively. Equation (20) shows that the actual VLF is not a single tone signal. For RF signals P90 RF and P0 RF , two current mode logic (CML) latches are used as shown in Figure 11b. P90 RF and P0 RF mix up with P90 IF and P0 IF according to (5). The output of the quadrature mixer is In this design, f RF and f IF are chosen to be 900 MHz and 200 kHz, respectively. Equation (20) shows that the actual V LF is not a single tone signal.
The second kind of mixer is the down-mixer MIX1 and MIX2 that convert the phase difference to the IF band. The circuit is shown in Figure 12 where the "HF" refers to V RF1 and V RF2 , which are the input/output of the SAW device driving amplifier, and "LF" refers to the quadrature mixer output V LF . V IF1 and V IF2 from Equations (3) and (4) need to be re-checked since V LF is no longer a single tone. The actual V IF1 and V IF2 can be written as The second kind of mixer is the down-mixer MIX1 and MIX2 that convert the phase difference to the IF band. The circuit is shown in Figure 12 where the "HF" refers to VRF1 and VRF2, which are the input/output of the SAW device driving amplifier, and "LF" refers to the quadrature mixer output VLF. VIF1 and VIF2 from Equations (3) and (4) need to be re-checked since VLF is no longer a single tone. The actual VIF1 and VIF2 can be written as (21) Figure 12. Circuit of the down-mixer. The inputs HF and LF are differential, and so is the output.
It can be shown that the harmonics have no effect on the lead-lag relationship between VIF1 and VIF2. This can be done by checking the zero-crossing points of VIF1 and VIF2. It is obvious that tzc(k) = (2k + 1)/4fIF (k = 0, 1, 2, ...) are the zero-crossing points of VIF1. A quick numeric simulation using Matlab shows that the harmonics will not create any extra zero-crossing point other than tzc(k).
If VRF1 is slightly leading VRF2, we have -π < Δφ < 0 and sin (Δφ) < 0. (23) and (24) shows that if k is odd, when VIF1 crosses zero with a positive slope, VIF2 is still below zero. Under this case VIF1 is still leading VIF2, just as VRF1 is leading VRF2. It can be shown that the harmonics have no effect on the lead-lag relationship between V IF1 and V IF2 . This can be done by checking the zero-crossing points of V IF1 and V IF2 . It is obvious that t zc (k) = (2k + 1)/4f IF (k = 0, 1, 2, . . . ) are the zero-crossing points of V IF1 . A quick numeric simulation using Matlab shows that the harmonics will not create any extra zero-crossing point other than t zc (k).
For any k, V IF1 (t zc (k)) = 0, cos(2π(−1) n (2n+1) f IF t zc (k)) (−1) n (2n+1) 2 = 0, the slope of V IF1 at the time point t zc (k) is First check the case that k is odd. When k is odd, at the time point t zc (k), (24) shows that V IF2 (t zc (k)) has the same polarity as sin(∆ϕ). If V RF1 is slightly leading V RF2 , we have -π < ∆ϕ < 0 and sin (∆ϕ) < 0. (23) and (24) shows that if k is odd, when V IF1 crosses zero with a positive slope, V IF2 is still below zero. Under this case V IF1 is still leading V IF2 , just as V RF1 is leading V RF2 .
The same conclusion can be made when k is even. This analysis has validated that harmonics in V LF have no effect on the lead-lag relationship between V IF1 and V IF2 .
On the other hand, the distortion caused by the CML nonlinearity has been checked using the transistor level simulation, and it is also proven that the CML nonlinearity can also be neglected.

Passive LPF and Comparator
In this design, the low past filter (LPF) is placed after the down-mixer to filter out the high frequency components, and the V IF1 and V IF2 signal can only contain the sub-1 MHz components for phase difference detection.
A passive RC filter is used to save power consumption. A simple realization is shown in Figure 13, where all the resistors and capacitors are chosen to be identical for simplicity. The third order passive LPF is chosen as a trade-off between stop-band attenuation and area. The same conclusion can be made when k is even. This analysis has validated that harmonics in VLF have no effect on the lead-lag relationship between VIF1 and VIF2.
On the other hand, the distortion caused by the CML nonlinearity has been checked using the transistor level simulation, and it is also proven that the CML nonlinearity can also be neglected.

Passive LPF and Comparator
In this design, the low past filter (LPF) is placed after the down-mixer to filter out the high frequency components, and the VIF1 and VIF2 signal can only contain the sub-1 MHz components for phase difference detection.
A passive RC filter is used to save power consumption. A simple realization is shown in Figure 13, where all the resistors and capacitors are chosen to be identical for simplicity. The third order passive LPF is chosen as a trade-off between stop-band attenuation and area. The comparator ("Comp" in Figure 5) circuit is shown in Figure 14. The comparator is a openloop amplifier with negative resistance transistors to increase the gain bandwidth [32]. In this readout chip, the comparator actually serves as a differential to a single-ended converter that converts the differential analog input VIF1 and VIF2 into digital pulses.

BBPD and Control Logic
The circuit of the BBPD is given in Figure 15. True single phase clock (TSPC) registers [33] are used here. The output "OUT1" and "OUT2" indicate whether "IN1" is leading "IN2" or vice versa. The output "SYNC" will be high if the time difference between the input signals is too small for the BBPD to distinguish, in other words, the input signals are "synchronous". The SAR searching control logic is composed of 3 parts, the delay compensation, the VCO capacitor bank preset and the SAR algorithm. The first and second parts are used only before the real The comparator ("Comp" in Figure 5) circuit is shown in Figure 14. The comparator is a open-loop amplifier with negative resistance transistors to increase the gain bandwidth [32]. In this readout chip, the comparator actually serves as a differential to a single-ended converter that converts the differential analog input V IF1 and V IF2 into digital pulses. The same conclusion can be made when k is even. This analysis has validated that harmonics in VLF have no effect on the lead-lag relationship between VIF1 and VIF2.
On the other hand, the distortion caused by the CML nonlinearity has been checked using the transistor level simulation, and it is also proven that the CML nonlinearity can also be neglected.

Passive LPF and Comparator
In this design, the low past filter (LPF) is placed after the down-mixer to filter out the high frequency components, and the VIF1 and VIF2 signal can only contain the sub-1 MHz components for phase difference detection.
A passive RC filter is used to save power consumption. A simple realization is shown in Figure 13, where all the resistors and capacitors are chosen to be identical for simplicity. The third order passive LPF is chosen as a trade-off between stop-band attenuation and area. The comparator ("Comp" in Figure 5) circuit is shown in Figure 14. The comparator is a openloop amplifier with negative resistance transistors to increase the gain bandwidth [32]. In this readout chip, the comparator actually serves as a differential to a single-ended converter that converts the differential analog input VIF1 and VIF2 into digital pulses.

BBPD and Control Logic
The circuit of the BBPD is given in Figure 15. True single phase clock (TSPC) registers [33] are used here. The output "OUT1" and "OUT2" indicate whether "IN1" is leading "IN2" or vice versa. The output "SYNC" will be high if the time difference between the input signals is too small for the BBPD to distinguish, in other words, the input signals are "synchronous". The SAR searching control logic is composed of 3 parts, the delay compensation, the VCO capacitor bank preset and the SAR algorithm. The first and second parts are used only before the real Figure 14. Schematic of the comparator, with cross coupled transistors as load for fast comparison.

BBPD and Control Logic
The circuit of the BBPD is given in Figure 15. True single phase clock (TSPC) registers [33] are used here. The output "OUT 1 " and "OUT 2 " indicate whether "IN 1 " is leading "IN 2 " or vice versa. The output "SYNC" will be high if the time difference between the input signals is too small for the BBPD to distinguish, in other words, the input signals are "synchronous". The same conclusion can be made when k is even. This analysis has validated that harmonics in VLF have no effect on the lead-lag relationship between VIF1 and VIF2.
On the other hand, the distortion caused by the CML nonlinearity has been checked using the transistor level simulation, and it is also proven that the CML nonlinearity can also be neglected.

Passive LPF and Comparator
In this design, the low past filter (LPF) is placed after the down-mixer to filter out the high frequency components, and the VIF1 and VIF2 signal can only contain the sub-1 MHz components for phase difference detection.
A passive RC filter is used to save power consumption. A simple realization is shown in Figure 13, where all the resistors and capacitors are chosen to be identical for simplicity. The third order passive LPF is chosen as a trade-off between stop-band attenuation and area. The comparator ("Comp" in Figure 5) circuit is shown in Figure 14. The comparator is a openloop amplifier with negative resistance transistors to increase the gain bandwidth [32]. In this readout chip, the comparator actually serves as a differential to a single-ended converter that converts the differential analog input VIF1 and VIF2 into digital pulses.

BBPD and Control Logic
The circuit of the BBPD is given in Figure 15. True single phase clock (TSPC) registers [33] are used here. The output "OUT1" and "OUT2" indicate whether "IN1" is leading "IN2" or vice versa. The output "SYNC" will be high if the time difference between the input signals is too small for the BBPD to distinguish, in other words, the input signals are "synchronous". The SAR searching control logic is composed of 3 parts, the delay compensation, the VCO capacitor bank preset and the SAR algorithm. The first and second parts are used only before the real The SAR searching control logic is composed of 3 parts, the delay compensation, the VCO capacitor bank preset and the SAR algorithm. The first and second parts are used only before the real measurements start. The delay compensation block is used to compensate for the delay mismatch between the two signal paths, i.e., the path of V RF1 /V IF1 and the path of V RF2 /V IF2 . Two digital controlled delay lines as shown in Figure 5 are tuned to cancel the delay mismatch using on a logic control circuit with the BBPD "SYNC" as its input.
The IF frequency is chosen to be 200 kHz, meeting the requirement of (11). The initial searching step time T STEP is 40 µs, which equals to 8 cycles of the IF signal (200 kHz). However, the frequency step becomes smaller as the binary search goes, and a variable searching step time T STEP is used in this design to shorten the overall measurement time T MEAS . T STEP is set to 8 IF signal cycles to determine 4 MSB bits of the PLL frequency setting, 4 IF cycles for the 4 LSB bits and 6 IF cycles for the 8 intermediate bits. Thus, it takes 96 IF signal cycles, which is 0.48 ms, to complete one measurement.

Measurement Set-up
The proposed readout circuit was implemented and fabricated in a 180 nm CMOS technology. The chip micrograph is shown in Figure 16. The core area of the circuit is about 1.8 mm × 1.8 mm. The readout circuit chip and the SAW device are connected together via bonding wires according, as shown in Figure 17. measurements start. The delay compensation block is used to compensate for the delay mismatch between the two signal paths, i.e., the path of VRF1/VIF1 and the path of VRF2/VIF2. Two digital controlled delay lines as shown in Figure 5 are tuned to cancel the delay mismatch using on a logic control circuit with the BBPD "SYNC" as its input.
The IF frequency is chosen to be 200 kHz, meeting the requirement of (11). The initial searching step time TSTEP is 40 µs, which equals to 8 cycles of the IF signal (200 kHz). However, the frequency step becomes smaller as the binary search goes, and a variable searching step time TSTEP is used in this design to shorten the overall measurement time TMEAS. TSTEP is set to 8 IF signal cycles to determine 4 MSB bits of the PLL frequency setting, 4 IF cycles for the 4 LSB bits and 6 IF cycles for the 8 intermediate bits. Thus, it takes 96 IF signal cycles, which is 0.48 ms, to complete one measurement.

Measurement Set-up
The proposed readout circuit was implemented and fabricated in a 180 nm CMOS technology. The chip micrograph is shown in Figure 16. The core area of the circuit is about 1.8 mm × 1.8 mm. The readout circuit chip and the SAW device are connected together via bonding wires according, as shown in Figure 17.  The measurement set-up in which the SAW device and the resonance frequency readout chip are used as a temperature sensor is shown in Figure 18. The test PCB is placed on a hot plate. An external 24 MHz clock signal is used as the PLL reference clock. A microcontroller (MCU) is employed to read/write the control words via a serial peripheral interface (SPI). Firstly, the temperature of hot plate is set to 25 °C. A spectrum analyzer records the PLL output spectrum. An oscilloscope is used to evaluate the PLL settling time and the phase difference detecting circuit. measurements start. The delay compensation block is used to compensate for the delay mismatch between the two signal paths, i.e., the path of VRF1/VIF1 and the path of VRF2/VIF2. Two digital controlled delay lines as shown in Figure 5 are tuned to cancel the delay mismatch using on a logic control circuit with the BBPD "SYNC" as its input.
The IF frequency is chosen to be 200 kHz, meeting the requirement of (11). The initial searching step time TSTEP is 40 µs, which equals to 8 cycles of the IF signal (200 kHz). However, the frequency step becomes smaller as the binary search goes, and a variable searching step time TSTEP is used in this design to shorten the overall measurement time TMEAS. TSTEP is set to 8 IF signal cycles to determine 4 MSB bits of the PLL frequency setting, 4 IF cycles for the 4 LSB bits and 6 IF cycles for the 8 intermediate bits. Thus, it takes 96 IF signal cycles, which is 0.48 ms, to complete one measurement.

Measurement Set-up
The proposed readout circuit was implemented and fabricated in a 180 nm CMOS technology. The chip micrograph is shown in Figure 16. The core area of the circuit is about 1.8 mm × 1.8 mm. The readout circuit chip and the SAW device are connected together via bonding wires according, as shown in Figure 17.  The measurement set-up in which the SAW device and the resonance frequency readout chip are used as a temperature sensor is shown in Figure 18. The test PCB is placed on a hot plate. An external 24 MHz clock signal is used as the PLL reference clock. A microcontroller (MCU) is employed to read/write the control words via a serial peripheral interface (SPI). Firstly, the temperature of hot plate is set to 25 °C. A spectrum analyzer records the PLL output spectrum. An oscilloscope is used to evaluate the PLL settling time and the phase difference detecting circuit. The measurement set-up in which the SAW device and the resonance frequency readout chip are used as a temperature sensor is shown in Figure 18. The test PCB is placed on a hot plate. An external 24 MHz clock signal is used as the PLL reference clock. A microcontroller (MCU) is employed to read/write the control words via a serial peripheral interface (SPI). Firstly, the temperature of hot plate is set to 25 • C. A spectrum analyzer records the PLL output spectrum. An oscilloscope is used to evaluate the PLL settling time and the phase difference detecting circuit. Secondly, the temperature of hot plate is set from 25 to 55 • C with a 5 • C step, by which the function of the proposed readout circuit is verified. Secondly, the temperature of hot plate is set from 25 to 55 °C with a 5 °C step, by which the function of the proposed readout circuit is verified.

Experimental Results
The resonance frequency resolution is measured first. By setting the frequency the PLL fractional division ratio with a difference of 2 −16 , the chip gave the RF signals with the minimum frequency difference, which is actually the resonance frequency resolution. The spectra of the two signals is shown in Figure 19, and the frequency resolution is 733 Hz, which agrees with the value of 732.42 Hz predicted by (6). The relative resolution is about 0.82 ppm with respect to the nominal measurement frequency of 900 MHz.

Experimental Results
The resonance frequency resolution is measured first. By setting the frequency the PLL fractional division ratio with a difference of 2 −16 , the chip gave the RF signals with the minimum frequency difference, which is actually the resonance frequency resolution. The spectra of the two signals is shown in Figure 19, and the frequency resolution is 733 Hz, which agrees with the value of 732.42 Hz predicted by (6). The relative resolution is about 0.82 ppm with respect to the nominal measurement frequency of 900 MHz. Secondly, the temperature of hot plate is set from 25 to 55 °C with a 5 °C step, by which the function of the proposed readout circuit is verified. Figure 18. Measurement set-up. The proposed chip and the SAW device are on the test PCB, and the test PCB is controlled by a MCU board which is further connected to PC for data collection.

Experimental Results
The resonance frequency resolution is measured first. By setting the frequency the PLL fractional division ratio with a difference of 2 −16 , the chip gave the RF signals with the minimum frequency difference, which is actually the resonance frequency resolution. The spectra of the two signals is shown in Figure 19, and the frequency resolution is 733 Hz, which agrees with the value of 732.42 Hz predicted by (6). The relative resolution is about 0.82 ppm with respect to the nominal measurement frequency of 900 MHz.    Figure 20 gives the measured phase noise of the VCO output centered at about 1.8 GHz when the PLL loop is locked. The phase noise is −95.29 dBc/Hz at 100 kHz frequency offset and is −102.53 dBc/Hz at 1 MHz frequency offset. It should be emphasized that it has been verified through behavior simulation that such noise level will not affect the frequency measurement resolution. The key non-idealities that affect the measurement accuracy with limited measurement time are the PLL settling time and the minimum phase difference that the BBPD can differentiate.
The waveform of the PLL control voltage V C with a 1 V step is shown in Figure 21. The measured settling time is 13 µs, which is quite close to the simulation result. In this design, the searching step length ranges from 20 to 40 µs (4~8 IF clock cycles), which leaves enough margin for the PLL to settle down during the resonance frequency measurement.  The waveform of the PLL control voltage VC with a 1 V step is shown in Figure 21. The measured settling time is 13 µs, which is quite close to the simulation result. In this design, the searching step length ranges from 20 to 40 µs (4~8 IF clock cycles), which leaves enough margin for the PLL to settle down during the resonance frequency measurement. The waveforms of VIF1 and VIF2 (actually the single ended output of the comparators) are shown in Figures 22 and 23. The green curve is VIF2 which is the down converted signal of the SAW device driving amplifier output VRF2, and the pink line is VIF1 which is the down converted signal of the SAW device driving amplifier input VRF1. The IF frequency is set to 12 MHz in Figures 22 and 23 instead of 200 kHz to amplify the time difference. As shown in Figure 22, when the PLL frequency is less than  The waveform of the PLL control voltage VC with a 1 V step is shown in Figure 21. The measured settling time is 13 µs, which is quite close to the simulation result. In this design, the searching step length ranges from 20 to 40 µs (4~8 IF clock cycles), which leaves enough margin for the PLL to settle down during the resonance frequency measurement. The waveforms of VIF1 and VIF2 (actually the single ended output of the comparators) are shown in Figures 22 and 23. The green curve is VIF2 which is the down converted signal of the SAW device driving amplifier output VRF2, and the pink line is VIF1 which is the down converted signal of the SAW device driving amplifier input VRF1. The IF frequency is set to 12 MHz in Figures 22 and 23 instead of 200 kHz to amplify the time difference. As shown in Figure 22, when the PLL frequency is less than The waveforms of V IF1 and V IF2 (actually the single ended output of the comparators) are shown in Figures 22 and 23. The green curve is V IF2 which is the down converted signal of the SAW device driving amplifier output V RF2 , and the pink line is V IF1 which is the down converted signal of the SAW device driving amplifier input V RF1 . The IF frequency is set to 12 MHz in Figures 22 and 23 instead of 200 kHz to amplify the time difference. As shown in Figure 22, when the PLL frequency is less than the SAW resonance frequency f 0 , V IF2 leads V IF1 , which means ∆ϕ is larger than 0, which agrees with Figure 4. Similarly, the case that V IF2 lags V IF1 as shown in Figure 23 means ∆ϕ is less than 0, which indicates the PLL frequency is larger than the SAW resonance frequency f 0 according to Figure 4. the SAW resonance frequency f0, VIF2 leads VIF1, which means Δφ is larger than 0, which agrees with Figure 4. Similarly, the case that VIF2 lags VIF1 as shown in Figure 23 means Δφ is less than 0, which indicates the PLL frequency is larger than the SAW resonance frequency f0 according to Figure 4.  The minimum detectable time difference of the BBPD is show in Figure 24. The green line and the pink lines are the BBPD input signals (the IF signals) to be differentiated, while the blue line and the red line are the differential outputs of the BBPD which tells the lead-lag relationship between the two input signals. It can be seen that the BBPD can give the correct output when the input difference is as small as 60 ps. the SAW resonance frequency f0, VIF2 leads VIF1, which means Δφ is larger than 0, which agrees with Figure 4. Similarly, the case that VIF2 lags VIF1 as shown in Figure 23 means Δφ is less than 0, which indicates the PLL frequency is larger than the SAW resonance frequency f0 according to Figure 4.  The minimum detectable time difference of the BBPD is show in Figure 24. The green line and the pink lines are the BBPD input signals (the IF signals) to be differentiated, while the blue line and the red line are the differential outputs of the BBPD which tells the lead-lag relationship between the two input signals. It can be seen that the BBPD can give the correct output when the input difference is as small as 60 ps. The minimum detectable time difference of the BBPD is show in Figure 24. The green line and the pink lines are the BBPD input signals (the IF signals) to be differentiated, while the blue line and the red line are the differential outputs of the BBPD which tells the lead-lag relationship between the two input signals. It can be seen that the BBPD can give the correct output when the input difference is as small as 60 ps.
According to (7), (8) and (10), the frequency resolution limit imposed by the BBPD is calculated as ∆ f min,BPFD = π · ∆t PD f IF f 0 Q = 262 Hz (25) in which ∆t PD = 60 ps as shown in Figure 24, f IF = 200 kHz, f 0 = 900MHz, Q =130. This number is smaller than the fractional-N PLL frequency resolution (773 Hz). Therefore the readout circuit frequency resolution is mainly constrained by the PLL frequency resolution.
The functionality of the proposed resonance readout circuit has been validated by using the readout chip and the SAW device as a temperature sensor. Figure 25 gives the measured SAW device resonance frequency shift versus the environment temperature using the measurement setup in Figure 18. The resonance frequency is calculated out of the PLL division ratio which represents the PLL frequency. The measurement sensitivity (the SAW device plus the readout circuit) is about −47 kHz/K with the linearity correlation coefficient R 2 equal to 0.9991. This test validates the functionality of the presented SAW resonance frequency readout circuit. According to (7), (8) and (10), the frequency resolution limit imposed by the BBPD is calculated as  (25) in which ΔtPD = 60 ps as shown in Figure 24, fIF = 200 kHz, f0 = 900MHz, Q =130. This number is smaller than the fractional-N PLL frequency resolution (773 Hz). Therefore the readout circuit frequency resolution is mainly constrained by the PLL frequency resolution. The functionality of the proposed resonance readout circuit has been validated by using the readout chip and the SAW device as a temperature sensor. Figure 25 gives the measured SAW device resonance frequency shift versus the environment temperature using the measurement setup in Figure 18. The resonance frequency is calculated out of the PLL division ratio which represents the PLL frequency. The measurement sensitivity (the SAW device plus the readout circuit) is about −47 kHz/K with the linearity correlation coefficient R 2 equal to 0.9991. This test validates the functionality of the presented SAW resonance frequency readout circuit.  Table 1 summarizes the performance of the presented resonance frequency readout circuit, and also gives the comparison between this work and the state-of-the-art results in literature. The measured power consumption of the SAW resonance frequency readout circuit is about 7 mW from a 1.6 V power supply. The frequency resolution is 733 Hz, and the relative measurement resolution, defined as the frequency resolution divided by the device resonance frequency, is 0.82 ppm, which is among the state-of-the-art results. It takes 0.48 ms for the readout circuit to determine the resonance frequency of the SAW device, which outperforms all the other work in literature. IOverall, this work has achieved a good trade-off between the relative accuracy and the measurement time performance. According to (7), (8) and (10), the frequency resolution limit imposed by the BBPD is calculated as  (25) in which ΔtPD = 60 ps as shown in Figure 24, fIF = 200 kHz, f0 = 900MHz, Q =130. This number is smaller than the fractional-N PLL frequency resolution (773 Hz). Therefore the readout circuit frequency resolution is mainly constrained by the PLL frequency resolution. The functionality of the proposed resonance readout circuit has been validated by using the readout chip and the SAW device as a temperature sensor. Figure 25 gives the measured SAW device resonance frequency shift versus the environment temperature using the measurement setup in Figure 18. The resonance frequency is calculated out of the PLL division ratio which represents the PLL frequency. The measurement sensitivity (the SAW device plus the readout circuit) is about −47 kHz/K with the linearity correlation coefficient R 2 equal to 0.9991. This test validates the functionality of the presented SAW resonance frequency readout circuit.

Conclusions
A resonance frequency readout method is proposed for a 900 MHz SAW device in this paper. The proposed method is based on phase difference detection and SAR. It provides a good trade-off between the frequency measurement resolution and the measurement time. The readout circuit has been designed and fabricated in a 180 nm CMOS technology. The experimental results show that the proposed readout circuit has greatly improved the frequency measurement resolution, while the time required for a single measurement is shorter than the state-of-the-art results in literature. The functionality of the readout circuit has been tested with a 900 MHz RF SAW device as a temperature sensor. The presented readout circuit will be tested with the resonance-based pressure sensors and mass sensors for more applications in the future.