Compensation of PVT Variations in ToF Imagers with In-Pixel TDC

The design of a direct time-of-flight complementary metal-oxide-semiconductor (CMOS) image sensor (dToF-CIS) based on a single-photon avalanche-diode (SPAD) array with an in-pixel time-to-digital converter (TDC) must contemplate system-level aspects that affect its overall performance. This paper provides a detailed analysis of the impact of process parameters, voltage supply, and temperature (PVT) variations on the time bin of the TDC array. Moreover, the design and characterization of a global compensation loop is presented. It is based on a phase locked loop (PLL) that is integrated on-chip. The main building block of the PLL is a voltage-controlled ring-oscillator (VCRO) that is identical to the ones employed for the in-pixel TDCs. The reference voltage that drives the master VCRO is distributed to the voltage control inputs of the slave VCROs such that their multiphase outputs become invariant to PVT changes. These outputs act as time interpolators for the TDCs. Therefore the compensation scheme prevents the time bin of the TDCs from drifting over time due to the aforementioned factors. Moreover, the same scheme is used to program different time resolutions of the direct time-of-flight (ToF) imager aimed at 3D ranging or depth map imaging. Experimental results that validate the analysis are provided as well. The compensation loop proves to be remarkably effective. The spreading of the TDCs time bin is lowered from: (i) 20% down to 2.4% while the temperature ranges from 0 °C to 100 °C; (ii) 27% down to 0.27%, when the voltage supply changes within ±10% of the nominal value; (iii) 5.2 ps to 2 ps standard deviation over 30 sample chips, due to process parameters’ variation.


Introduction
Arrayable single-photon avalanche-diodes (SPADs) are available in complementary metal-oxide-semiconductor (CMOS) technologies, gaining popularity in the development of 3D image sensors [1]. Thanks to their ability to accurately detect the arrival of single photons, they can be employed to perform direct time-of-flight (ToF) measurements [2]. This is an additional feature with respect to integrating photodiodes [3], which calculate ToF by using indirect estimation methods. In order to capture a depth map of the scene, SPADs are arranged in a bi-dimensional array that can effectively associate an estimation of the ToF to each point in the image. Direct ToF requires a time-to-digital converter (TDC), able to timestamp the onset of the avalanche following the arrival of a photon, while indirect ToF [4] estimation can still be done by photon counting. Apart from 3D imaging, direct ToF measurement can be also applied to positron emission tomography (PET) [5,6] and to other biomedical techniques using a faint light source such as fluorescence lifetime imaging microscopy (FLIM) [7]. Ultimately, all these applications require statistics building of the photon control signals, noise cancellation, and real-time 3D image reconstruction at 1000 fps; (iv) a picosecond laser. The camera is aimed for depth map imaging and photon counting applications.
The rest of the paper is organized as follows. The next section thoroughly describes the operation of the in-pixel TDC and the PLL-based global compensation scheme. The third section provides the theoretical background to understand the effect of PVT variations on the TDCs time bin. The fourth section reports several experimental results such as the time resolution programmability and the jitter of the in-pixel time interpolator. Moreover, measurements of the dependence of the TDCs time bin on the PVT variations are also shown, validating the compensation method. The models of oscillation frequency and process parameters' variation are compared to the experimental results. The last section is dedicated to the conclusions. image reconstruction at 1000 fps; (iv) a picosecond laser. The camera is aimed for depth map imaging and photon counting applications. The rest of the paper is organized as follows. The next section thoroughly describes the operation of the in-pixel TDC and the PLL-based global compensation scheme. The third section provides the theoretical background to understand the effect of PVT variations on the TDCs time bin. The fourth section reports several experimental results such as the time resolution programmability and the jitter of the in-pixel time interpolator. Moreover, measurements of the dependence of the TDCs time bin on the PVT variations are also shown, validating the compensation method. The models of oscillation frequency and process parameters' variation are compared to the experimental results. The last section is dedicated to the conclusions.

Time Bin Control Scheme
Direct ToF estimation requires accurate determination of the time interval delimited by the output pulse of the SPAD and the synchronization of the pulsed laser. For this to be carried out, a TDC is incorporated into each pixel. In order to achieve sub-nanosecond accuracy in CMOS, counting clock edges would be insufficient. The counter needs to be combined with time-interpolation techniques. In our case, each TDC (Figure 1-pixel inset: In-pixel TDC) is built by a coarse 8 bits ripple-counter, a VCRO and an encoder that generates the finest 3 bits from the phases of the VCRO, plus some control logic. A reverse start-stop scheme is employed to save power. The VCRO is started by the first positive edge of Vout, signaling a triggering of the SPAD detector. Consequently the EN_TDC signal is enabled. Later on, the VCRO is stopped by the positive edge of the Ext_Stop synchronization signal, causing EN_TDC to be disabled. At this time, the ripple counter and the 8 phases of the oscillator are frozen. The most significant 8 bits of the ToF estimation are contained by the counter, while the VCRO's phases are encoded to provide the least significant 3 bits. The conversion result is available at the very end of the measured time interval which makes this scheme appropriate for applications which require a high conversion rate.

Time Bin Control Scheme
Direct ToF estimation requires accurate determination of the time interval delimited by the output pulse of the SPAD and the synchronization of the pulsed laser. For this to be carried out, a TDC is incorporated into each pixel. In order to achieve sub-nanosecond accuracy in CMOS, counting clock edges would be insufficient. The counter needs to be combined with time-interpolation techniques. In our case, each TDC (Figure 1-pixel inset: In-pixel TDC) is built by a coarse 8 bits ripple-counter, a VCRO and an encoder that generates the finest 3 bits from the phases of the VCRO, plus some control logic. A reverse start-stop scheme is employed to save power. The VCRO is started by the first positive edge of Vout, signaling a triggering of the SPAD detector. Consequently the EN_TDC signal is enabled. Later on, the VCRO is stopped by the positive edge of the Ext_Stop synchronization signal, causing EN_TDC to be disabled. At this time, the ripple counter and the 8 phases of the oscillator are frozen. The most significant 8 bits of the ToF estimation are contained by the counter, while the VCRO's phases are encoded to provide the least significant 3 bits. The conversion result is available at the very end of the measured time interval which makes this scheme appropriate for applications which require a high conversion rate. The array of VCROs is driven by the voltage labeled as TUNE. It is provided by a global compensation scheme implemented by an on-chip PLL ( Figure 2). A master VCRO is locked by the PLL. Whenever a PVT variation occurs, the loop acts to correct it by adjusting the voltage on the loop filter in order to keep the same oscillation frequency. Consequently, the oscillation frequency of the slave VCROs follows the master VCRO ( Figure 2-inset: Master VCRO). It is worth mentioning that this compensation technique works if the gradient of the PVT variations is uniformly distributed across the array. Moreover, the ripple of the TUNE voltage causes a deviation of the TDC time bin. This implication can be written as: where ∆V re f is the ripple of the loop filter output, ∆T bin is the deviation in the TDC time bin, K VCRO is the VCRO gain, and V re f is the average output of the loop filter. The array of VCROs is driven by the voltage labeled as TUNE. It is provided by a global compensation scheme implemented by an on-chip PLL ( Figure 2). A master VCRO is locked by the PLL. Whenever a PVT variation occurs, the loop acts to correct it by adjusting the voltage on the loop filter in order to keep the same oscillation frequency. Consequently, the oscillation frequency of the slave VCROs follows the master VCRO ( Figure 2-inset: Master VCRO). It is worth mentioning that this compensation technique works if the gradient of the PVT variations is uniformly distributed across the array. Moreover, the ripple of the TUNE voltage causes a deviation of the TDC time bin. This implication can be written as: where ∆ is the ripple of the loop filter output, ∆ is the deviation in the TDC time bin, is the VCRO gain, and is the average output of the loop filter.

Pseudo-Differential VCRO
The ring oscillator is the core building block of the TDC. It gives the clock for the ripple-counter generating the most significant bits of the conversion, while providing the phases for the encoder to obtain the least significant bits of the conversion by phase interpolation. The proposed scheme is a 4-stage pseudo-differential VCRO, also suitable to be implemented in FPGA [14]. The block diagram of the VCRO is depicted in Figure 1-pixel inset: Slave VCRO. Notice that the reset signal forces the oscillator to start each time with the same phase. This auto-alignment minimizes the start-up error which affects the time accuracy of the TDC. The selection of the number of stages is a matter of trade-off between the number of interpolation phases and the area. Thus, considering an oscillation frequency of 850 MHz, four stages are enough to obtain a time resolution below 150 ps. The novelty of this VCRO scheme relies on the highly linear frequency control scheme, which is based on the variable resistance of a transmission gate, represented by the block "RV" in Figure 3.

Pseudo-Differential VCRO
The ring oscillator is the core building block of the TDC. It gives the clock for the ripple-counter generating the most significant bits of the conversion, while providing the phases for the encoder to obtain the least significant bits of the conversion by phase interpolation. The proposed scheme is a 4-stage pseudo-differential VCRO, also suitable to be implemented in FPGA [14]. The block diagram of the VCRO is depicted in Figure 1-pixel inset: Slave VCRO. Notice that the reset signal forces the oscillator to start each time with the same phase. This auto-alignment minimizes the start-up error which affects the time accuracy of the TDC. The selection of the number of stages is a matter of trade-off between the number of interpolation phases and the area. Thus, considering an oscillation frequency of 850 MHz, four stages are enough to obtain a time resolution below 150 ps. The novelty of this VCRO scheme relies on the highly linear frequency control scheme, which is based on the variable resistance of a transmission gate, represented by the block "R V " in Figure 3. Let us consider the schematic of the delay cell depicted in Figure 3. The reset signal, R, is disabled, being set to VDD. The half circuit of the delay cell ( Figure 4a) can be employed to approximate the oscillation frequency of the VCRO. By solving the differential equation of the step response, the output voltage is: where the time constant and have the following forms: , , , and are the equivalent resistances (including the cross coupled inverters) loading the output node of the delay cell, the resistance of MP1 (Figure 3b) working as a switch, and the equivalent variable resistance of the transmission gate labeled "RV" (see Figure 4), respectively. The large signal oscillation frequency can be written as [15]: where is the propagation delay and M is the number of delay cells. It is defined as the time lapse between the ideal input step and the moment when the output ramp crosses the trip point of the next delay cell. Considering that the switching point of the delay cell is at VDD 2 ⁄ and applying Equation (2), is written as: Note that and depend on the strength of the positive reaction of the cross-coupled inverters.   Let us consider the schematic of the delay cell depicted in Figure 3. The reset signal, R, is disabled, being set to VDD. The half circuit of the delay cell ( Figure 4a) can be employed to approximate the oscillation frequency of the VCRO. By solving the differential equation of the step response, the output voltage is: where the time constant τ n and τ p have the following forms: R eqn , R eqp , R ON , and R V are the equivalent resistances (including the cross coupled inverters) loading the output node of the delay cell, the resistance of MP1 (Figure 3b) working as a switch, and the equivalent variable resistance of the transmission gate labeled "R V " (see Figure 4), respectively.
The large signal oscillation frequency can be written as [15]: where t d is the propagation delay and M is the number of delay cells. It is defined as the time lapse between the ideal input step and the moment when the output ramp crosses the trip point of the next delay cell. Considering that the switching point of the delay cell is at VDD/2 and applying Equation (2), t d is written as: Note that R eqn and R eqp depend on the strength of the positive reaction of the cross-coupled inverters.  Let us consider the schematic of the delay cell depicted in Figure 3. The reset signal, R, is disabled, being set to VDD. The half circuit of the delay cell ( Figure 4a) can be employed to approximate the oscillation frequency of the VCRO. By solving the differential equation of the step response, the output voltage is: where the time constant and have the following forms: , , , and are the equivalent resistances (including the cross coupled inverters) loading the output node of the delay cell, the resistance of MP1 (Figure 3b) working as a switch, and the equivalent variable resistance of the transmission gate labeled "RV" (see Figure 4), respectively. The large signal oscillation frequency can be written as [15]: where is the propagation delay and M is the number of delay cells. It is defined as the time lapse between the ideal input step and the moment when the output ramp crosses the trip point of the next delay cell. Considering that the switching point of the delay cell is at VDD 2 ⁄ and applying Equation (2), is written as: Note that and depend on the strength of the positive reaction of the cross-coupled inverters.

Temperature Dependence
Equations (4) and (5) are employed to analyze the dependence of f o on temperature variations. The carrier mobility and threshold voltage of the transistors along the signal path depend on the temperature (Equation (6)) which involves changes of t d . From now on, let us consider that the threshold voltages of both NMOS (N channel metal-oxide semiconductor) and PMOS (P channel metal-oxide semiconductor) transistors are positive, i.e., V T N > 0 and V T P > 0.
where the temperature coefficient for both transistors is negative [16]: Then the temperature derivative of f o is: which involves the computation of the temperature derivative of t d : Rewriting Equation (9), we find that the sign of ∂t d /∂T depends on the sign of ∂R eqn /∂T, ∂R V /∂T, and ∂R ON /∂T: Let us suppose that R eqn , R ON , and R V are linear and the equivalent resistances are approximated as: This assumption is made only to simplify the computation of the derivatives which are written as follows: 1 where R V,MN and R V,MP are the two components of the transmission gate. We have evaluated Equations (13) and (14) to find the sign of the derivatives, which is not obvious in this case. Based on simulation results, ∆T, ∆µ n , ∆µ p , ∆V T N , and ∆V T P are of 100, −0.013, −0.005, −85 mV, and −95 mV, respectively. Under these circumstances, the derivatives from Equations (13) and (14) are positive, leading to a positive derivative of t d .
Hence the derivative of the oscillation frequency, f o , and the TDC time bin, T bin , with respect to temperature can be expressed as: Equation (15) shows that f o decreases as the temperature rises. It will also be proved by the experimental results, in the next section. Moreover, the model of the oscillation frequency (see Equations (4) and (5)) is demonstrated in Section 4.1 by comparing it with the measurement results.

Voltage Supply Dependence
In order to analyze this dependence, we use the same model for the oscillation frequency and time bin as in the previous subsection.
Similar with the result obtained for the temperature variation, it has been found that the sign of ∂t d /∂VDD depends on the sign of ∂R eqn /∂VDD, ∂R V /∂VDD, and ∂R ON /∂VDD: Hence the derivatives of R eqn , R ON , and R V are written as follows: This time, according to Equations (18) and (19), it is obvious that the derivative of the time delay to the voltage supply is negative (Equation (17)).
Again, evaluating the effect on the time bin by calculating the partial derivative of T bin to the voltage supply, we found that: The time bin decreases when VDD increases. This fulfills our expectations because the oscillation frequency grows with the voltage supply.

Process Parameter Variation Effect
The variation of the process parameters leads to deviations of the VCRO oscillation frequency,  (1)). The global compensation loop is also employed to minimize ∆ f o from chip-to-chip.
where M is the number of pseudo-differential delay cells. Let us consider that ∆ f o is due to the deviations of the variable resistance and lumped capacitance, namely ∆R V and ∆C L , respectively. These deviations are caused by the variation of process parameters, such as electron and hole mobility, gate oxide thickness, threshold voltage, and transistor length and width. Assume that ∆R V and ∆C L are normally distributed with zero mean and non-zero standard deviation.
The chip-to-chip relative deviation of the oscillator frequency of an individual VCRO, The contribution of (∆R V /R V ) 2 can be expressed as a function of (∆V T ) 2 and (∆β/β) 2 that are inversely proportional to the device area [17]: The contribution of (∆C L /C L ) 2 is evaluated taking into account that C L is a lumped capacitor that is a sum of α i C ox W i L i capacitances, where α i is either 1, 2/3, or 1/2 depending on the transistor's operation point. The subscription i is either MN, MN1, MN2, MP, MP1, or MP2. Therefore the relative deviation of the output capacitance is written as: According to Equations (22)-(24), the larger the area of the devices, the smaller the relative deviation of f o . The area of the transistors cannot be increased too much because the occupied area is one of the top priorities of the design. Under these circumstances, the compensation loop is successfully used to reduce the drift of f o due to the chip-to-chip process parameters' variation. Further improvement can be done by applying an off-chip compensation based on look-up tables.
The proposed model is compared to the simulation and measurement results of over 30 samples. This discussion will be developed in Section 4.4.

Experimental Results
The analysis presented in the previous section is experimentally confirmed by measurements on a prototype chip. First, we will illustrate the dependence of the T bin on the control voltage, TUNE. Afterwards, we will display measurements on the effect of each PVT variation on T bin , with (TUNE is an internal voltage reference provided by the PLL loop filter) and without (TUNE is an external voltage reference) activating the compensation loop.

Time Bin of the TDC Array
As mentioned before, the reference voltage for the array of VCROs is provided by an on-chip PLL. Also, by changing the loop division factor, the time resolution of the sensor can be set to a different value. In our prototype chip, the time resolution of the TDCs ranges between 145 ps and 357 ps ( Figure 5). This measurement has been reported as a preliminary result in [11]. The output frequency of the oscillator varies between 850 MHz and 350 MHz. The frequency divider of the PLL takes about 15.5 µs to change its configuration; then the locking time is less than 3 µs. Figure 5b shows the change in frequency of the VCRO, at pixel (64, 64) when the loop division factor changes from 15 down to 8. Therefore the oscillation frequency jumps from 711 MHz to 355 MHz. We have measured the TDC time bin as a function of the VCRO reference voltage, TUNE. The oscillation frequency has been analytically computed according to Equations (4) and (5). We have determined the piece-wise linearized resistances + (Figure 6b-circle marker) and from simulations. Note that is smaller than and does not depend on the TUNE voltage; besides, is much larger than + , and for simplicity we have considered a constant value of 30 kΩ. With these values, we have fitted the predicted by using Equation (5) (Figure 6a-circle marker) on the measured (Figure 6a-asterisk marker) and found the output capacitance of the delay cell, (Figure 6b-diamond marker). The TDC time bin as a function of PLL division factor has been measured as well (Figure 6a-dot marker). Note that the X-axis is the division factor N of the PLL instead of a voltage We have measured the TDC time bin as a function of the VCRO reference voltage, TUNE. The oscillation frequency has been analytically computed according to Equations (4) and (5). We have determined the piece-wise linearized resistances R V + R ON (Figure 6b-circle marker) and R eqn from simulations. Note that R ON is smaller than R V and does not depend on the TUNE voltage; besides, R eqn is much larger than R V + R ON , and for simplicity we have considered a constant value of 30 kΩ.
With these values, we have fitted the predicted t d by using Equation (5) (Figure 6a-circle marker) on the measured t d (Figure 6a-asterisk marker) and found the output capacitance of the delay cell, C L (Figure 6b-diamond marker).
where is the core oscillator sensitivity to voltage control, , and is the nominal oscillation frequency of the VCRO. M is the number of delay cells. If the voltage reference is provided by the on-chip PLL, then the time bin is written as: where is the frequency division factor, and , is the PLL reference frequency. Notice that the best time bin is limited by the PLL which goes out of lock (see Figure 6a-black curve with dot marker). The single shot precision of the TDC is affected by the cumulative jitter, , of the VCRO. In order to measure it, we selected the VCRO of a test pixel and connected its frequency control voltage to the internal reference provided by the PLL loop filter. The jitter is measured over a time window corresponding to the TDC full range, namely 2 . The standard deviation of is depicted in Figure 7. It is worth mentioning that for division factors larger than 17, the PLL goes out of lock.  The TDC time bin as a function of PLL division factor has been measured as well (Figure 6a-dot marker). Note that the X-axis is the division factor N of the PLL instead of a voltage signal. This is because N is the actual control input which in turn is proportional to the internal reference voltage which controls the TDC array in this case.
A first approximation of the in-pixel TDC time bin, considering that the core oscillator has an external voltage reference is: where K VCRO is the core oscillator sensitivity to voltage control, V re f , and f o is the nominal oscillation frequency of the VCRO. M is the number of delay cells. If the voltage reference is provided by the on-chip PLL, then the time bin is written as: where N is the frequency division factor, and f re f ,PLL is the PLL reference frequency. Notice that the best time bin is limited by the PLL which goes out of lock (see Figure 6a-black curve with dot marker).
The single shot precision of the TDC is affected by the cumulative jitter, σ c , of the VCRO. In order to measure it, we selected the VCRO of a test pixel and connected its frequency control voltage to the internal reference provided by the PLL loop filter. The jitter is measured over a time window corresponding to the TDC full range, namely 2 11 T bin . The standard deviation of σ c is depicted in Figure 7. It is worth mentioning that for division factors larger than 17, the PLL goes out of lock. Thus, the ripple on the loop filter increases. According to Equation (1), this ripple modulates the output frequency of the VCRO, and hence the T bin . This is the reason why the jitter increases when the PLL goes out of range. Thus, the ripple on the loop filter increases. According to Equation (1), this ripple modulates the output frequency of the VCRO, and hence the . This is the reason why the jitter increases when the PLL goes out of range.

Compensation of Temperature Variations
The time bins of the array of TDCs are sensitive to temperature variations. According to Equation (16), the TDC time bin increases when the temperature rises which it is confirmed by the measurement results (Figure 8a-square marker). Considering that is the lumped parasitic capacitor connected to the output node of the delay cell, it mainly depends on the transistors' geometry and their operating points. Thus it is assumed to be invariant to temperature. Therefore by fitting the modeled (Figure 8a: without compensation-diamond marker; with compensation-asterisk marker) on the measured (Figure 8a: without compensation-square marker; with compensation-circle marker) we have found the dependence of the resistance + on temperature (Figure 8b: without compensation-diamond marker; with compensation-asterisk marker). For simplicity, has been considered constant.

Compensation of Temperature Variations
The time bins of the array of TDCs are sensitive to temperature variations. According to Equation (16), the TDC time bin increases when the temperature rises which it is confirmed by the measurement results (Figure 8a-square marker). Considering that C L is the lumped parasitic capacitor connected to the output node of the delay cell, it mainly depends on the transistors' geometry and their operating points. Thus it is assumed to be invariant to temperature. Therefore by fitting the modeled t d (Figure 8a: without compensation-diamond marker; with compensation-asterisk marker) on the measured t d (Figure 8a: without compensation-square marker; with compensation-circle marker) we have found the dependence of the resistance R V + R ON on temperature (Figure 8b: without compensation-diamond marker; with compensation-asterisk marker). For simplicity, R eqn has been considered constant.
The compensation mechanism is explained in Figure 2. As long as the PLL is locked, the loop acts as follows: if the temperature rises, the oscillation frequency f o of the master VCRO decreases (see Equation (15)). Consequently, the frequency control voltage increases, causing f o to increase. This fact is demonstrated by the measurements displayed in Figure 9 for the three different frequency division factors. Figure 10 proves that the oscillation frequency of the master VCRO is invariant to temperature. This temperature-invariant oscillation frequency is employed to generate a control voltage that feeds the frequency control input of the slave VCROs incorporated in the TDC array. The effectiveness of this compensation scheme is evaluated in Figure 8. The spreading of the T bin caused by temperature variation is significantly lowered from 20% down to 2.4%, with average values of 202.2 ps and 198 ps. range; the frequency control voltage of the VCRO is connected to the internal reference provided by the phase-locked loop (PLL) loop filter.

Compensation of Temperature Variations
The time bins of the array of TDCs are sensitive to temperature variations. According to Equation (16), the TDC time bin increases when the temperature rises which it is confirmed by the measurement results (Figure 8a-square marker). Considering that is the lumped parasitic capacitor connected to the output node of the delay cell, it mainly depends on the transistors' geometry and their operating points. Thus it is assumed to be invariant to temperature. Therefore by fitting the modeled (Figure 8a: without compensation-diamond marker; with compensation-asterisk marker) on the measured (Figure 8a: without compensation-square marker; with compensation-circle marker) we have found the dependence of the resistance + on temperature (Figure 8b: without compensation-diamond marker; with compensation-asterisk marker). For simplicity, has been considered constant.
(a) (b) Figure 8. (a) Average T dependence on temperature variation: with compensation (model-asterisk marker; measurement-circle marker) and without compensation (model-diamond marker; measurement-square marker) (b) Equivalent resistance + as a function of temperature: with compensation-asterisk marker; without compensation-diamond marker. The compensation mechanism is explained in Figure 2. As long as the PLL is locked, the loop acts as follows: if the temperature rises, the oscillation frequency of the master VCRO decreases (see Equation (15)). Consequently, the frequency control voltage increases, causing to increase. This fact is demonstrated by the measurements displayed in Figure 9 for the three different frequency division factors. Figure 10 proves that the oscillation frequency of the master VCRO is invariant to temperature. This temperature-invariant oscillation frequency is employed to generate a control voltage that feeds the frequency control input of the slave VCROs incorporated in the TDC array. The effectiveness of this compensation scheme is evaluated in Figure 8. The spreading of the caused by temperature variation is significantly lowered from 20% down to 2.4%, with average values of 202.2 ps and 198 ps.  In order to have a better understanding of these deviations from the application point of view, one has to convert them into time intervals and distances. Without compensation, the peak-to-peak deviation of is of 38.7 ps which leads to an equivalent depth error of 11.88 m at a maximum distance range of 62 m. With compensation, the error decreases to 1.4 m at a maximum distance range of 60.8 m. The compensation mechanism is explained in Figure 2. As long as the PLL is locked, the loop acts as follows: if the temperature rises, the oscillation frequency of the master VCRO decreases (see Equation (15)). Consequently, the frequency control voltage increases, causing to increase. This fact is demonstrated by the measurements displayed in Figure 9 for the three different frequency division factors. Figure 10 proves that the oscillation frequency of the master VCRO is invariant to temperature. This temperature-invariant oscillation frequency is employed to generate a control voltage that feeds the frequency control input of the slave VCROs incorporated in the TDC array. The effectiveness of this compensation scheme is evaluated in Figure 8. The spreading of the caused by temperature variation is significantly lowered from 20% down to 2.4%, with average values of 202.2 ps and 198 ps.  In order to have a better understanding of these deviations from the application point of view, one has to convert them into time intervals and distances. Without compensation, the peak-to-peak deviation of is of 38.7 ps which leads to an equivalent depth error of 11.88 m at a maximum distance range of 62 m. With compensation, the error decreases to 1.4 m at a maximum distance range of 60.8 m. In order to have a better understanding of these deviations from the application point of view, one has to convert them into time intervals and distances. Without compensation, the peak-to-peak deviation of T bin is of 38.7 ps which leads to an equivalent depth error of 11.88 m at a maximum distance range of 62 m. With compensation, the error decreases to 1.4 m at a maximum distance range of 60.8 m.

Compensation of Voltage Supply Variations
According to Equation (20), the TDC time bin or the time delay decreases when the voltage supply rises. This prediction has been confirmed by the measurement depicted in Figure 11a-square marker. Similar to temperature variation, let us consider that the C L and R eqn deviations due to VDD changes are neglected. By fitting the modeled t d (Figure 11a: without compensation-diamond marker; with compensation-asterisk marker) to the measured t d (Figure 11a: without compensation-square marker; with compensation-circle marker), we have found the dependence of R V + R ON on the VDD variations (Figure 11b: with compensation-asterisk marker; without compensation-diamond marker). The average TDC time bin measured for the uncompensated and compensated TDC array is of 181.5 ps and 220.7 ps, respectively. Let us consider a common variation of the voltage supply of ±10% from the nominal value of 1. (a) (b) Figure 11. (a) Average T dependence on VDD: with compensation (model-asterisk marker; measurement-circle marker) and without compensation (model-diamond marker; measurement-square marker) (b) Equivalent resistance + as a function of temperature: with compensated-asterisk marker; without compensation-diamond marker.
Note that the compensation loop stays locked for a wider range of VDD, i.e., from 1.4 V to 2.6 V. The behavior of the PLL with the variation of the voltage supply is revealed in Figure 12 as follows. Figure 12a shows that different synthesized frequencies are locked while the voltage supply varies from 1.7 V to 2.55 V. VCROF1, 2, 3 are the output voltages of the control loop when is 9, 12, and 16. These values correspond to output frequencies of 450 MHz, 600 MHz, and 800 MHz, respectively.  Figure 11.
(a) Average T bin dependence on VDD: with compensation (model-asterisk marker; measurement-circle marker) and without compensation (model-diamond marker; measurement-square marker) (b) Equivalent resistance R V + R ON as a function of temperature: with compensated-asterisk marker; without compensation-diamond marker.
Note that the compensation loop stays locked for a wider range of VDD, i.e., from 1.4 V to 2.6 V. The behavior of the PLL with the variation of the voltage supply is revealed in Figure 12 as follows. Figure 12a shows that different synthesized frequencies are locked while the voltage supply varies from 1.7 V to 2.55 V. VCRO F1, 2, 3 are the output voltages of the control loop when N is 9, 12, and 16. These values correspond to output frequencies of 450 MHz, 600 MHz, and 800 MHz, respectively.
The graph in Figure 12b shows how the compensation loop works. V F1, 2, 3 are the voltages on the loop filter when N is 9, 12, and 16, respectively, and V ext is an external analog voltage reference. As it has been demonstrated, the VCRO output frequency increases when the voltage supply rises. The loop acts to cancel this variation by decreasing the internal reference voltage taken from the loop filter. In this way, the output frequencies of the master VCRO and the array of slave VCROs are decoupled from the voltage supply variation. Figure 11. (a) Average T dependence on VDD: with compensation (model-asterisk marker; measurement-circle marker) and without compensation (model-diamond marker; measurement-square marker) (b) Equivalent resistance + as a function of temperature: with compensated-asterisk marker; without compensation-diamond marker.
Note that the compensation loop stays locked for a wider range of VDD, i.e., from 1.4 V to 2.6 V. The behavior of the PLL with the variation of the voltage supply is revealed in Figure 12 as follows. Figure 12a shows that different synthesized frequencies are locked while the voltage supply varies from 1.7 V to 2.55 V. VCROF1, 2, 3 are the output voltages of the control loop when is 9, 12, and 16. These values correspond to output frequencies of 450 MHz, 600 MHz, and 800 MHz, respectively.

Attenuation of the Effect of the Process Parameters' Variation
The relative deviation of f o due to process variation has been modeled. It depends on the relative deviations of R V and C L which subsequently are modeled by Equations (23) and (24). The prediction of Equation (22) is compared with the simulation results and measurements (see Table 1).
This analysis is backed up by the following discussion around the measured, predicted, and experimental results. To start, a Monte Carlo post-layout simulation has been performed to determine the standard deviation of f o due to process variation. The simulation results are depicted in Figure 13. The graph in Figure 12b shows how the compensation loop works. VF1, 2, 3 are the voltages on the loop filter when is 9, 12, and 16, respectively, and Vext is an external analog voltage reference. As it has been demonstrated, the VCRO output frequency increases when the voltage supply rises.
The loop acts to cancel this variation by decreasing the internal reference voltage taken from the loop filter. In this way, the output frequencies of the master VCRO and the array of slave VCROs are decoupled from the voltage supply variation.

Attenuation of the Effect of the Process Parameters' Variation
The relative deviation of due to process variation has been modeled. It depends on the relative deviations of and which subsequently are modeled by Equations (23) and (24). The prediction of Equation (22) is compared with the simulation results and measurements (see Table 1).
This analysis is backed up by the following discussion around the measured, predicted, and experimental results. To start, a Monte Carlo post-layout simulation has been performed to determine the standard deviation of due to process variation. The simulation results are depicted in Figure 13 Table 2. They have been extracted from the previous Monte Carlo simulation.   V o = 0.9 V, e ox = 35.13 pF/m. The TUNE signal has been set such that the time bin of the TDC array falls in the middle of its range. The rest of the parameters are displayed in Table 2. They have been extracted from the previous Monte Carlo simulation.  Ultimately, the predicted and simulated results have to be compared to the experimental results. For this purpose, 30 samples have been measured by evaluating the performance of a certain pixel. The effectiveness of the parameter variation compensation loop is proved as well. Each sample has been evaluated in two different scenarios. In the first experimental setup, we have connected the analog reference of the array of slave VCROs to an external voltage set at 1.31 V, as it was in the simulation. The second measurement setup consists of setting the analog reference to be the internal PLL loop filter voltage. The frequency divider of the PLL is set such that the output voltage given by the loop filter has to have a value close to the one chosen for the external reference voltage. The TDC time bin has been measured in both scenarios for all the samples (Figure 14). Without compensation, the time bin has a standard deviation of 5.2 ps, for an average value of 198.2 ps. With compensation, the standard deviation of the time bin is 2 ps with an average value of 203.8 ps. The span of the time bin decreases significantly as shown in the upper side of Figure 14. Note that the global compensation loop (Figure 2) minimizes the deviation of f o , and hence T bin , due to chip-to-chip process parameters' deviation. This compensation scheme cannot be applied to cancel the deviations of the TDCs time bin due to pixel-to-pixel mismatches.  Ultimately, the predicted and simulated results have to be compared to the experimental results. For this purpose, 30 samples have been measured by evaluating the performance of a certain pixel. The effectiveness of the parameter variation compensation loop is proved as well. Each sample has been evaluated in two different scenarios. In the first experimental setup, we have connected the analog reference of the array of slave VCROs to an external voltage set at 1.31 V, as it was in the simulation. The second measurement setup consists of setting the analog reference to be the internal PLL loop filter voltage. The frequency divider of the PLL is set such that the output voltage given by the loop filter has to have a value close to the one chosen for the external reference voltage. The TDC time bin has been measured in both scenarios for all the samples (Figure 14). Without compensation, the time bin has a standard deviation of 5.2 ps, for an average value of 198.2 ps. With compensation, the standard deviation of the time bin is 2 ps with an average value of 203.8 ps. The span of the time bin decreases significantly as shown in the upper side of Figure 14. Note that the global compensation loop (Figure 2) minimizes the deviation of , and hence , due to chip-to-chip process parameters' deviation. This compensation scheme cannot be applied to cancel the deviations of the TDCs time bin due to pixel-to-pixel mismatches. The 64 × 64-pixels dToF-CIS has the following specifications: (i) Pixel size of 64 × 64 µm 2 , fill factor of 2.7%, and in-pixel TDC area of 1740 µm 2 ; (ii) The TDC least significant bit (LSB) variation caused by pixel-to-pixel mismatches is between 146.7 ps and 155.6 ps. It means a standard deviation of 32 codes at full scale. The RMS DNL and INL computed across the array are less than 0.35 LSB and 1.5 LSB [18]; (iii) The single shot precision at 10% and 90% of the full range has a standard deviation of 0.79 and 13.88 codes, respectively; (iv) The TDC average power consumption of 9 µW has been obtained from post-layout worst-case simulations. In order to have a fair comparison with reference [10], we have normalized it per 10 ns conversion time and 500 k conversions per second; (v) As has been verified by the experiments, the global compensation scheme considerably reduces the spreading of the TDCs time bin from: (a) 20% down to 2.4% while the temperature ranges from 0 • C to 100 • C; (b) 27% down to 0.27%, when the voltage supply changes within ±10% from the nominal value of 1.8 V; (c) 5.2 ps to 2 ps standard deviation due to process variation, with an average value of 198.2 ps and 203.8 ps. 30 samples have been measured during this experiment.
The SPAD camera prototype is aimed at depth map photography. A demonstrative snapshot is shown in Figure 15. The laser illuminates the scene from the right side which explains the shadow on the left side of the picture. Thus no photons from the laser reach back to the sensor. The same occurs to the area from the upper side of the picture (Figure 15b-black marker). The pixels corresponding to these areas are triggered only by uncorrelated noise. The SPAD camera prototype is aimed at depth map photography. A demonstrative snapshot is shown in Figure 15. The laser illuminates the scene from the right side which explains the shadow on the left side of the picture. Thus no photons from the laser reach back to the sensor. The same occurs to the area from the upper side of the picture (Figure 15b-black marker). The pixels corresponding to these areas are triggered only by uncorrelated noise.

Conclusions
Direct ToF-CIS with in-pixel TDCs are sensitive to PVT variations as they lead to deviations of the locally-generated multiphase clock which in turn is inversely proportional to the TDC time bin. Consequently, these variations are causing changes in the gain of the TDC, and hence the output code and distance estimation in 3D ranging applications. This work covers a detailed analysis of these variations and their impact on the performance of the imager. The design and characterization of a global compensation loop against the aforementioned non-idealities is presented as well. The calculations are validated by simulations and/or measurement results.
Author Contributions: Ion Vornicu was the principal designer of the circuit reported in this paper. Ricardo Carmona-Galán and Ángel Rodríguez-Vázquez also contributed crucially for its successful implementation.

Conflicts of Interest:
The authors declare no conflict of interest.

Conclusions
Direct ToF-CIS with in-pixel TDCs are sensitive to PVT variations as they lead to deviations of the locally-generated multiphase clock which in turn is inversely proportional to the TDC time bin. Consequently, these variations are causing changes in the gain of the TDC, and hence the output code and distance estimation in 3D ranging applications. This work covers a detailed analysis of these variations and their impact on the performance of the imager. The design and characterization of a global compensation loop against the aforementioned non-idealities is presented as well. The calculations are validated by simulations and/or measurement results.