Novel Compensation Scheme for the Modulation Gain to Suppress the Quantization-Induced Bias in a Fiber Optic Gyroscope

A novel digital compensation scheme is demonstrated to control the gain of the modulation chain and suppress the influence of quantization error on bias. The error produced by the quantization multiplied by the scaling factor is theoretically analyzed. Simulations indicate that the quantization error varies with the input angular velocity and temperature, which is verified by experiments. By switching the integration and compression operations in the modulation chain, this quantization error is reduced, while automatic reset of the digital phase ramp register is achieved. We test the scheme in a fiber optic gyroscope. The test results reveal that the quantization-induced bias is suppressed and the residual bias is two times less than the desired accuracy with data accumulated over one-second sample interval. The scheme is a feasible method to miniaturize fiber optic gyroscope using a totally digital circuit for compensation of the modulation gain.


Introduction
The fiber optic gyroscope (FOG) is widely used in navigation applications [1]. In an all-digital closed-loop FOG, the electro-optic coefficient of the integrated optic modulator (IOM) varies with temperature. Hence, the gain of the modulation chain drifts, which affects the scale factor stability [2]. Meanwhile, when the digital phase ramp resets, the height of the phase reset is no longer equal to 2π radian, and the imperfect 2π reset deteriorates bias and noise [3][4][5]. Conventionally, the gain drift is compensated by a second feedback loop using another D/A converter (DAC), through which the reference voltage of the DAC in the modulation chain is adjusted [2][3][4]6,7]. This analog compensation method achieves high scale-factor stability without deterioration of bias and noise, but it needs more complex electronics, which means extra volume and power consumption.
To simplify the circuit, a digital compensation scheme has been put forward by integrating the function of the second feedback loop into a digital logic chip [8]. Ma et al. focused on the verification of the effect of using a digital compensation procedure for replacing the classical second feedback loop on the scale factor stability. However, the quantization errors, which might induce unstable spurious bias, were not discussed. At that time, although the spurious bias deviated from the normal value, the bias repeatability at a fixed temperature met the performance requirements, and the variation of spurious bias with scaling factor (in fact, temperature induced variation of 2π reset voltage) was compensated by temperature compensation procedure mainly for suppressing the Shup error in fiber coil. Latterly, we compensated the spurious bias by adding the truncated part of the products of scaling factor and digital phase step onto the output of FOG based on the digital algorithm in [8]. Besides, the algorithmic implementation is complicated because of the register operation of the forced reset.
In this paper, we present the improved digital compensation method, which depressed the unstable spurious bias by differential operation of the optical path and time-average, without any additional procedures. We believe it is time to discuss the quantization errors of both kinds of digital compensation algorithms. The quantization errors on the bias are theoretically analyzed based on the simplified model of the digital close-loop FOG. Next, the suppression of the quantization error is demonstrated in the improved scheme, which leaves the auto-reset of the digital phase ramp known as one of the advantages of all digital close-loop FOG. Simulations are carried out to investigate in detail the bias of the two digital compensation schemes at different input angular velocities and digital scaling factors. Finally, we validate the improved scheme by comparing the performance of the two types of digital schemes with that of the conventional analog method on the same FOG.

Analysis of the Compensation for the Gain Drift of the Modulation Chain
According to the implementation of an all-digital closed-loop FOG, the linearized model is simplified by ignoring the dynamic or transient state [9][10][11][12], as shown in Figure 1. algorithm in [8]. Besides, the algorithmic implementation is complicated because of the register operation of the forced reset.
In this paper, we present the improved digital compensation method, which depressed the unstable spurious bias by differential operation of the optical path and time-average, without any additional procedures. We believe it is time to discuss the quantization errors of both kinds of digital compensation algorithms. The quantization errors on the bias are theoretically analyzed based on the simplified model of the digital close-loop FOG. Next, the suppression of the quantization error is demonstrated in the improved scheme, which leaves the auto-reset of the digital phase ramp known as one of the advantages of all digital close-loop FOG. Simulations are carried out to investigate in detail the bias of the two digital compensation schemes at different input angular velocities and digital scaling factors. Finally, we validate the improved scheme by comparing the performance of the two types of digital schemes with that of the conventional analog method on the same FOG.

Analysis of the Compensation for the Gain Drift of the Modulation Chain
According to the implementation of an all-digital closed-loop FOG, the linearized model is simplified by ignoring the dynamic or transient state [9][10][11][12], as shown in Figure 1. : the integration operation, (1 − ): the differential operation for the delay between two counter-propagating light waves.
In view of the configuration of the modulation chain and the digital phase ramp reset, the height of the phase reset should be 2π radians when the dynamic range width of the ramp register is 2 (n is the bit length of the register). The modulation gain is [2]: where is the DAC coefficient, is the gain of buffer amplifier in the modulation chain, and is the electro-optic coefficient of the IOM. In Equation (1), not only should the ratio (modulation gain ) be kept constant to ensure the scale factor stability, but the numerator (the height of the phase reset ) should also be exactly 2π radians to avoid the deterioration of the bias and noise. In the conventional analog method, the gain drift is compensated by adjusting the DAC coefficient to counteract the change of the modulator coefficient , and the mentioned requirements of the ratio and the numerator are satisfied simultaneously.
However, when the function of gain compensation is integrated into a digital logic chip, the analog coefficient and in Equation (1) can no longer be regulated. Besides, the dynamic range width of the ramp register is adjusted to 2 to guarantee that the height of the phase reset equals 2π radians. Synchronously, a scaling factor is introduced to compensate for the change of the modulation gain, as shown in Figure 2. In [8], this scheme is adopted, and we refer to it as the First-Compression-Last-Integration (FCLI) scheme. . Ω: the input angular velocity, C : the output data of the FOG, K s : the proportional coefficient of the Sagnac Effect, K D : the total gain of the detection chain, K FIL : the gain of the digital filter in the output chain, and K F : the total gain of the modulation chain, 1/ 1 − z −1 : the integration operation, 1 − z −1 : the differential operation for the delay between two counter-propagating light waves.
In view of the configuration of the modulation chain and the digital phase ramp reset, the height of the phase reset φ r should be 2π radians when the dynamic range width D r of the ramp register is 2 n (n is the bit length of the register). The modulation gain K F is [2]: where K DA . is the DAC coefficient, K A is the gain of buffer amplifier in the modulation chain, and K IOM is the electro-optic coefficient of the IOM. In Equation (1), not only should the ratio (modulation gain K F ) be kept constant to ensure the scale factor stability, but the numerator (the height of the phase reset φ r ) should also be exactly 2π radians to avoid the deterioration of the bias and noise. In the conventional analog method, the gain drift is compensated by adjusting the DAC coefficient K DA to counteract the change of the modulator coefficient K IOM , and the mentioned requirements of the ratio and the numerator are satisfied simultaneously.
However, when the function of gain compensation is integrated into a digital logic chip, the analog coefficient K DA and K A in Equation (1) can no longer be regulated. Besides, the dynamic range width D r of the ramp register is adjusted to 2 x to guarantee that the height of the phase reset equals 2π radians. Synchronously, a scaling factor G is introduced to compensate for the change of the modulation gain, as shown in Figure 2. In [8], this scheme is adopted, and we refer to it as the First-Compression-Last-Integration (FCLI) scheme. It is easy to determine that the scaling factor equals 2 2 ⁄ , and the compensated modulation gain ′ is given by: When the phase step s is compressed by multiplying the scaling factor, the quantization error δ is induced by the truncation operation due to the finite word-length of the register [13]. The compressed phase step is: where represents the truncation operation. Then, the compressed phase step is integrated to generate the phase ramp , and: After the differential operation, the time-average of the feedback phase shift is: where 〈 〉 represents the calculation operation of time-average. In Equation (5), the time-average of the feedback phase shift 〈 〉 is strictly proportional to 〈 − ⁄ 〉 rather than the time-average of the phase step 〈 〉, and it is equivalent to induce the error 〈 ⁄ 〉 in the phase step of the output chain.
The equivalent bias Ω of angular velocity is: According to Equation (6), the equivalent bias varies with both the scaling factor and the quantization error , which are affected by temperature and input angular velocity, respectively.
As for the FCLI algorithm implemented according to [8], the purpose of the second feedback loop is to obtain the dynamic range width 2 . Then, the real value of the digital phase ramp register is set by forced reset. The forced reset under various operating conditions makes the FCLI scheme more complicated than the conventional analog scheme, in which automatic reset is adopted.

First-Integration-Last-Compression Scheme
In this paper, the scaling factor is moved after the integrator of the modulation chain, which is equivalent to in front of the integrator in consideration of the total gain of the modulation chain, as shown in Figure 3. We name this scheme as the First-Integration-Last-Compression (FILC) scheme.  It is easy to determine that the scaling factor G equals 2 x /2 n , and the compensated modulation gain K F is given by: When the phase step s i is compressed by multiplying the scaling factor, the quantization error δ i is induced by the truncation operation due to the finite word-length of the register [13]. The compressed phase step is: where represents the truncation operation. Then, the compressed phase step is integrated to generate the phase ramp r i , and: After the differential operation, the time-average of the feedback phase shift f i is: where represents the calculation operation of time-average. In Equation (5), the time-average of the feedback phase shift f i is strictly proportional to s i − δ i /G rather than the time-average of the phase step s i , and it is equivalent to induce the error δ i /G in the phase step of the output chain.
The equivalent bias Ω bias of angular velocity is: According to Equation (6), the equivalent bias varies with both the scaling factor G and the quantization error δ i , which are affected by temperature and input angular velocity, respectively.
As for the FCLI algorithm implemented according to [8], the purpose of the second feedback loop is to obtain the dynamic range width 2 x . Then, the real value of the digital phase ramp register is set by forced reset. The forced reset under various operating conditions makes the FCLI scheme more complicated than the conventional analog scheme, in which automatic reset is adopted.

First-Integration-Last-Compression Scheme
In this paper, the scaling factor G is moved after the integrator of the modulation chain, which is equivalent to G in front of the integrator in consideration of the total gain of the modulation chain, as shown in Figure 3. We name this scheme as the First-Integration-Last-Compression (FILC) scheme. It is easy to determine that the scaling factor equals 2 2 ⁄ , and the compensated modulation gain ′ is given by: When the phase step s is compressed by multiplying the scaling factor, the quantization error δ is induced by the truncation operation due to the finite word-length of the register [13]. The compressed phase step is: where represents the truncation operation. Then, the compressed phase step is integrated to generate the phase ramp , and: After the differential operation, the time-average of the feedback phase shift is: where 〈 〉 represents the calculation operation of time-average. In Equation (5), the time-average of the feedback phase shift 〈 〉 is strictly proportional to 〈 − ⁄ 〉 rather than the time-average of the phase step 〈 〉, and it is equivalent to induce the error 〈 ⁄ 〉 in the phase step of the output chain.
The equivalent bias Ω of angular velocity is: According to Equation (6), the equivalent bias varies with both the scaling factor and the quantization error , which are affected by temperature and input angular velocity, respectively.
As for the FCLI algorithm implemented according to [8], the purpose of the second feedback loop is to obtain the dynamic range width 2 . Then, the real value of the digital phase ramp register is set by forced reset. The forced reset under various operating conditions makes the FCLI scheme more complicated than the conventional analog scheme, in which automatic reset is adopted.

First-Integration-Last-Compression Scheme
In this paper, the scaling factor is moved after the integrator of the modulation chain, which is equivalent to in front of the integrator in consideration of the total gain of the modulation chain, as shown in Figure 3. We name this scheme as the First-Integration-Last-Compression (FILC) scheme.  After integration, compression and differential operation, the feedback phase shift is deduced, which is similar to Equations (4) and (5): As for the current feedback phase shift, the FILC scheme still has the quantization error (δ i−1 − δ i ), but this error is suppressed due to the time-averaging process [2]: And: The time-averaged feedback phase shift is strictly proportional to the time-averaged output phase step in the FILC scheme. That is to say, the phase step is uniform between the modulation chain and the output chain. The quantization error is suppressed by the differential operation of the optical path without any additional digital signal processes.
The algorithmic flow-chart of the FILC scheme is presented in Figure 4. The purpose of the second feedback loop is set to demodulate the scaling factor G directly. The digital phase ramp is reset by automatic overflow with a dynamic range width of 2 n . After compression, the equivalent dynamic range width is transformed to D r = G * 2 n = 2 x , as shown in Figure 5. The requirements for the modulation gain and the height of the phase reset are satisfied simultaneously. After integration, compression and differential operation, the feedback phase shift is deduced, which is similar to Equations (4) and (5): As for the current feedback phase shift, the FILC scheme still has the quantization error ( − ), but this error is suppressed due to the time-averaging process [2]: And: The time-averaged feedback phase shift is strictly proportional to the time-averaged output phase step in the FILC scheme. That is to say, the phase step is uniform between the modulation chain and the output chain. The quantization error is suppressed by the differential operation of the optical path without any additional digital signal processes.
The algorithmic flow-chart of the FILC scheme is presented in Figure 4. The purpose of the second feedback loop is set to demodulate the scaling factor directly. The digital phase ramp is reset by automatic overflow with a dynamic range width of 2 . After compression, the equivalent dynamic range width is transformed to = * 2 = 2 , as shown in Figure 5. The requirements for the modulation gain and the height of the phase reset are satisfied simultaneously.   After integration, compression and differential operation, the feedback phase shift is deduced, which is similar to Equations (4) and (5): As for the current feedback phase shift, the FILC scheme still has the quantization error ( − ), but this error is suppressed due to the time-averaging process [2]: And: The time-averaged feedback phase shift is strictly proportional to the time-averaged output phase step in the FILC scheme. That is to say, the phase step is uniform between the modulation chain and the output chain. The quantization error is suppressed by the differential operation of the optical path without any additional digital signal processes.
The algorithmic flow-chart of the FILC scheme is presented in Figure 4. The purpose of the second feedback loop is set to demodulate the scaling factor directly. The digital phase ramp is reset by automatic overflow with a dynamic range width of 2 . After compression, the equivalent dynamic range width is transformed to = * 2 = 2 , as shown in Figure 5. The requirements for the modulation gain and the height of the phase reset are satisfied simultaneously.   In summary, the improved FILC scheme not only removes the unstable parasitic bias in the original FCLI scheme but also retains the automatic reset, as the conventional analog method does, which simplifies the algorithm implementation. It is a reliable optimized method that integrates the function of gain-control into a digital signal processor, such as Field Programmable Gate Array (FPGA), to miniaturize the FOG.

Simulation and Experiment
In view of the gain compensation of the modulation loop, the two kinds of digital schemes are equivalent and the scaling factors have the same value. The dynamic performance of the digital compensation scheme has been verified by testing whether or not the scaling factor could vary with temperature in real time and, at the same time, the compensation resolution could be ensured [8]. The dynamic performance is not affected by switching the integration and compression operations. In this paper, we focus on the differences in bias resulting from these two kinds of methods.
The designed parameters of the FOG under testing are presented in Table 1, and the desired accuracy is 0.3 • /h with data accumulated over a 1 s sample interval. The schematic diagram of the FOG is shown in Figure 6. The second D/A generates the reference voltage of the first D/A. In the analog scheme, the reference voltage of the first D/A is changed to compensate for the fluctuation of the modulation chain gain caused by varied temperature. Conversely, in the FCLI or FILC scheme, the reference voltage is set to a fixed value while the modulation chain gain is compensated by digital procedure. In Figure 6, the parts denoted by dotted lines are only required in analog scheme. The functional modular and data flow of FILC scheme in the FPGA are also shown in Figure 6. In summary, the improved FILC scheme not only removes the unstable parasitic bias in the original FCLI scheme but also retains the automatic reset, as the conventional analog method does, which simplifies the algorithm implementation. It is a reliable optimized method that integrates the function of gain-control into a digital signal processor, such as Field Programmable Gate Array (FPGA), to miniaturize the FOG.

Simulation and Experiment
In view of the gain compensation of the modulation loop, the two kinds of digital schemes are equivalent and the scaling factors have the same value. The dynamic performance of the digital compensation scheme has been verified by testing whether or not the scaling factor could vary with temperature in real time and, at the same time, the compensation resolution could be ensured [8]. The dynamic performance is not affected by switching the integration and compression operations. In this paper, we focus on the differences in bias resulting from these two kinds of methods.
The designed parameters of the FOG under testing are presented in Table 1, and the desired accuracy is 0.3°/h with data accumulated over a 1 s sample interval. The schematic diagram of the FOG is shown in Figure 6. The second D/A generates the reference voltage of the first D/A. In the analog scheme, the reference voltage of the first D/A is changed to compensate for the fluctuation of the modulation chain gain caused by varied temperature. Conversely, in the FCLI or FILC scheme, the reference voltage is set to a fixed value while the modulation chain gain is compensated by digital procedure. In Figure 6, the parts denoted by dotted lines are only required in analog scheme. The functional modular and data flow of FILC scheme in the FPGA are also shown in Figure 6. According to the analysis in Section 2, we know that the quantization-induced bias is affected by the scaling factor and the input angular velocity. In the simulation and experiment, two different angular velocities (9.6°/h and 11.5°/h) are used as the input according to the axis of the FOG pointing to the sky and the north, respectively, in our laboratory located at 40 degrees north latitude. The According to the analysis in Section 2, we know that the quantization-induced bias is affected by the scaling factor and the input angular velocity. In the simulation and experiment, two different angular velocities (9.6 • /h and 11.5 • /h) are used as the input according to the axis of the FOG pointing to the sky and the north, respectively, in our laboratory located at 40 degrees north latitude. The scaling factor ranges from 0.52 at −40 • C to 0.66 at +60 • C. The bias is simulated according to Equations (6) and (10), as well as tested to evaluate the influences of the quantization error of the FCLI and FILC schemes. The quantization-induced bias is shown in Figure 7. In Figure 7a, the differences between the simulations and experiments of the FCLI scheme can be summarized as the differences of the slope and the intercept of the curves. According to the Equation (6), the quantization error is affected by the Sagnac effect coefficient Ks. Moreover, the intercept of the curves is sensitive to the gain and the noise of the detection chain. It is difficult to measure precisely the K s , the gain of detection chain and the noise of the FOG under test. Therefore, these differences between simulation and experiments in Figure 7a are caused by the fact that the parameters in the simulation are not equal to those in the experiment exactly. In Figure 7b, the simulated spurious bias of the improved scheme induced by compression is suppressed to almost zero. Hence the simulations do not vary with K s , gain and noise in the detection chain. The differences between the simulations and experiments are caused by the bias repeatability of the FOG under test.
In Figure 7, the quantization-induced bias of the FCLI scheme is unstable, and the variation scale is nine times larger than the desired accuracy. However, the maximum residual bias of the FILC scheme is 0.08 • /h, which is two times smaller than the desired accuracy.
Sensors 2017, 17, 823 6 of 9 (6) and (10), as well as tested to evaluate the influences of the quantization error of the FCLI and FILC schemes. The quantization-induced bias is shown in Figure 7. In Figure 7a, the differences between the simulations and experiments of the FCLI scheme can be summarized as the differences of the slope and the intercept of the curves. According to the Equation (6), the quantization error is affected by the Sagnac effect coefficient Ks. Moreover, the intercept of the curves is sensitive to the gain and the noise of the detection chain. It is difficult to measure precisely the , the gain of detection chain and the noise of the FOG under test. Therefore, these differences between simulation and experiments in Figure 7a are caused by the fact that the parameters in the simulation are not equal to those in the experiment exactly. In Figure 7b, the simulated spurious bias of the improved scheme induced by compression is suppressed to almost zero. Hence the simulations do not vary with , gain and noise in the detection chain. The differences between the simulations and experiments are caused by the bias repeatability of the FOG under test.
In Figure 7, the quantization-induced bias of the FCLI scheme is unstable, and the variation scale is nine times larger than the desired accuracy. However, the maximum residual bias of the FILC scheme is 0.08°/h, which is two times smaller than the desired accuracy. The raw output data with its corresponding Allan deviation for the three compensation schemes are shown in Figure 8, which is tested under the condition that the angular velocity is 9.6°/h and the scaling factor is approximately 0.60.
The bias performances of the three compensation methods are listed in Table 2.  The raw output data with its corresponding Allan deviation for the three compensation schemes are shown in Figure 8, which is tested under the condition that the angular velocity is 9.6 • /h and the scaling factor is approximately 0.60. In Table 2, the FILC scheme has a performance similar to the analog compensation scheme. Clearly, the bias of the FCLI scheme is larger than that of the other schemes. The noise of the FCLI scheme is 14% larger than that of the other methods, which is caused mainly by the quantization errors induced by the fluctuation of the scaling factor, as shown in Figure 7a, and partially by its bias drift, as shown in the Allan deviation plot in Figure 8c.
The parameters of the scale factor of those three different schemes are also tested as the input angular velocity increases from 0 to 300°/s with an increment of 10°/s. The scale factor is calculated by the least squares method according to [14]. In Table 3, the scale factors are nearly uniform in the  The bias performances of the three compensation methods are listed in Table 2. In Table 2, the FILC scheme has a performance similar to the analog compensation scheme. Clearly, the bias of the FCLI scheme is larger than that of the other schemes. The noise of the FCLI scheme is 14% larger than that of the other methods, which is caused mainly by the quantization errors induced by the fluctuation of the scaling factor, as shown in Figure 7a, and partially by its bias drift, as shown in the Allan deviation plot in Figure 8c.
The parameters of the scale factor of those three different schemes are also tested as the input angular velocity increases from 0 to 300 • /s with an increment of 10 • /s. The scale factor is calculated by the least squares method according to [14]. In Table 3, the scale factors are nearly uniform in the three schemes, and the tiny differences are caused by gain fluctuation with residual quantization error in digital signal processing. So far, we can fabricate high precision 0.01 • /h FOG without temperature compensation on bias. We believe our method is suitable for those FOGs without temperature compensation on bias.

Conclusions
A novel First-Integration-Last-Compression scheme is proposed to compensate the gain drift of the modulation chain in a fiber optic gyroscope. The FILC scheme guarantees the uniform time-average of the phase step between the modulation chain and the output chain and, consequently, suppresses the adverse effects of the quantization error on the output bias. Meanwhile, the FILC scheme keeps the advantage of automatic reset as an analog compensation scheme does, which simplifies the implementations of digital signal processing.
We verify the First-Integration-Last-Compression scheme on a middle-precision prototype of fiber optic gyroscope. The maximum residual quantization-induced bias achieves a value of 0.08 • /h over −40 • C to +60 • C, which is two times lower than the noise amplitude with data accumulated over one second sample intervals. The scale-factor linearity is 10 ppm. The results indicate that the FILC scheme is a feasible method to miniaturize FOG by integrating the function of the second feedback loop into the digital signal processor.
Author Contributions: All the authors made contributions to this work. The idea was originally from Xiong Pan and Jing Jin; Xiong Pan, Pengcheng Liu proposed the scheme, developed the algorithms, and wrote the manuscript; Pengcheng Liu, Shaobo Zhang completed the simulation, and performed the experiments; Ningfang Song supervised all the work and improved the manuscript in terms of the English presentation.