A 75-ps Gated CMOS Image Sensor with Low Parasitic Light Sensitivity

In this study, a 40 × 48 pixel global shutter complementary metal-oxide-semiconductor (CMOS) image sensor with an adjustable shutter time as low as 75 ps was implemented using a 0.5-μm mixed-signal CMOS process. The implementation consisted of a continuous contact ring around each p+/n-well photodiode in the pixel array in order to apply sufficient light shielding. The parasitic light sensitivity of the in-pixel storage node was measured to be 1/8.5 × 107 when illuminated by a 405-nm diode laser and 1/1.4 × 104 when illuminated by a 650-nm diode laser. The pixel pitch was 24 μm, the size of the square p+/n-well photodiode in each pixel was 7 μm per side, the measured random readout noise was 217 e− rms, and the measured dynamic range of the pixel of the designed chip was 5500:1. The type of gated CMOS image sensor (CIS) that is proposed here can be used in ultra-fast framing cameras to observe non-repeatable fast-evolving phenomena.


Introduction
Fast gated or global shutter cameras with shutter time at a level of tens of picoseconds are widely used in the observation of fast-evolving phenomena, including repeatable and non-repeatable processes. Traditionally, micro-channel plate (MCP)-based gating cameras are used in range imaging systems (time-of-flight depth cameras) and wide-field fluorescence-lifetime imaging microscopy to observe repeatable fast evolving phenomena. In recent years, a large number of solid-state devices have been developed for such applications [1][2][3][4][5].
Currently, MCP-based gated cameras are almost the only type of receive-only 2D imaging device used in applications that require the observation of non-repeatable fast-evolving phenomena, with a time resolution as little as approximately 35 ps [6]. Such applications include plasma expansion dynamics research, charged particle accelerator diagnosis, optical time-of-flight measurements of fast moving objects, and high-resolution photo-acoustic imaging. However, some other successful efforts have also been presented for these purposes that use streak cameras [7] or that rely upon light-absorption-induced modulation of the optical refractive index of a semiconductor sensor medium [8].
A pulse-dilation enhanced gated optical imager can achieve a time resolution of approximately 5 ps [9][10][11], which is an overwhelmingly high speed for receive-only 2D imaging. The drawback of such a device is that it is bulky in size, sensitive to magnetic fields, and relatively low in spatial resolution.
Very fast global shutter complementary metal-oxide-semiconductor (CMOS) readout test chips with on-chip photodiodes have also been implemented [12]. Tests to measure the minimum exposure time when using on-chip photodiodes have achieved results of approximately 200 ps [13], but without

Pixel Circuit Design
In order to obtain the desirable fast photo response, p+/n-well photodiodes are used in the pixel array. Semiconductor processes and device simulations have shown that a small-sized p+/n-well photodiode manufactured using this process has an impulse response time that is shorter than approximately 5 ps, for visible light or near ultraviolet, at a bias of 5 V. Figure 1a shows the simulated photocurrent response of the small-sized p+/n-well photodiode at a 5-V bias after illumination by 1 ps short light pulses with 0.2 pJ of energy. The software used in the device simulation was Silvaco Atlas, and Figure 1b shows the structure and the doping profile of the photodiode used in the device simulation. A wavelength of 558 nm was used in the simulation, which is the maximum emission of a bright ultra-fast scintillator (n-C 6 H 13 NH 3 ) 2 PbI 4 , which is in a natural multiple quantum well (MQW) structure and has a decay component of 390 ps (30%) at room temperature [15]. X-ray or electron sensitivity can be achieved by coupling the proposed image sensor to this type of bright ultra-fast scintillator screen by microscopy.
Sensors 2016, 16,999 2 of 10 practical applications is still limited. To the best of the authors' knowledge, no reports have been given on the parasitic light sensitivity of the global shutter CMOS readout chip while using the onchip photodiodes. If the parasitic light sensitivity does not meet requirements, artifacts will be captured within an image from bright moving objects or light spots after exposure and before the readout [14].
In this paper, the authors present the detailed design, test methods, and results of a low parasitic light sensitivity 40 × 48 pixel gated CMOS image sensor that is sensitive to visible and near ultraviolet light with a shutter time as low as 75 ps, which is manufactured using a 0.5-μm 2-poly 3-metal polycide mixed-signal CMOS process. The type of CMOS image sensor proposed in this paper can be used in ultra-fast framing cameras to observe single-shot fast-evolving phenomena.

Pixel Circuit Design
In order to obtain the desirable fast photo response, p+/n-well photodiodes are used in the pixel array. Semiconductor processes and device simulations have shown that a small-sized p+/n-well photodiode manufactured using this process has an impulse response time that is shorter than approximately 5 ps, for visible light or near ultraviolet, at a bias of 5 V. Figure 1a shows the simulated photocurrent response of the small-sized p+/n-well photodiode at a 5-V bias after illumination by 1 ps short light pulses with 0.2 pJ of energy. The software used in the device simulation was Silvaco Atlas, and Figure 1b shows the structure and the doping profile of the photodiode used in the device simulation. A wavelength of 558 nm was used in the simulation, which is the maximum emission of a bright ultra-fast scintillator (n-C6H13NH3)2PbI4, which is in a natural multiple quantum well (MQW) structure and has a decay component of 390 ps (30%) at room temperature [15]. X-ray or electron sensitivity can be achieved by coupling the proposed image sensor to this type of bright ultra-fast scintillator screen by microscopy. The circuit diagram for a single pixel is shown in Figure 2a. In the design, Vreset, Vstart, and Vend are set to the same value as VDD, and Vselect is set to ground when waiting for the trigger signal. Thus, only the transistors M1 and M2 are turned on. Once triggered, Vstart and subsequently Vend are pulled down to ground in the sequence, within a time interval that is slightly shorter than the exposure time. During exposure, when M1 is turned off and M2 is still on, part of the photo-induced charge is stored on the polysilicon-insulator-polysilicon (PIP) capacitor C1. After exposure, all five transistors of the pixel are turned off. After approximately 14 nanoseconds, Vreset is pulled down to ground, thus pulling up the anode of the photodiode to VDD and forming the final signal voltage on the gate of M3 for the read-out.
A timing chart for Vstart, Vend, Vreset, and the simulated results of the drain voltages of M1 and M2 is shown in Figure 2b. In the simulation, a 6.25-fF capacitor representing the parasitic capacitance was added between the bottom plate of C1 and the ground. Figure 2b shows that the M2 drain voltage The circuit diagram for a single pixel is shown in Figure 2a. In the design, V reset , V start , and V end are set to the same value as V DD , and V select is set to ground when waiting for the trigger signal. Thus, only the transistors M1 and M2 are turned on. Once triggered, V start and subsequently V end are pulled down to ground in the sequence, within a time interval that is slightly shorter than the exposure time. During exposure, when M1 is turned off and M2 is still on, part of the photo-induced charge is stored on the polysilicon-insulator-polysilicon (PIP) capacitor C1. After exposure, all five transistors of the pixel are turned off. After approximately 14 nanoseconds, V reset is pulled down to ground, thus pulling up the anode of the photodiode to V DD and forming the final signal voltage on the gate of M3 for the read-out. drops to around −0.396 V after Vend has been pulled down to ground. This value is acceptable as the simulated leakage current of the 0.396-V forward-biased p− substrate/n+ drain diode of M2 is only 216 pA at room temperature. The relatively large parasitic capacitance between the bottom plate of C1 and the grounded p− substrate is the key to keeping the M2 drain voltage from dropping deeper, while it also restricts the sensitivity of the proposed image sensor. In more recently developed global shutter CMOS image sensors, a photodiode substrate and an in-pixel storage node substrate is interconnected by microbumps to achieve excellent parasitic light sensitivity [14]. In an ultra-fast gated CMOS image sensor, this type of strategy is not the best choice as the parasitic capacitance of the microbump interconnections is too large. Instead, sufficient light shield, and some shield for the carriers, is applied to a single-chip CMOS image sensor to achieve a low enough level of parasitic light sensitivity. In the proposed CMOS image sensor, the entire area in the pixel array, with the exception of the photodiodes, is shielded by the top metal layer in order to achieve high shutter efficiency. Furthermore, for each pixel, a continuous contact ring is included in the design, which is in contact with the n+ active area within the photodiode n-well and surrounding the photodiode p+ active area, in order to achieve superior light shielding efficiency. The anode of the photodiode (the p+ area) is led out by metalized polysilicon through a small opening on the contact ring. There are also continuous via rings between the metal layers (1,2) and (2,3) surrounding the photodiode without any openings. Although using continuous contact rings or via rings in the circuit violates the topological design rule from the foundry, the proposed design works well. It is based on the 0.5-μm CMOS process without any changes to the default process parameters. The 0.5-μm CMOS process that is used to fabricate the proposed chip does not include any chemical mechanical planarization (CMP) processing.
The layout of a couple of pixels in the pixel array is shown in Figure 3a, and a cross-sectional diagram of the photodiode in the pixel is shown in Figure 3b. Transistors M1 and M2 of the pixels in the even and odd columns share the same active areas. Thus, the drain of transistor M2 is far away from the nearest contact opening, which helps provide sufficient light shielding to the drain of transistor M2. This approach also simplifies the layout of the vertical clock tree in the pixel array.
In order to minimize the drain capacitance, both gates of transistors M1 and M2 are configured in a square annular structure. This also provides some shield for the photoelectrons for the drain of M2 and increases the shutter efficiency. The authors also used several depletion NMOS capacitors with an approximate total value of 200 fF in each pixel for power-decoupling purposes. A timing chart for V start , V end , V reset , and the simulated results of the drain voltages of M1 and M2 is shown in Figure 2b. In the simulation, a 6.25-fF capacitor representing the parasitic capacitance was added between the bottom plate of C1 and the ground. Figure 2b shows that the M2 drain voltage drops to around´0.396 V after V end has been pulled down to ground. This value is acceptable as the simulated leakage current of the 0.396-V forward-biased p´substrate/n+ drain diode of M2 is only 216 pA at room temperature. The relatively large parasitic capacitance between the bottom plate of C1 and the grounded p´substrate is the key to keeping the M2 drain voltage from dropping deeper, while it also restricts the sensitivity of the proposed image sensor.
In more recently developed global shutter CMOS image sensors, a photodiode substrate and an in-pixel storage node substrate is interconnected by microbumps to achieve excellent parasitic light sensitivity [14]. In an ultra-fast gated CMOS image sensor, this type of strategy is not the best choice as the parasitic capacitance of the microbump interconnections is too large. Instead, sufficient light shield, and some shield for the carriers, is applied to a single-chip CMOS image sensor to achieve a low enough level of parasitic light sensitivity. In the proposed CMOS image sensor, the entire area in the pixel array, with the exception of the photodiodes, is shielded by the top metal layer in order to achieve high shutter efficiency. Furthermore, for each pixel, a continuous contact ring is included in the design, which is in contact with the n+ active area within the photodiode n-well and surrounding the photodiode p+ active area, in order to achieve superior light shielding efficiency. The anode of the photodiode (the p+ area) is led out by metalized polysilicon through a small opening on the contact ring. There are also continuous via rings between the metal layers (1,2) and (2,3) surrounding the photodiode without any openings. Although using continuous contact rings or via rings in the circuit violates the topological design rule from the foundry, the proposed design works well. It is based on the 0.5-µm CMOS process without any changes to the default process parameters. The 0.5-µm CMOS process that is used to fabricate the proposed chip does not include any chemical mechanical planarization (CMP) processing.
The layout of a couple of pixels in the pixel array is shown in Figure 3a, and a cross-sectional diagram of the photodiode in the pixel is shown in Figure 3b. Transistors M1 and M2 of the pixels in the even and odd columns share the same active areas. Thus, the drain of transistor M2 is far away from the nearest contact opening, which helps provide sufficient light shielding to the drain of transistor M2. This approach also simplifies the layout of the vertical clock tree in the pixel array.  Figure 4a shows a simplified circuit model of a pixel before exposure at the moment when transistors M1 and M2 are both on. Cd includes the capacitance from the photodiode D1 and the transistors M1 and M5. C1 represents the capacitance of the sampling capacitor C1 in Figure 2a. R1 and R2 represent the on-state resistance of the transistors M1 and M2, respectively. It can be assumed that the pulse current source Id emits a short enough current pulse with a total charge of Qp before exposure. The time interval between the current pulse and the start of exposure is t1, and Q1 is the charge on capacitor C1 after the shutter has remained in the "open" state, as shown in Figure 4b, for sufficient time. For simplicity, let C = Cd = C1, and then Q1 can be expressed as

Limitations of Shortest Shutter Time
Q1 will decline as t1 increases. In the proposed design, R1 = R2 = 1413 Ω, and we assume C = 21 fF. Let thalf1 be the value of t1 when Q1 has decreased to half of its maximum value. For the values given above, thalf1 = 31.5 ps. Figure 4b shows the simplified circuit model of a pixel during exposure, when transistor M1 is off and M2 is still on. It can be assumed that the current source Id emits a short enough current pulse with a total charge Qp during the shutter "open" state. If t2 denotes the time interval after the current pulse and Q2 denotes the charge on capacitor C1 at time t2, Q2 can be expressed as Q2 will increase after the current pulse and eventually reaches a maximum value. Let thalf2 be the time after the current pulse when Q2 reaches half of its maximum value; thalf2 can then be expressed as In the proposed design, C1 = 21 fF, R2 = 1413 Ω, and the simulated value of Cd is 27 fF with a 5-V power supply, giving thalf2 = 11.7 ps. The shortest shutter time of the proposed design should therefore be longer than thalf1 + thalf2, i.e., 43.2 ps. In order to minimize the drain capacitance, both gates of transistors M1 and M2 are configured in a square annular structure. This also provides some shield for the photoelectrons for the drain of M2 and increases the shutter efficiency. The authors also used several depletion NMOS capacitors with an approximate total value of 200 fF in each pixel for power-decoupling purposes. Figure 4a shows a simplified circuit model of a pixel before exposure at the moment when transistors M1 and M2 are both on. C d includes the capacitance from the photodiode D1 and the transistors M1 and M5. C 1 represents the capacitance of the sampling capacitor C 1 in Figure 2a. R 1 and R 2 represent the on-state resistance of the transistors M1 and M2, respectively. It can be assumed that the pulse current source I d emits a short enough current pulse with a total charge of Q p before exposure. The time interval between the current pulse and the start of exposure is t 1 , and Q 1 is the charge on capacitor C 1 after the shutter has remained in the "open" state, as shown in Figure 4b, for sufficient time. For simplicity, let C = C d = C 1 , and then Q 1 can be expressed as

Limitations of Shortest Shutter Time
Sensors 2016, 16, 999 5 of 10  Figure 5a shows a micrograph for the designed image sensor, and Figure 5b illustrates the circuit architecture of the sensor. The exposure control signals Vstart and Vend can be configured to be directly controlled by an external digital input, or alternatively the exposure process can be triggered using an external digital signal. When the exposure process is triggered by an external signal, the time between the falling edge of Vstart and Vend signal (roughly the exposure time) is controlled by a voltagecontrolled delayer, which is located in the exposure clock control circuits at the bottom of the chip. Q 1 will decline as t 1 increases. In the proposed design, R 1 = R 2 = 1413 Ω, and we assume C = 21 fF. Let t half1 be the value of t 1 when Q 1 has decreased to half of its maximum value. For the values given above, t half1 = 31.5 ps. Figure 4b shows the simplified circuit model of a pixel during exposure, when transistor M1 is off and M2 is still on. It can be assumed that the current source I d emits a short enough current pulse with Sensors 2016, 16, 999 5 of 10 a total charge Q p during the shutter "open" state. If t 2 denotes the time interval after the current pulse and Q 2 denotes the charge on capacitor C 1 at time t 2 , Q 2 can be expressed as

Sensor Chip Architecture
Q 2 will increase after the current pulse and eventually reaches a maximum value. Let t half2 be the time after the current pulse when Q 2 reaches half of its maximum value; t half2 can then be expressed as In the proposed design, C 1 = 21 fF, R 2 = 1413 Ω, and the simulated value of C d is 27 fF with a 5-V power supply, giving t half2 = 11.7 ps. The shortest shutter time of the proposed design should therefore be longer than t half1 + t half2 , i.e., 43.2 ps. Figure 5a shows a micrograph for the designed image sensor, and Figure 5b illustrates the circuit architecture of the sensor. The exposure control signals V start and V end can be configured to be directly controlled by an external digital input, or alternatively the exposure process can be triggered using an external digital signal. When the exposure process is triggered by an external signal, the time between the falling edge of V start and V end signal (roughly the exposure time) is controlled by a voltage-controlled delayer, which is located in the exposure clock control circuits at the bottom of the chip.   Figure 5a shows a micrograph for the designed image sensor, and Figure 5b illustrates the circuit architecture of the sensor. The exposure control signals Vstart and Vend can be configured to be directly controlled by an external digital input, or alternatively the exposure process can be triggered using an external digital signal. When the exposure process is triggered by an external signal, the time between the falling edge of Vstart and Vend signal (roughly the exposure time) is controlled by a voltagecontrolled delayer, which is located in the exposure clock control circuits at the bottom of the chip. The exposure control signals Vstart and Vend are firstly distributed across the horizontal components [4,5], then across the vertical components of the clock trees, and finally to the pixels. The vertical components of the clock trees are placed in the pixel array by pruning one row of pixels after every eight rows, as shown in Figure 5b. The three even and the four odd vertical components of the clock trees belong to the Vstart and the Vend signals, respectively. A simplified schematic of the single vertical components of the clock trees is shown in the right part of Figure 5b. These clock trees consist of fast falling-edge digital buffers [12] and distributed power decoupling capacitors. This type of design of clock trees can be easily extended to large-format gated CMOS image sensors.

Sensor Chip Architecture
Since balanced clock trees with fast falling-edge digital buffers are used in the exposure control signal distribution in both the horizontal and vertical directions, and the output of the final nodes of all vertical components of the Vstart clock tree are connected together as shown in the right part of Figure 5b, as are the horizontal components and the Vend clock tree, the exposure signal skew should be relatively small compared with the shortest shutter time of the small designed image sensor.
The image signal from the pixels is first multiplexed by an analog multiplexer to a voltage shifter, The exposure control signals V start and V end are firstly distributed across the horizontal components [4,5], then across the vertical components of the clock trees, and finally to the pixels. The vertical components of the clock trees are placed in the pixel array by pruning one row of pixels after every eight rows, as shown in Figure 5b. The three even and the four odd vertical components of the clock trees belong to the V start and the V end signals, respectively. A simplified schematic of the single vertical components of the clock trees is shown in the right part of Figure 5b. These clock trees consist of fast falling-edge digital buffers [12] and distributed power decoupling capacitors. This type of design of clock trees can be easily extended to large-format gated CMOS image sensors.
Since balanced clock trees with fast falling-edge digital buffers are used in the exposure control signal distribution in both the horizontal and vertical directions, and the output of the final nodes of all vertical components of the V start clock tree are connected together as shown in the right part of Figure 5b, as are the horizontal components and the V end clock tree, the exposure signal skew should be relatively small compared with the shortest shutter time of the small designed image sensor.
The image signal from the pixels is first multiplexed by an analog multiplexer to a voltage shifter, and it is then buffered by an on-chip analog buffer and eventually drives an off-chip analog-to-digital (A/D) converter.

Test Methods and Results
A test board connected to a PCI digital data acquisition board was used to test the designed chip. A 12-bit A/D converter chip operating at a 5-V input range was used on the test board. The highest speed achievable by the digital data acquisition board when operating bi-directionally is 10 M samples per second. This speed limits the A/D converter clock frequency and the sampling rate to a maximum of 5 M samples per second. Figure 6 shows the measured photo response curve and the photo response non-uniformity (PRNU) between pixels of the proposed image sensor. The photo response curve and the PRNU were obtained by varying the exposure time, while keeping a constant uniform illumination by a blue LED. The measured PRNU for the selected area at half of the saturated voltage for all columns, odd columns only and even columns only was 1.39%, 1.42%, and 1.28%, respectively. This is normal and the difference in the pixel layouts for the odd and even columns show no significant influence on the PRNU.

Test Methods and Results
A test board connected to a PCI digital data acquisition board was used to test the designed chip. A 12-bit A/D converter chip operating at a 5-V input range was used on the test board. The highest speed achievable by the digital data acquisition board when operating bi-directionally is 10 M samples per second. This speed limits the A/D converter clock frequency and the sampling rate to a maximum of 5 M samples per second. Figure 6 shows the measured photo response curve and the photo response non-uniformity (PRNU) between pixels of the proposed image sensor. The photo response curve and the PRNU were obtained by varying the exposure time, while keeping a constant uniform illumination by a blue LED. The measured PRNU for the selected area at half of the saturated voltage for all columns, odd columns only and even columns only was 1.39%, 1.42%, and 1.28%, respectively. This is normal and the difference in the pixel layouts for the odd and even columns show no significant influence on the PRNU. To measure small signal responsivity or the charge-to-voltage gain of the designed image sensor, the central area of the pixel array was illuminated by a defocused 405-nm wavelength continuouswave (CW) diode laser spot, as shown in Figure 7a. The difference between the measured total supply current of the chip when the 405-nm laser was on and off was the measured total photocurrent. During such measurements, the pixel array was in a state of waiting for the trigger signal, and Vselect of all pixels was set to ground, so that the output analog buffer remained in the same state. The measured small signal responsivity of the designed chip was 1.47 μV/e − . The linear range of the output signal was from 2.5 V to about 0.7 V, so the full capacity of the pixel was around 1,200,000 e − . The measured random readout noise of the output signal was 475 μV rms. The quantization noise of a 12-bit readout with a 5-V full range is 352 μV rms. Thus, the random readout noise of the designed chip was 319 μV rms, which is equivalent to 217 photoelectrons generated by the photodiode. Therefore, the dynamic range of the designed chip was about 5500:1. To measure small signal responsivity or the charge-to-voltage gain of the designed image sensor, the central area of the pixel array was illuminated by a defocused 405-nm wavelength continuous-wave (CW) diode laser spot, as shown in Figure 7a. The difference between the measured total supply current of the chip when the 405-nm laser was on and off was the measured total photocurrent. During such measurements, the pixel array was in a state of waiting for the trigger signal, and V select of all pixels was set to ground, so that the output analog buffer remained in the same state. The measured small signal responsivity of the designed chip was 1.47 µV/e´. The linear range of the output signal was from 2.5 V to about 0.7 V, so the full capacity of the pixel was around 1,200,000 e´. The measured random readout noise of the output signal was 475 µV rms. The quantization noise of a 12-bit readout with a 5-V full range is 352 µV rms. Thus, the random readout noise of the designed chip was 319 µV rms, which is equivalent to 217 photoelectrons generated by the photodiode. Therefore, the dynamic range of the designed chip was about 5500:1. measured small signal responsivity of the designed chip was 1.47 μV/e − . The linear range of the output signal was from 2.5 V to about 0.7 V, so the full capacity of the pixel was around 1,200,000 e − . The measured random readout noise of the output signal was 475 μV rms. The quantization noise of a 12-bit readout with a 5-V full range is 352 μV rms. Thus, the random readout noise of the designed chip was 319 μV rms, which is equivalent to 217 photoelectrons generated by the photodiode. Therefore, the dynamic range of the designed chip was about 5500:1. The measured parasitic light sensitivity of the in-pixel storage node was very low when illuminated by a continuous-wave diode laser with a peak wavelength of 405 nm. The parasitic light sensitivity was measured by comparing the following two images. For the first image, the shutter The measured parasitic light sensitivity of the in-pixel storage node was very low when illuminated by a continuous-wave diode laser with a peak wavelength of 405 nm. The parasitic light sensitivity was measured by comparing the following two images. For the first image, the shutter time was set to approximately 300 ps. The exposure to the 405-nm diode laser lasted 0.5 s after the shutter was closed, and the captured image was then read out. The second image was taken by setting the shutter time to 100 ns and read out immediately after the shutter was closed. The dark image taken with the laser off was subtracted from both images to eliminate the output signal bias and fixed pattern noise. The resulting two images were then used to calculate the parasitic light sensitivity. The final measured parasitic light sensitivity when illuminated by a 405-nm diode laser was 1/8.5ˆ10 7 .
The parasitic light sensitivity when illuminated by a 650-nm continuous-wave diode laser was measured using a similar method, and the measured value was 1/1.4ˆ10 4 .
The measured leakage signal in a dark environment after the global shutter was closed was 0.7 V/s. According to the simulation, this leakage signal value is equivalent to a leakage current of approximately 22 fA on the storage node in the pixel.
The shortest shutter time (fastest shutter speed, best temporal resolution) of the designed chip was measured using a frequency-doubled 400-nm wavelength Ti:sapphire laser system with a 130-fs pulse width. The 400-nm laser flash was used to uniformly illuminate a fiber cable. The cable was composed of 30 silica fibers of different lengths [11]. The difference in length between adjacent fibers in the fiber cable was 2.0 mm. The output port of the fibers was imaged on the image sensor using the lens. During the shutter time measurement, the image sensor was triggered by a biased p-i-n photodiode outside the chip. Figure 7b shows the image that was obtained at a 1-V exposure time control voltage, which corresponds to a shutter time of 17 ns, whereas Figure 7c was obtained at a 4-V exposal time control voltage, which corresponds to a 30 ps simulated shutter control signal delay. The two images were used to obtain a normalized exposure curve, as shown in Figure 8. The measured shortest shutter time of this camera was less than 75 ps. pulse width. The 400-nm laser flash was used to uniformly illuminate a fiber cable. The cable was composed of 30 silica fibers of different lengths [11]. The difference in length between adjacent fibers in the fiber cable was 2.0 mm. The output port of the fibers was imaged on the image sensor using the lens. During the shutter time measurement, the image sensor was triggered by a biased p-i-n photodiode outside the chip. Figure 7b shows the image that was obtained at a 1-V exposure time control voltage, which corresponds to a shutter time of 17 ns, whereas Figure 7c was obtained at a 4-V exposal time control voltage, which corresponds to a 30 ps simulated shutter control signal delay. The two images were used to obtain a normalized exposure curve, as shown in Figure 8. The measured shortest shutter time of this camera was less than 75 ps. The characteristics and measurement results of the designed image sensor and a comparison with prior works are summarized in Table 1.

Discussion
A measured leakage signal of 0.7 V/s in a dark environment is too large compared to the readout The characteristics and measurement results of the designed image sensor and a comparison with prior works are summarized in Table 1.

Discussion
A measured leakage signal of 0.7 V/s in a dark environment is too large compared to the readout time of a large-format imager when there are 5-M samples being read out per second. Therefore, either the readout speed needs to be increased, or the leakage current needs to be lowered for an imager with much more pixels. Methods such as cooling or improving the pixel circuit design can be used to lower the leakage current.
The measured minimum shutter time of 75 ps is much larger than the calculated value of 43.2 ps, and the exposure curve shown in Figure 8 seems to be symmetric. This is as expected, since the shutter time is limited mainly by the fall time of the exposure control signals V start and V end driving the gates of M1 and M2, and not by the intrinsic minimum shutter time of the pixel circuit.
The parasitic light sensitivity that is measured when a 650-nm diode laser is used for illumination is much higher than that obtained using a 405-nm diode laser. This is due to the fact that the absorption depths of light at 405 nm and 650 nm in intrinsic silicon is approximately 0.12 µm and 3.56 µm, respectively [16]. Therefore, much more photoelectrons are generated in the p´substrate under the photodiode when it is illuminated by the 650-nm light, and some of these photoelectrons drift to the n+ drain of the transistor M2, although the p-well of transistor M2 provides some shield to the photoelectrons generated in the p´substrate [17]. Therefore, placing the p-well of transistor M2 in a deep n-well isolated area may provide considerable improvement to the shutter efficiency.
Since the exposure signal skew is relatively small compared with the shortest shutter time in the small designed image sensor, and there is a lack of pixels with skew test circuits [12] in the pixel array, it is hard to measure the exact exposure signal skew. Precise measurement may be possible in the future using an ultra-fast gated CMOS image sensor based on a similar design, but with a much larger imaging area.

Conclusions
For this paper, a 40ˆ48-pixel ultra-fast global shutter CMOS image sensor was designed and manufactured using a 0.5-µm mixed-signal CMOS process. The measured parasitic light sensitivity for a 405-nm diode laser was 1/8.5ˆ10 7 , which is comparable to MCP-based gated cameras and is low enough for most applications. The measured shutter time can be as short as 75 ps, and the measured dynamic range of the pixel of the designed chip was 5500:1, which is no worse than MCP-based picosecond framing cameras that are currently used [18]. The authors are confident that further significant improvements can be made to the proposed design's temporal resolution through the combined use of more advanced CMOS processes such as advanced silicon-on-insulator (SOI) CMOS technologies and by overdriving the gates of M1 and M2 immediately before and during the exposure process.