Improved Circuits with Capacitive Feedback for Readout Resistive Sensor Arrays

One of the most suitable ways of distributing a resistive sensor array for reading is an array with M rows and N columns. This allows reduced wiring and a certain degree of parallelism in the implementation, although it also introduces crosstalk effects. Several types of circuits can carry out the analogue-digital conversion of this type of sensors. This article focuses on the use of operational amplifiers with capacitive feedback and FPGAs for this task. Specifically, modifications of a previously reported circuit are proposed to reduce the errors due to the non-idealities of the amplifiers and the I/O drivers of the FPGA. Moreover, calibration algorithms are derived from the analysis of the proposed circuitry to reduce the crosstalk error and improve the accuracy. Finally, the performances of the proposals is evaluated experimentally on an array of resistors and for different ranges.


Introduction
There is a large range of applications which use resistive sensor arrays to obtain information about a specific system, such as temperature sensing [1,2], gas detection [3,4], tactile sensing [5][6][7][8] and others. The complexity of the electronic system necessary to read the information of the array depends on the number of sensors, the number of connections necessary to extract the information, the resistance values of each sensor, and the speed necessary to obtain this information. Moreover, the system is even more complex when subsequent processing, such as in the case of a smart sensor, is required for sending data to a central unit and it is to be done in the circuit which scans the information of the array.
The processing speed of the array signals involves a trade-off with the complexity of the system: if maximum processing speed is required, parallel access to the information of all the individual sensors must be done individually, meaning a high number of wires to carry this information and a large number of processing units in the circuits to receive it.
Indeed, for circuits with maximum parallelism, if the sensors are distributed in a 2 dimensional array with lengths M for rows and N for columns, the number of wires may reach 2ˆMˆN. However, one of the sensor terminals is generally shared, meaning the final number may be reduced to MˆN + 1 [9]. Each of these wires should be connected to a circuit to scan the information of a specific sensor in which the resistance value is translated into a voltage value and subsequently a digital number, meaning MˆN of these circuits would be required. The time to scan the array would approximately coincide with the time to scan an array element.

Readout Circuit with Capacitive Feedback
A circuit with a direct resistive sensor-FPGA interface, without A/D converters, is presented in [13]. This circuit uses operational amplifiers (OAs) with capacitive feedback to implement grounding and reduce crosstalk on the element being tested (hereinafter EBT). This solution is shown in Figure 1.  [13] for reading of a resistive array.
The resistance value R ij of an EBT is read by measuring a discharge time through C j . Initially, the charged capacitor maintains voltage in the OA output node, which is interpreted as a 1-logic in a digital processor input pin. As the capacitor discharges, a voltage is reached which makes the input pin interpret the input as a 0-logic level. The measurement will therefore be the time difference between the capacitor charge finishing and receipt of a 0 through the digital processor input pin. [13] sets out a series of arguments in which the choice of an FPGA is suitable as a processing unit. These include, most notably, that each of the inputs can be processed in parallel by the FPGA programmable hardware.
The way the circuit works is described in more detail below. As illustrated in Figure 1, the sensor row lines are the M pin outputs, configured as output of an FPGA. In order to know the resistance of the sensor with value R ij , the pin of row i, PFi, is placed at a high level (a value close to V DD in the FPGA output), and the other row pins at 0-logic value (a value close to 0 V at the FPGA output). This means current will only circulate through the resistors of this row (a single resistor in each column).
In order to duly use this current in a first cycle (CHARGE cycle), all the C j capacitors are charged with V DD voltage in the OA output terminal, maintaining 0 V in the inverter terminal. This is done via two FPGA output buffers (Zero and PV oj in Figure 2). It should be noted that the pins which will be in charge of reading PV oj voltage are configured as output in this phase. The OA will also be disabled (placing the shutdown pin at 0 V) and the FPGA outputs which control the row signals, PF k , will all be 0 V. A new cycle, ACTIVATE, is then entered, activating the OA and placing shutdown at high level.The pin PV oj is configured in high impedance at the same time. Finally, the DISCHARGE cycle is carried out, discharging the capacitors. To do this, the Zero pin is configured in high impedance and the output buffer of the row to be scanned, PFi, is placed at V DD , with all other row buffers remaining at 0 V. At the same time, the OA output voltage reading pins, PV oj , are configured as input. This means the output voltage of all OAs will decrease as the current which crosses the different R ij discharges the capacitors.
Operating in this manner, all PV oj pins will have an input of value V DD volts at the start of the DISCHARGE cycle, which will decrease as time passes through to a value VT j , the threshold voltage for which the PV oj pin input buffers start to interpret the input as a 0-logic which is transmitted to inside the FPGA. The time in which V oj passes from V DD to VT j in the DISCHARGE cycle will be known as ∆t ij . Considering the OA ideal and the resistance value of the sensor constant, a simple analysis would indicate that: in which there is a linear relationship between time measured ∆t ij and resistance value R ij . The main advantages of the circuit proposed in [13] are the elimination of the AD converter and the possibility of parallel processing in the FPGA of the information from the series of sensors which are scanned simultaneously. This configuration therefore allows greater processing speed and a reduced area and consumption.
An additional row, calibration row, is added in [13], in order to not have to evaluate C j and VT j in Equation (1), since these magnitudes are difficult to measure due to their value varying with the supply voltage, time and temperature. This procedure is equivalent to what is known in literature as single-point calibration [15]. However, this type of calibration does not take into account the resistances of the buffers of each row, k, of the FPGA, RB k , which results in an error in estimating R ij . If the RB k values were constant and equal for all buffers, the value could be calculated with a Two-Points calibration [15], which would involve adding a second calibration row to that proposed in [13]. Moreover, RB k although it is constant in a DISCHARGE cycle, it is not equal in all buffers, since it depends on the array resistors it is connected to, meaning even adding a second calibration row would not avoid the errors due to this resistor. It is important to note that we have to evaluate its value and also avoid the effect of crosstalk which comes about from being joined to several array resistors, one resistor per column, a question which a two-point calibration does not resolve. Furthermore, it should be remembered that the OAs used are not ideal and, in consequence, present second-order effects, which also results in crosstalk, as will be shown in more detail below. Finally, [13] does not include any analysis of the possible ranges of resistance values which the circuit may measure correctly.

Improving Circuits with Capacitive Feedback for Readout Resistive Sensor Arrays
Each paragraph in this section analyses and proposes solutions for each of the problems set out above.

Estimation of R ij Considering the Effect of the Resistance of the Row Selection Buffers and Variations in the Values C j and VT j
In order to reduce the effects of variation in measurements C j and VT j and to simultaneously eliminate the effect of the resistance of the row selection buffers, using the circuit in Figure 3 is proposed. The so-called calibration row and column have been added to it (in red). The circuit therefore has M + 1 rows and N + 1 columns. In consequence, N + M + 1 additional resistors with known values need to be used, along with an extra OA in the calibration column.
The operation of the circuit is exactly the same as indicated in the paragraph above, taking into account that there is now one more row to read (for simplicity, the part marked in blue in Figure 2 is not shown). Figure 4 shows the equivalent circuit to scan the resistors of row i. Here the row control buffer has been replaced with the corresponding output resistor RB k . In these buffers the resistors for high status output, RB p k , are different to those shown in a low status output, RB n k , although both can be small (10-50 Ω), due to the CMOS technology used in manufacture.  Supposing that the OA are ideal, the value for ∆t ij would be given in the Equation (1), although this does not take into account the different RB k . To illustrate the influence of these resistors, the current, Ic i j , which enters through resistor R ij and discharges capacitor C j when row i is activated, is calculated. If RP i " R i1 ||R i2 || ... ||R iN ||R ic is the parallel of all resistors being scanned, including the calibration resistor, a simple analysis of the circuit of Figure 4 shows: meaning the time to discharge C j at VT j is given by: It is worthwhile noting that the Equation (3) shows the appearance of crosstalk in the circuit, since ∆t ij is no longer a function of a single resistor of the array, R ij , but rather of all resistors of the same row (through RP i ). Hence, ∆t ij should be calculated by way of a non-linear system of N + 1 equations in which it is necessary to know the exact values of C j , VT j , RB p i and the discharge times for all the columns when row i is activated. It is also necessary to take into account that RB p i is not constant and varies throughout the discharge process. The details below indicate how to proceed in order to avoid these inconveniences in the R ij calculation using different array measurement times.
Once the scanning process for all resistors has been completed, these times are stored in the FPGA. Hence, ∆t ic can be used to calculate the ∆t ij /∆t ic coefficient and express R ij based on the Equation (3) as follows: In this expression only the part between parentheses is unknown; however, as there is also ∆t cj and ∆t cc its value can be found by proceeding in the same way as when finding the expression (4): replacing Equation (5) in Equation (4): In the term on the right of Equation (6), once the sensor array has been scanned, all the terms are known and, in consequence, it is not necessary to modify the scanning process indicated in Section 2 in order to obtain the values of the different R ij resistors. The operations necessary to find R ij can be carried out in the FPGA and their results transmitted or processed whilst extracting data from a new sensor array frame.
The Equation (6) can also be used in line with the digital number of cycles (D) which the FPGA uses to measure the different times of this equation. Hence, if ∆t = DˆT s , where T s is the meter clock period, Equation (6) the result is: It should be noted that in Equation (2), in order to deduce R ij , a series of resistors RB k have been used which model the operation of each buffer; however, if R ij is evaluated by way of Equation (6), these effects do not have any influence since RB k does not appear in the expression.

Limitations in the Range of Resistors to Be Measured
In order to use the Equation (6) correctly, it is necessary to determine the range of resistors which can be measured with the circuit of Figure 3. Two main circumstances limit this range. Firstly, the maximum current which the FPGA can provide will depend on each specific model and must be carefully examined in the design stage. For the correct operation of the circuit, it does not matter that the buffer output provides a voltage below V DD in a specific amount, since the limitation actually comes from the maximum current which can be provided by a specific buffer or series of buffers which select the rows of the array without affecting the correct operation of the FPGA.
Secondly, it should be noted that the current provided by each buffer will depend inversely on RP i , and, in consequence, will increase with the number of array columns or with the reduction of the resistance values. This limits the size of the array to be scanned and the possible array resistor ranges. In order to prevent this restriction, the resistor of each row to be scanned can be increased by adding an RS i series resistor at the output of each buffer, which will be added to RB k , thus reducing the current provided by the buffer. Although this resistor is added, the Equation (6) can continue to be used to calculate R ij .
However, there is another limitation related to the range of resistors to be measured, since each resistor of the sensors of a row takes different times to discharge the capacitor of its column. Hence, whilst row i has the lowest possible value resistor, RL (in column l), and another with the highest possible value, RH (in column h), it may occur that the former completely discharges its capacitor to 0 V whilst the latter has not yet achieved output voltage below VT h . In this situation, the capacitor of column l continues to receive current from the sensor resistor, but, as V ol has reached its minimum value, the OA enters non-linear operation mode (even when it is a rail-to-rail OA), meaning the voltage in the OA inverter input node starts to increase, and ceases to be a virtual ground. If this occurs, the crosstalk phenomenon will appear through the resistors of the non-selected rows (as shown in Section 3.4), affecting the resistor time measurement RH which is as yet incomplete.
I RH and I RL are the currents which cross the RH and RL resistors respectively. The relation which must be met in order to prevent the aforementioned situation from coming about is set out below.
The output voltage of a column in DISCHARGE phase is given by: Hence, the time necessary for RL to discharge the capacitor of its column to 0 V will be: In order for crosstalk effect to be prevented, in this time the output voltage of column h must have dropped below the threshold value VT (for the purpose of simplicity, it is considered that the threshold voltages of all rows are equal). Hence, in accordance with Equation (8): replacing Equation (9) in Equation (10) and supposing, for the purpose of simplicity, the capacitors of all the columns are equal, we obtain: The Equation (2) can be used to find the values for I RL and I RH , and replacing them in Equation (11) we obtain: Hence, Equation (12) shows the limitations in the possible sensor resistance values in order for the circuit to work correctly. In the implementation carried out in Section 4, using a Spartan 3 XCS50AN-4TQG144C, with V DD = 3.3 V results in VT = 1.4 V, meaning RH < 1.74ˆRL.
As will also be shown in Section 4, for RL values over, approximately, 3 kΩ, the effects of failing to meet Equation (12) are very small. Moreover, it is possible to prevent increased voltage of the OA inverter node by activating the Zero pin of the FPGA at the moment the output node reaches voltage VT. However, for lower RL values of the array, crosstalk effect is increasingly important and Equation (12) is a serious limitation in the circuit.

Increasing the Range of Resistors
In order to increase the range of resistors to be measured, it is not necessary to modify the design of the Figure 3 but only to carry out the reading of two simultaneous rows: the sensors array, i, and the calibration resistors row, c.
Doing this, there are two resistors through which the capacitor of each column is discharged. If the maximum and minimum resistors of the array, RH and RL, are found again in the row to be scanned, in columns h and l simultaneously, the calibration resistors of the same columns are scanned: R C (all with the same value), so the Equation (11) is now transformed into: Replacing the values of the currents obtained using Equation (2) in this expression, the following can be written: (14) in which the threshold voltages and the capacitors of all the rows have again be taken as equal.
Regrouping all the terms with RH in the left member of Equation (14), the following can be written: A simpler expression can be achieved with the approximation RB p ăă RP (the resistors of the row selection buffers have very low values), meaning Equation (15) obtains an upper limit for RH as:

16)
Comparing the Equations (12) and (16) shows how the range has been extended. The restrictions on RH can also be eliminated by making the denominator of Equation (16) equal to 0. This means that R C should be: In the previous design example R C = 0.74ˆRL. However, if the restriction RB p ăă RP is not met, either because the number of columns is large, the RL values are small, or a series resistor has been introduced with the buffer, then RH will continue to be limited by Equation (15); however, if in this expression the term between square brackets is below or equal to 0, any RH value would be possible. Modifying Equation (15), this condition can be written as: In order to meet the restriction, the R C and RB p i values can be modified (including a series resistor with the buffer, RS i ). Hence, a higher limit can be found for the R C value and a lower limit for RB p i`R S i . These limits will be more restrictive when RP i is maximum, RP imax found in accordance with the following expression: Taking into account all the foregoing, R C can be cleared in Equation (18) obtaining: It is clear that the member of the right of Equation (20) must be greater than 0, but this can always be achieved thanks to RS i , even when the number of columns N is large. However, in order to obtain Equation (20), two rows of the array are selected simultaneously, and, in consequence, the expression Equation (6) is no longer valid since it is not a single current which discharges the capacitor but rather the sum of two: the current which circulates through resistor R ij and the one which circulates through resistor R cj .
In order to find an expression equivalent to Equation (6) and to determine the value of R ij , 4 discharge times are used: ∆t 1 ij , ∆t 1 ic , ∆t cj and ∆t cc . The first two are the discharge times of the columns j and c when rows i and calibration row c are selected simultaneously. ∆t cj and ∆t cc are the discharge times of columns j and c when only the calibration row is selected. The expression Equation (3) can be used to calculate ∆t cj and ∆t cc , whilst to calculate ∆t 1 ij , ∆t 1 ic only two currents discharge the capacitor and in consequence: Taking into account these expressions and using those obtained in Equation (2) for the currents, R ij can be expressed as: Hence, modifying the array scanning procedure and selecting the appropriate values of R C means very wide ranges of resistors can be measured, and, knowing four discharge times, the value of R ij determined. It should be highlighted that the time spent scanning the whole array in order to obtain the data of Equation (6) is the same as the time taken to obtain the data of Equation (22), and that the number of time measurements to be saved in the internal memory of the FPGA is the same. Moreover, the calculations to obtain R ij by Equation (22) can be carried out in the FPGA whilst data are obtained for a new array frame.

Crosstalk Due to the Offset Voltages of the Operational Amplifiers
The OAs present offset voltages, θ, which, depending on the models used, can vary in the range between millivolts and microvolts. As the offset voltages are random values determined by variations in the transistor manufacture processes, each OA (even when it is the same model) can have a different value. Moreover, as the OA non-inverter input voltage is set to ground in the circuit, the offset voltage appears in the OA inverter terminal. For this reason, the inverter input voltages of all OAs can vary, resulting in the appearance of crosstalk.
The circuit used to analyse crosstalk due to the offset of the OAs is indicated in Figure 5, which shows the different offset voltages of the OAs, θ j ; j P t1, 2, ...N, cu and the situation in which a single row of sensors, row i, is scanned is illustrated. All FPGA row control buffers have been replaced with their corresponding resistors, RB p i , for the case of rows selected at V DD or RB n i for rows at 0 V. The value to be found is the current Ic i j which enters capacitor C j . This current has several components. Figure 6 can be used for analysis, showing in detail the components of Ic i j .
Observing Figure 6a, all the currents which flow through the resistors of row i can be set out in accordance with I ij since: Hence, using this equation, we can write: where θ jk = θ j´θk and k = N + 1 is the calibration column. Taking into account that V DD can be expressed: I ij can be cleared using Equation (25): Secondly there are all the currents which, through the rest of the resistors of column j, are drained to ground, Figure 6b. As shown in this figure, I n gj is the current which flows through the resistor, R gj , with g " i. Using the same analysis as for the calculation of I ij in Figure 6a (replacing V DD with 0 V, RB p i with RB n i and taking the appropriate indices) we arrive at: As current is drained to ground through all the resistors of column j with the exception of R ij , this can be calculated as: where g = M + 1 is the calibration row. Replacing Equation (27) and Equation (28) where, separating θ jk = θ j´θk , we can write: an expression which characterises the crosstalk of the circuit when the inverter input of the OAs does not have a virtual ground voltage. It should be noted that this expression can be written in abbreviated form: where F(i) is a function which depends on index i but not on j: and G(j) is a function which depends on index j but not on i: Gpjq "´θ j M`1 ÿ g"1 1 R gj`M`1 ÿ g"1 RB n g¨R P g RB n g`R P g¨1 R gj Moreover, using Equation (28) it is easy to check that: a result which will be used in the following section.
In this manner, dependence on Ic i j is separated in: one term for rows and another for columns and the value of R ij . This will allow us to, as will be seen in the following section, design a strategy to find the value of R ij taking into account the effects of the offset voltages of the OA. It can also be seen how from the Equation (31), with all offset voltages at 0, we can derive the Equation (2).
Returning to the Equation (31), the operation of the crosstalk in the array can be analysed. Hence, if the resistors of buffers RB n and RB p are very small, or small compared to RP, Equation (31) this is simplified: where the crosstalk effect due to resistors of other columns has disappeared. Hence, Ic i j is only modified, with regard to the Equation (2), by the resistors of the same column, j, and by θ j . This may not be the case if an extension were necessary in the range of resistor values, since RS i may have to be added to RB p i if the Equation (20) so requires. However, this provides a design guide, since RS i must be as small as possible in order to reduce the crosstalk.
Equation (31) also shows how an increase in the minimum values of the R ij resistors of the array brings a larger decrease in terms 2 and 4 of the right side of the equation with regards to the first (since these have a quadratic dependence with the array resistors) meaning, if the resistors are not large enough, these terms could be eliminated and Equation (31) would be again reduced to Equation (36).
Moreover, an increase in the number of rows or columns due to the summations which appear in Equation (31) means an increase in crosstalk through terms 2, 3 and 4 of the right member of this equation. In consequence, even with high minimum array resistor values, if this has a large number of rows and columns, the crosstalk effect may be the factor which most influences the current which crosses a resistor, even more than the value of the resistor itself.

R ij Calculation Taking into Account the Offset Voltages of the Operational Amplifiers
This section sets out a simple method to obtain the R ij , values taking into account all the second-order effects presented so far. To apply this method, it is necessary to modify the circuit of Figure 3, adding a second calibration row (these rows will be called c1 and c2), as shown in Figure 7.
Again the method is based on modifying the row reading procedure and the use of different discharge times in order to, firstly, eliminate the term G(j) from the Equation (32) and, secondly, use simple coefficients to find the resistor values, eliminating F(i). The process requires the following steps:

‚
Step-1: A row, i, of the array and row c1 are activated simultaneously. The process is repeated for each of the array rows. A series of M times ∆t 1 ij , the times taken to discharge the different capacitors of the columns when rows i and c1 are activated simultaneously, are therefore obtained.
It should be noted that Steps 2 and 3 are only carried out once during the scanning of all the array rows, and that the three steps can be carried out in any order. The process to obtain R ij based on the previous steps is shown below. Following the same procedure as used to find Equation (29), in Step-1 we would have: where Ic i,c1 j indicates the current which discharges capacitor C j simultaneously activating rows i and c1. Subtracting the current, Ic i j , found during Step-2: we obtain:

43)
The members of the right of Equations (40) and (42) are now divided by the members of the right of Equations (41) and (43), proceeding in the same way for the members of the left. Operating with these ratios finally: As resistances R ic , R c2j and R c2c and the times are known, the value of R ij can be calculated again without taking into account the value of the capacitors, VT or buffer resistors, RB. It should also be noted that the fact that rows i and c1 can be activated simultaneously allows the extension of the array resistor ranges as seen in Section 3.3.
It should be noted that, although the offset voltage has been compensated using the Equation (44), it would be necessary to add to the terms θ j a term V oj /A due to the finite gain of the OA. However, as will be seen in Section 4, this term takes a much lower value than offset voltage, for which reason it is not taken into account.

Elimination of Effects of the Polarization Currents of the Operational Amplifiers
The Equation (44) also take into account the effects of the polarization current which would enter the OA through the inverter terminal, Ib j . In effect, if Ib j is taken into account, Equations (37) and (38) must be modified: As it appears in the same way in both, it disappears when obtaining the subtraction Ic i,c1 j´I c c1 j , as is also the case with the three current subtractions carried out to obtain Equation (44), meaning this equation continues to be valid, even considering the polarization currents.

Materials and Methods
The circuits proposed have been carried out on an FPGA Spartan3AN by Xilinx (XC3S50AN-4TQG144C) [16] with a working frequency of 50 MHz. The meter used by the capture modules is 14 bits, with a base time of 20 ns. The supply voltages are 1.2 V for the core and 3.3 V for the inputs/outputs.
The OAs used are the model TLV2475N [17] by Texas Instruments. Their main characteristics are: CMOS Rail-To-Rail Input/Output, shutdown mode, input offset voltage: 2400µV (max), voltage amplification: 88 dB (min). From these parameters it can be deducted that, as commented in Section 3.5, the voltage which appears in the inverter terminal due to the finite gain is, at the most, 3.3 V/25119 = 0.13 mV, 20 times lower than offset voltage. The sensor array consists of eight rows and six columns. In addition, two rows and one column are used to measure the calibration resistors. Its values, along with the values of the capacitors of each of the columns of the array, are indicated in the following section for each of the experiments carried out.

Results and Discussion
The experiments carried out are detailed below:

Experiment 1
This experiment is carried out in order to analyse the performances of the Equation (6). The results are shown in Table 1. Three resistors (560, 5357.51 and 10018.6 Ω) will be measured using 5350 Ω as nominal value for the calibration resistors. The other resistors of the array take the minimum value 560 Ω, this being the worst situation in terms of crosstalk in the array when evaluating the value of a resistor. The capacitors of each column of the array have a nominal value of 47 nF.
The results of R and σ have been obtained carrying out 500 measurements, whilst the errors of columns 4 and 5 of Table 1 show the worst case for the 500 measurements. The same procedure will be used for the other experiments of this section.
The maximum resistance RH permitted in accordance with the Equation (12) for an RL of 560 Ω is 870 Ω, a condition which is not met in any of the two RL resistors. Indeed it is verified that the results for the two last rows of the table show high absolute and relative errors. The same can be observed in the column which shows the systematic error (|R´R|). This happens even when using the Zero pin of the FPGA, as indicated in Section 2.

Experiment 2
In this case, the Equation (6) is once again used, but for a range of resistors (3.3 kΩ-10 kΩ), the minimum value for which is significantly higher than in the previous case. For the calibration resistors, 6.8 kΩ has been taken as the nominal value. The capacitors of each column of the array continue to be the same as in Experiment 1. In this case the value RH in accordance with Equation (12) is 5723.94 Ω, meaning we continue to have resistors which do not form part of the optimal measurement range. Table 2 shows how both the systematic error and the maximum errors are reduced compared to Experiment 1. This confirms the discussion set out in Section 3.5 on the Equation (30), since in this Experiment the terms 2 and 4 of the right member of the equation are reduced proportionally more than term 1, having increased the minimum value of the array resistor. Moreover, since the RL resistor is much greater than in Experiment 1, the Zero pin of the FPGA achieves a smaller value in the OA inverter input. In consequence, these two experiments show that the Equation (6) only applies in resistive sensors where RL > 3 kΩ.

Experiment 3
As observed in Experiment 1, the results are not as desired for the resistor ranges where RL takes lower values. For this reason, in this experiment the circuit of Figure 7 is implemented, allowing an increase in the range of resistors by modifying the row addressing. In this case there are two approximation methods which can be used: the Equation (22) which allows an increase in the range of resistors permitted, and Equation (44) which, in addition to increasing the range, eliminates the influence of the offset voltage on the EBT estimation. The range of resistors used in this case goes from 560 Ω to 3.3 kΩ. A value of 750 Ω has been chosen for the calibration resistors of row c1 and the calibration column. 990 Ω has been taken as nominal value for the calibration resistors of row c2. The capacitors of each column of the array have a value of 330 nF.
As can be seen in Table 3, the errors, both systematic and relative, using the Equation (22) are much lower than those obtained in experiment 1. Moreover, the maximum resistor of the range used exceeds the maximum value permitted, RH = 2163 Ω, obtained from the Equation (16). Table 3 shows how, in greater RH values, these systematic errors are much higher than the others, although they are lower than those obtained for the same resistors of experiment 1.  Table 4 uses the same experimental data as those used in Table 3 but evaluated in accordance with the Equation (44). It can be seen that the systematic error is lower in this case, having considered the effects of offset. However it is observed that the maximum errors are reduced less than the systematic error. This is due to the fact that the Equation (44) uses six independent time measurements to carry out the estimation, whilst Equation (22), only needs four. In this case, no increase is observed in the systematic errors for resistors above value RH.

Experiment 4
This experiment also uses the circuit of Figure 7, and the Equations (22) and (44) to calculate the value of R ij . The only change compared to experiment 3 is the range of resistors to study, 3.3-10 kΩ. A value of 10 kΩ has been chosen for the calibration resistors of row c1 and the calibration column. 6.8 kΩ has been taken as nominal value for the calibration resistors of row c2. The capacitors of each column of the array have a value of 47 nF.
For this range the maximum resistor again exceeds the maximum value permitted, RH = 7560 Ω, obtained from the Equation (16). However, on this occasion, using Equation (22), as indicated in Table 5, does not show any important variations in the systematic and maximum errors for the resistors which exceed RH, as would be expected when increasing RL and for use of the Zero pin.
Again, Table 6 uses the same experimental data as those used in Table 5 but evaluated in accordance with Equation (44). The significant reduction can again be seen in the systematic and maximum errors compared to those obtained by Equation (22).

Conclusions/Outlook
This paper studies the use of a distribution of M rows and N columns for arrays of resistive sensors of different ranges and for many applications, for instance chemical, biological, robotics, etc. This distribution allows access, with a certain degree of parallelism (M simultaneous readings) to the information provided by the sensors. It also allows the use of simple conditioning circuits for analogue-digital conversion. The circuit, which enables a simple connection between the information of the resistive sensor and an FPGA as the converter element, comprises a series of M OAs with capacitive feedback. However, it presents certain limitations due to its inherent nature which reduce its functions. The causes of these limitations include: the appearance of crosstalk, the reduced range of resistors to measure (a function of the minimum resistor of the array), variability and difficulty in measuring parameters and important elements of the circuit (FPGA buffer resistors, the threshold voltages of these buffers, capacitors used in OA feedback) and, finally, the offset voltage and bias currents of the OAs. Different modiffications of the circuit and procedures have been proposed to mitigate each of these limitations. In order to check the effectiveness of the different proposed reading methods, a series of experiments have been carried out for a piezoresistive tactile sensor. Our final proposal achieves a maximum relative systematic error of 0.11% and a maximum relative error of 0.77% for an array with values in the range (556 Ω to 3159 Ω) and a maximum relative systematic error of 0.08% and a maximum relative error of 0.69% for an array with values in the range (3296 Ω to 9975 Ω). Future work will need to evaluate the influence of the finite gain of the OA on the performance of the circuit. It has been shown that in the design proposed in this document, this is much lower than the influence due to offset voltage. However, this may not be the case in other implementations.