Ultra-Low Power High Temperature and Radiation Hard Complementary Metal-Oxide-Semiconductor (CMOS) Silicon-on-Insulator (SOI) Voltage Reference

This paper presents an ultra-low power CMOS voltage reference circuit which is robust under biomedical extreme conditions, such as high temperature and high total ionized dose (TID) radiation. To achieve such performances, the voltage reference is designed in a suitable 130 nm Silicon-on-Insulator (SOI) industrial technology and is optimized to work in the subthreshold regime of the transistors. The design simulations have been performed over the temperature range of −40–200 °C and for different process corners. Robustness to radiation was simulated using custom model parameters including TID effects, such as mobilities and threshold voltages degradation. The proposed circuit has been tested up to high total radiation dose, i.e., 1 Mrad (Si) performed at three different temperatures (room temperature, 100 °C and 200 °C). The maximum drift of the reference voltage VREF depends on the considered temperature and on radiation dose; however, it remains lower than 10% of the mean value of 1.5 V. The typical power dissipation at 2.5 V supply voltage is about 20 μW at room temperature and only 75 μW at a high temperature of 200 °C. To understand the effects caused by the combination of high total ionizing dose and temperature on such voltage reference, the threshold voltages of the used SOI MOSFETs were extracted under different conditions. The evolution of VREF and power consumption with temperature and radiation dose can then be explained in terms of the different balance between fixed oxide charge and interface states build-up. The total occupied area including pad-ring is less than 0.09 mm2.


Introduction
Silicon circuits are increasingly sought by biomedical applications, such as radiation detectors, breathing sensors and temperature sensors. These applications often require ultra-low power circuits, sometimes also robust to harsh environments. Figure 1 shows our previous development [1] of an ultra-low power microsystem, composed of a temperature sensor, a comparator and a voltage reference. This microsystem aims at temperature sensing in the harsh conditions used in medical sterilization such as high total ionized dose radiation (TID) or high temperature. It has three main functions: detecting a user-defined temperature threshold T 0 , generating a wake-up signal that turns on a data-acquisition microprocessor above T 0 , and measuring temperatures above T 0 . The microsystem was developed using a suitable and robust technology, i.e., 1 µm partially-depleted (PD) Silicon-on-Insulator (SOI). Such technology is often used in harsh environments applications because of its attractive features; extended range of working temperature (up to 300 • C), reduced parasitic effects, low-power, high speed and lower sensitivity to transient radiation effects comparing to other technologies [2]. However, during measurements, the voltage reference circuit was the weak point of the microsystem and showed a large shift in the measured reference voltage with radiation of up to 900 mV at 1 Mrad (Si) [3]. To overcome this limitation, a new design of an ultra-low power and harsh-environment immune voltage reference is performed. We firstly choose to port the design to a more suitable SOI industrial technology with Complementary Metal-Oxide-Semiconductor (CMOS) process node of 130 nm featuring a much reduced gate and buried oxides thickness and hence TID degradation [4]. Secondly, we improved the architecture by introducing a cascode bias stage for enhanced stability, and a new start-up design to avoid start deficiency at low temperature and extreme corners (resulting in high V th ). This proposed circuit is optimized to work in the subthreshold regime of the transistors in order to achieve ultra-low power dissipation (less than 100 µW) at high temperature (up to 200 • C).
In this paper, we firstly present the design of the voltage reference circuit. Then, we detail the experimental results of the voltage reference under large range of temperature and under combined high temperature and radiation influence. Lastly, we explain the impact of the combination of high total ionizing dose and high temperature on the proposed circuit and draw conclusions.

Voltage Reference Circuit Description
The voltage reference is a CMOS circuit ( Figure 2) based on the gate-source voltage difference between a pair of P-type MOS (PMOS) and N-type (NMOS) transistors (M p and M n ) biased by a proportional to absolute temperature (PTAT) current I REF (Equation (8)). Differently to the initial work described in [5], our design was: (1) improved by introducing a cascode bias stage for enhanced stability and a new start-up design to avoid start deficiency at extreme temperature and process corners (resulting in high V th ); (2) extended to operate in a large temperature range from −40 to 200 • C; (3) conceived to limit the power dissipation in harsh environments, using transistors optimized to work in subthreshold regime.

VREF
In the next paragraph, operation of our previous circuit [3] is reviewed, and in the next sections, an improved architecture is proposed.

Design Principles
From the analysis of the circuit described in Figure 2, the voltage reference value V REF and the bias current I B are obtained as: where V GSn , V GSp , V GS1 and V GS2 are the gate-source voltages for transistors M n , M p , M 1 and M 2 , respectively. For NMOS and PMOS transistors working in the subthreshold regime, the I − V characteristics can be expressed by [6]: where β n = µ n .C ox .(W n /L n ) and β p = µ p .C ox .(W p /L p ), µ n,p is the electron and holes mobilities in the channel, C ox is the oxide capacitance per unit area, V thn and V thp are the threshold voltages of NMOS and PMOS respectively, W n (W p ) and L n (L p ) are the channel width and length for NMOS (PMOS), respectively. U T = k B .T /q is the thermal voltage (k B is the Boltzmann constant, q the elementary charge and T the absolute temperature), n is the subthreshold slope parameter, V GS and V DS (V SG and V SD ) are the gate-to-source and drain-to-source voltages respectively for the NMOS (PMOS) transistor. For |V DS | > 4U T , the drain current I D becomes almost independent of the drain-to-source voltage [7], so that from Equations (3) and (4) we can extract : In Figure 2, if k is the size ratio (W 1 .L 2 /(L 1 .W 2 )) of transistors M 1 and M 2 , m the current copy ratio in the output stage (I REF = m.I B ) and using Equations (2) and (5), the bias current I B is given by: Assuming that the current through the resistances R 1 and R 2 is negligible and using Equations (1), (5) and (6) we obtain the following expression of V REF : with β Mn(p) = µ n(p) .C ox .(W/L) n(p) for the output transistors M n and M p respectively ( Figure 2). These β parameters (∝ T −α with α ≥1.5) together with the parameter n and the threshold voltage V thn and V thp have a temperature dependency [8,9]. M r is the resistors ratio (R 1 /R 2 ). R B is a non-silicided polysilicon resistance, showing almost negligible temperature dependency in the simulations.

Circuit Realization
A new design of the voltage reference ( Figure 3) was developed with a cascoded current source, to reduce the V REF variations due to the process corners, supply voltage variation and mainly the radiation effects caused by single ionized particles [10]. As it is based on the same principle as the previous design [3], the voltage reference expression V REF remains unchanged (Equation (9)).

Design Optimization
The design optimization consists in determining the bias current I B and the transistor and resistor sizes (in Figure 3) to minimize the V REF variation with the device physical parameters as given by the previous equations and process corners. The temperature dependence of the voltage reference must be as low as possible. The aforesaid dependence is expressed by evaluating the temperature coefficient (T C) defined by the following expression: In order to minimize the T C coefficient for our design, we have extracted temperature dependencies of the physical parameters, computed Equation (10) and searched the best design parameters (W 1 , W 2 , L n , m, M r , W n , W p and R B ). However this first guess does not take into account the process corners. Next, extensive ELDO (Mentor Graphics) simulations were performed for the different process corners in a temperature range of −40 to 200 • C.

Design Robustness Against Radiation Effects
To take into account the variations due to radiation effects, additional constraints were considered as follow: • The designed circuit was checked with custom model parameters of transistors including TID effects on transistors [11] (up to 30% mobilities degradation and negative voltage threshold shifts of 100 mV). • Using transistors with a body contact to limit the effect of the parasitic bipolar possibly created by radiation [10]. • Choosing relatively long transistor to assure lower leakage current and lower threshold voltages shift, which may appear as a result of TID and high-temperature effects [2,12,13]. • The circuit layout is further carried out by paying attention to critical components; thus all matched device pairs were realized by a centroid implementation, including the necessary dummies ( Figure 6).   Size of NMOS M n 20 µm/1 µm (W/L) 9 Size of NMOS M 9 5 µm/0.5 µm

Simulations Results
Simulations are performed for five different process corners and a custom model parameters of transistors including TID effects, namely: As shown in Figure 7, the reference voltage V REF versus temperature range of −40 to 200 • C gives an average voltage of 1.5 V for Typical corner, with a variation of ±8% over all process corners and temperature/radiation conditions. More specifically, lower |V th | values lead to a lower V REF at a given temperature according to Equation (9), whereas the temperature dependence depends on the exact balance between the n, U T and the V th terms.

Experimental Results
The main purpose of our voltage reference is to be used in a harsh biomedical sterilization conditions. To validate this feature, first the voltage reference circuit was measured in a large range of temperatures from −40 to 200 • C. Subsequently, other chips have been tested during irradiation at different temperatures, using a small ceramic heater resistor placed under chips. Irradiation was performed at the Cyclotron facility of UCL with Gamma-rays, using a Cobalt source ( 60 Co). The next sections present the measured results for a power supply of 2.5 V.

Temperature Measurements
The experimental voltage reference generates a mean reference voltage of about 1.5 V (Figure 8) with a variation of about 1%, for the temperature range of −40-90 • C with a temperature coefficient less than 133 ppm/ • C. This increases to 470 ppm/ • C for the large tested temperature range of −40-200 • C with a maximum variation of 10%. The maximum power dissipation is less than 42 µW at the lower temperature of −40 • C, about 50 µW at room temperature and only 75 µW at a high temperature of 200 • C (Figure 9).
The 10% increase of the reference voltage value V REF textitversus temperature can be explained through the increase of the subthreshold current and parameters n, U T and (1/β M n ) shown in the Equation (9). The decrease of the absolute values of threshold voltages of transistors V thn and |V thp | with temperature [8] helps (but not sufficiently) to limit the increase of V REF value versus temperature. To first order, the power dissipation of the circuit is equal to "V DD .(m+2).I B " and according to Equation (8) is proportional to the term n.U T (∝ n.T). This explains the linear variation with temperature of the power dissipation of the reference voltage (Figure 9).

Measurements under Combined High Temperature and Radiation Exposure
Six chips were exposed to gamma-rays radiation during one week with a dose rate of 10 krad/h and regularly measured. Two chips were kept at room temperature, two heated at 100 • C during radiation and the last two chips at 200 • C. The voltage reference value remains about the expected voltage of 1.5 V with a maximum increase of ±5% shift for room and 200 • C temperature. At 100 • C the voltage reference value increases with total dose up to 400 krad (Si) and starts to decrease at higher dose ( Figure 10). The power consumption of the voltage reference increases with radiation and temperature, except for the highest heating temperature during radiation for which the power remains stable at about 75 µW upon radiation ( Figure 11). Similar trends are observed for all measured chips. Similarly to temperature case, we can express the radiation dependencies of the voltage reference circuit. This is about 25 ppm/krad for room temperature up to 1 Mrad (Si).

Discussion of Measurement Results
In order to understand the effect of the combination of radiation and high temperature on the designed voltage reference circuit, the threshold voltages V th n,p for the used SOI transistors were extracted in the same conditions (irradiation + temperatures). Gamma-rays radiation is known to result in oxide and interface charges build-up (N ox and N it ). They shift the threshold voltages as (V th n ∝ (N it − N ox ) and |V th p | ∝ (N it + N ox )) and degrade mobilities in transistors [11].
Thus, for PMOS ( Figure 12) the absolute |V th p | value increases with radiation. This effect is amplified at 200 • C due to higher N it creation. For NMOS transistor (Figure 13), at room temperature, induced N ox charges are dominant (versus N it ) and, therefore V th n value decreases slightly. At 100 • C a balance between N ox and N it occurs and keeps a relatively stable value for V th n versus radiation dose.   (9)) and knowing that the parameter n is increased and the carrier mobilities µ n(p) are degraded both by radiation and temperature [11,14], we can explain the combined effect of radiation and temperature on the circuit (Figures 10 and 11) as follows.
• At room temperature: As the shift of threshold voltages of PMOS and NMOS seems to be small, the increase of V REF and the power dissipation can be explained by the increase of the parameter n and the decrease of the mobility µ n (∝ to 1/β M n ) under radiation.
• At 100 • C: At small dose (less than 400 krad) the same effects as for room temperature occur. For higher dose, the absolute value of the threshold voltage of PMOS increases while the NMOS one remains quasi stable, thus leading to the decrease of the voltage value of V REF and to stabilize the power dissipation.
• At 200 • C: After an initial decrease of V th n and increase of |V th p | which is reflected in a decrease of V REF and the power dissipation, both absolute values of V th n and V th p increase under radiation. Thus, they compensate each other in the Equation (9) Table 2 summarizes the performance of the proposed voltage reference circuit and compares it with results of the literature. When compared to our previous work [3], the new circuit is twice less sensitive to temperature variation and the sensitivity to radiation is divided by more than one order of magnitude thanks to: (1) the suitable SOI technology featuring a reduced oxide thickness (5 nm in this work versus 25 nm in the previous work) which limits oxide charge build-up and hence TID degradation; (2) to the new design circuit performed with reasonable margin for the current consumption.
When compared to literature, the proposed circuit operates in a wider range of temperature −40 to 200 • C and radiation (up to 1 Mrad (Si)) than other solutions. Our circuit proposes a high reference voltage value of 1.5 V with a small current consumption (less than 20 µA at room temperature) and achieves a low temperature coefficient for a similar range of temperature.

Conclusions
In this work we demonstrated an ultra-low power voltage reference circuit, designed in the subthreshold regime of transistors, developed to be used in harsh environment such as biomedical sterilization. This circuit was simulated up to 200 • C using our extended MOS models and was shown to consume about 75 µW only at higher temperature. The design was verified to be robust against radiation effects (using custom model parameters) and the voltage reference value very fairly stable over a large range of process corners and temperature variations. To enhance immunity to total dose effects, the layout has been implemented using specific guidelines and a suitable SOI CMOS technology with thin gate and buried oxides. Measurements have shown a fairly correct operation of such ultra-low power circuit for a large temperature range (from −40 • C up to 200 • C) and under a combination of total ionizing dose (up to 1 Mrad (Si)) and high temperature. The threshold voltages V th n,p for the used SOI transistors were extracted under radiation and temperature. They show a significant increase of the absolute value of PMOS threshold voltage with radiation at high temperature, while for NMOS the threshold voltage value V th n decreases slightly at room temperature, keeps a relative stable value versus radiation dose at 100 • C and increases at higher temperature 200 • C, depending on the balance between N ox and N it build-up. The results fairly support the observed V REF and power consumption dependences on temperature and total dose radiation.