High-Throughput Polar Code Decoders with Information Bottleneck Quantization

In digital baseband processing, the forward error correction (FEC) unit belongs to the most demanding components in terms of computational complexity and power consumption. Hence, efficient implementation of FEC decoders is crucial for next-generation mobile broadband standards and an ongoing research topic. Quantization has a significant impact on the decoder area, power consumption and throughput. Thus, lower bit widths are preferred for efficient implementations but degrade the error correction capability. To address this issue, a non-uniform quantization based on the Information Bottleneck (IB) method is proposed that enables a low bit width while maintaining the essential information. Many investigations on the use of the IB method for Low-density parity-check code) LDPC decoders exist and have shown its advantages from an implementation perspective. However, for polar code decoder implementations, there exists only one publication that is not based on the state-of-the-art Fast Simplified Successive-Cancellation (Fast-SSC) decoding algorithm, and only synthesis implementation results without energy estimation are shown. In contrast, our paper presents several optimized Fast-SSC polar code decoder implementations using IB-based quantization with placement and routing results using advanced 12 nm FinFET technology. Gains of up to 16% in area and 13% in energy efficiency are achieved with IB-based quantization at a Frame Error Rate (FER) of 10−7 and a polar code of N=1024,R=0.5 compared to state-of-the-art decoders.


I. INTRODUCTION
Polar codes are a relatively new class of Forward Error Correction (FEC) codes, first described by Erdal Arıkan in 2009 [1].These codes are part of the 5G standard.They offer low-complexity encoding and decoding algorithms, which is especially important for high-throughput and low-latency applications in upcoming standards such as 6G [2].The most commonly used decoding algorithms for polar codes, Successive Cancellation (SC) and Successive Cancellation List (SCL), can be efficiently pipelined to achieve very high throughput and low latency [3], [4].
Quantization has a significant impact on implementation costs.Coarse quantization improves implementation efficiency in terms of area, power and throughput but may decrease the error-correction performance.Finding a good trade-off is therefore essential for efficient hardware implementations.
One promising technique to maintain the message information but enable a reduction of the bit width is the Information Bottleneck (IB) method [5].Here, an information compression is achieved by maximizing the mutual information between an observed and a compressed random variable for a given bit width.This yields a non-uniform quantization.
While IB-based quantization for Low Density Parity Check (LDPC) decoder implementations is well investigated [6]- [8], the efficiency of the IB method for polar code decoder is quite unexplored.It is an open research question whether IB based quantization in polar decoders can yield more efficient implementations compared to standard quantization methods.It was shown in [8], [9], that a pure lookup table (LUT)based application of the IB method yields very large LUTs, making this approach unfeasible.The Reconstruction Computation Quantization (RCQ) scheme [10] also uses LUTs to reconstruct and, after computation, quantize back to smaller bit width.The resulting LUTs have much lower complexity.Hence, the RCQ scheme is the most promising approach from an implementation perspective.
To the best of our knowledge, only one publication investigates the efficiency of IB-based polar decoder implementation [9].However, the investigations in [9] do not consider the state-of-the-art Fast Simplified Successive Cancellation (Fast-SSC) decoding algorithm and, even more importantly, provides only synthesis results without any power data, which is one of the most important implementation metrics.
This work therefore makes the following new contributions: • We present the first Fast-SSC polar decoder architecture using IB-based quantization with optimized LUTs to improve area and energy efficiency.
• We compare the non-uniform, IB-based quantization scheme with uniformly quantized fixed-point (FP) representations in terms of error correction performance and implementation efficiency for code lengths of 128 bit and 1024 bit.
• We analyse the impact of the IB-based quantization on area and power consumption with 7 different designs in an advanced 12 nm FinFET technology.
The remainder of this paper is structured as follows: We provide the required background of polar codes, their decoding algorithms and the IB method in Sec.II.IB-based Fast-SSC decoding and our decoder architecture is described in Sec.III.Sec.IV presents a detailed comparison with uniformly quantized FP decoders in terms of error correction performance and implementation costs and Sec.V concludes this paper.

A. Polar Codes
Polar codes P(N, K) are linear block codes with code length N = 2 n , that encode K information bits.Channel polarization derives N virtual channels where K reliable channels (information set I) are used to transmit the information.The N − K remaining (unreliable) channels are set to zero and called frozen bits (frozen set F).The encoding includes a bit-reversal permutation [1].

B. Successive Cancellation Decoding
SC decoding can be described as depth-first tree traversal of the Polar Factor Tree (PFT) [11].The PFT has log(N ) + 1 stages s and N leaf nodes at stage s = 0, representing the frozen and information bits.Each node v receives a Log-Likelihood Ratio (LLR) vector α v of size N s to first calculate the N s /2 elements of the left-child message α l by the hardware-efficient min-sum formulation of the ffunction With the bit vector β l received from the left child, the N s /2 elements of α r are calculated using the g-function and sent to the child on the right.With the results of both children, the h-function calculates the partial-sum β v with ⊕, the binary XOR-operator, as that is sent to the parent node.In leaf nodes, bit decisions are made.Frozen bits are 0 per definition, and information bit nodes return the Hard Decision (HD) on the LLR: The decoder outputs the partial-sum β 0 of the root node.

C. Fast-SSC Decoding
Pruning the PFT reduces the number of operations required to decode one code word [11].Subtrees containing only frozen bits do not have to be traversed, because their decoding result is known to be an all-zero vector in advance.Such Rate-0 nodes are always left children and are merged into their parent nodes.Here, the g-and h-functions are executed with the known all-zero β l , denoted by g 0 and h 0 , respectively.Similarly, subtrees without any frozen bits can be decoded directly by the HD, because no parity information is contained.Merging these Rate-1 nodes results in the h 1 -function, which directly calculates β r using and combines it with β l to observe β v .
Fast-SSC decoding [12] applies further optimizations: If a subtree contains only one information bit, it is considered a Repetition (REP) code and replaced by a specialized REP node.All its bits are decoded by summing up the vector α v of received LLR values and extracting the sign bit of the sum: In subtrees containing only one frozen bit, this bit always acts as parity bit.Thus, the partial sum of this subtree represents a Single Parity-Check (SPC) code.A specialized SPC node performs Maximum Likelihood (ML) decoding by calculating the parity γ v ∈ {0, 1} of the input: finding the least reliable bit and setting β v to satisfy the single parity constraint:

D. Information Bottleneck Method
The IB method is a mathematical framework used for clustering in information theory and machine learning [5].In the IB setup, the target is to preserve the shared mutual information I(X; Y ) between an observed random variable Y and the relevant random variable X while compressing Y to T , i. e., maximizing I(T ; X).Different IB algorithms exist [13] to provide the compression mapping p(t|y) derived only from the joint distribution p(x; y) and the cardinality of the compressed event space (|T |), with x ∈ X = {0, 1}, y ∈ Y, t ∈ T being realizations of the random variables X, Y, T , respectively and |T | ≪ |Y|.A collection of IB algorithms is provided by [14] and is used in this work.This compression is applied to the output of an Additive White Gaussian Noise (AWGN) channel to obtain a coarse, non-uniform quantization.
In the case of our IB decoder, y ∈ Y are the received LLRs that are quantized with a high bit width, e.g. 10 bit, which equals |Y| = 2 10 = 1024 bins.The IB algorithm then iteratively tries to find pairs of bins to combine into one bin with the least loss of mutual information I(X; Y ).In that way |Y| is reduced to |T | = 16 (4 bit) and a mapping from y to t is derived.

A. Numerical Representations and LUT Generation
In this paper, we focus on decoders with very high throughput and low latency.These decoders are fully unrolled and pipelined and use a Sign-Magnitude (SM) representation of the quantized, FP LLR values [15].For high Signal-to-Noise-Ratios (SNRs), saturation reduces signal toggling because only the sign bit changes, which reduces power consumption.Additionally, the comparators in the f -functions (1) and SPC nodes (8) can directly operate on the magnitude.To perform the additions in the g-functions (2) and REP nodes (6), the SM representations are converted to Two's-Complement (TC) to efficiently perform the calculations.
Our IB decoder implementations exploit all these optimizations.However, because of the non-uniform distribution characterizing the IB indices, mathematical computations must be replaced by LUTs [9].However, these LUTs can become extremely large.For example, for a g-function (2) with one binary and two LLR inputs, the resulting LUT is of size From an implementation perspective, the LUTs are transformed into Boolean functions.Despite the logic optimization executed by state-of-the-art synthesis tools, the resulting logic costs can quickly outweigh the benefits of reduced bit widths, particularly for increasing LUT sizes [8].
A promising approach to address this problem is the RCQ scheme [10], [16].RCQ combines non-uniform quantization with the traditional node computations.Only small LUTs are necessary that are placed in front of the computation units to upscale the reduced non-uniform IB quantization to a uniform FP quantization (Reconstruction).Node computations are then performed on the uniform FP quantization (Computation).After computation the results are downscaled to smaller bit width (Quantization).The RCQ scheme results in much smaller LUTs because the mappings for the conversions between IB and FP domains can be implemented as LUTs of size 2 Q for each value where Q is the bit width.We use Q IB = log 2 (|T |) and Q FP to denote the bit widths in the IB and FP domains, respectively.For the g-function example mentioned above, the number of entries in the LUTs shrinks from We use density evolution to generate samples.At least 100K samples are monitored at each node in the decoder, i. e., at each edge of the PFT.These samples yield the joint distributions p(x; y) which are input to the IB algorithm [13] that calculates the compression mappings p(t|y) for every edge.Then, the Symmetric information bottleneck algorithm [7], [14] is applied which is optimized to preserve the symmetry of the transmission channel (assuming an AWGN channel and Binary Phase Shift Keying (BPSK) modulation).Exploiting this symmetry enables a bisection of the LUT , because it is sufficient to store only the magnitudes.Accordingly, we use a SM-like representation of the IB indices as shown in the example in Table I for |T | = 8.Therefore, for both directions of conversion (IB to FP, and FP to IB), the LUTs directly map one magnitude to another, i. e., the magnitudes in both domains also act as indices for the LUTs.Thus, the size of each LUT is 2 Q−1 and the total number of entries for the example of the g-function becomes 2 • 2 QIB−1 + 2 QFP−1 .As shown in Figure 1   Furthermore, this approach eliminates the need for multiple comparisons with thresholds per conversion as in [16].
Notation: To differentiate between the numerical representations, we use α to denote values in the IB domain, α for SM and α for TC representation.The j-th bit of the binary expansion of α i is given by α i (j) and the most significant bit (MSB) Q − 1 refers to the sign bit.

B. IB-based Fast-SSC Decoding
1) f -Function: With the symmetric mapping and inherent order of the IB indices (Table I), the f -function (1) can be directly performed in the non-uniform IB domain and no LUTs are necessary, which corresponds to the "re-MS-IB decoder" implementation of [9].In contrast to [9], we map the IB indices so that negative values also correspond to negative LLRs and, thus, do not need to invert the result of the XOR-ed sign bits.
2) g-Function: As in [16], we apply an RCQ scheme, but based on our optimized up-and downscale LUTs: The internal separation between the different number representations is maintained for the reasons described in Sec.III-A and shown in Fig. 1.The Reconstruction with LUT v up maps the magnitude of the IB index α v i to its SM representation αv i with preserved sign bit.β l i must be considered before conversion to the TC representation αv i for the Computation step.The result αr i has a 1 bit larger resolution, implying a saturation for the conversion back to SM representation with Q FP bit.The Quantization step is again realized as magnitude LUT v down for the transformation back to the IB domain.
For the special case of merged Rate-0 nodes, i. e., the g 0function, the XOR-operation with Fig. 2. Unrolled and pipelined Fast-SSC decoder architecture for a P (16,8).
Colors represent numerical domains: green for IB, red for FP, blue for binary and dark green shows the LUTs.
3) REP Nodes: REP nodes calculate the sum over all input values to observe the single (repeated) information bit by HD on the sum (6).Thus, the RCQ scheme as described for the g-function is applied for REP nodes.An adder tree of N s − 1 adders and a depth of s = log 2 N s operates on the TC representations of the N s input values.The final HD as Quantization step extracts the single sign bit as bit decision of the node, for which reason no further conversion of the sum is needed.
4) SPC Nodes: As in the f-function, due to the ordered mapping of the IB indices, the minimum search of the SPC node ( 8) can be performed directly in the IB domain.Furthermore, the chosen mapping is also suitable for the direct parity calculation (7) and the bit estimations (9), because the sign bits are preserved in the IB domain.
5) h 1 -Function: The h 1 -function internally uses the gfunction to compute β r (5).However, in this g-function, the backward conversion is not needed, because the HD is made directly in the compute domain with TC representation, as already described for the REP nodes.

C. Decoder Architecture
An outline of the fully unrolled and deeply pipelined Fast-Simplified SC (SSC) decoder architecture for a P(16, 8) is shown in Figure 2. We omit the clock signals and the delay lines are represented by shift registers.The pipeline consists of various building blocks that implements the decoding functions described in the previous section.The IB, FP and binary domains are represented by the coloring of the blocks and signals.The decoders presented in this paper are based on the framework presented in [15] which we extended to apply the IB method as described above.

IV. RESULTS
We present 7 decoder designs for N = 128 and N = 1024 which are optimized for a target frequency of 500 MHz and 750 MHz, respectively.Throughput is considered as coded throughput.The designs were synthesized with Design Compiler and placed and routed with IC-Compiler, both from Synopsys in a 12 nm FinFET technology with a super-low V t transistor library from Global Foundries under worst case Process, Voltage and Temperature (PVT) conditions (125 °C, 0.72 V) for timing and nominal case PVT (25 °C, 0.8 V) for power.Error-correction performance was simulated for an AWGN channel and BPSK modulation with a minimum of 100 erroneous code words.

A. Decoder for the Polar(128,64) Code
The Frame Error Rate (FER) of the P(128, 64) is shown in Figure 3.The IB decoder with 4 bit and the FP decoder with 5 bit show similar error-correction performance, whereas the error-correction performance of the 4 bit FP decoder starts to degrade at an FER of 10 −3 .Comparing the decoders with similar FER (IB vs. 5 bit FP), we observe similar combinatorial area (logic), whereas the area for the memory (registers) is reduced by 16 %.This improves the area efficiency by 7 % and yields power savings and energy efficiency improvements of 13 %.
When comparing the IB decoder with the 4 bit FP decoder, the cost of the LUTs can be directly observed in the combinatorial area (0.005 mm 2 vs. 0.003mm 2 ) while the area for the registers is identical.This cost can be considered as the price for the improved error correction performance of the IB decoder.
As already mentioned there exits only one other publication that gives implementation results for IB-based decoders.Since the authors of [9] only provide synthesis results in an older 28 nm technology, a fair comparison is difficult.To enable at least some comparison, we scaled the results of [9] to 12 nm according to the equations of [17].The scaled results are included in Table II.We limited the maximum frequency to 1000 MHz which is more reasonable, since 3681 MHz (and even 1510 MHz in the original publication) are not realistic for a design in 28 nm after placement.The reasons are: first, the power consumption and power density becomes infeasible with this high frequency.Second, 3681 MHz are unfeasible for standard placement and routing in semi-custom design flows in 28 nm technology.Even with the scaled estimate without frequency limitation, we observe that our optimised decoders outperform [9] in throughput, latency, area and area efficiency.[17] and maximum frequency limited to 1000 MHz.For 28 nm and 12 nm the scaling factors of 32 nm and 14 nm were used, since they belong to the same technology generation and give the best approximation.
B. Decoder for the Polar(1024,512) Code The longer P(1024, 512) polar code has a longer pipeline and is therefore more affected by accumulating quantization errors.In contrast to the shorter code, 6 bit FP are necessary to match the floating point precision.We compare the 4 bit IB decoder to the FP decoder with 5 bit, as they show similar error-correction performance (Figure 4).Here, the IB decoder even outperforms the 5 bit FP decoder at an FER of 10 −7 .III), the total area is reduced by %, mostly stemming from the reduction in registers.This leads to an improved area efficiency of 18 %, whereas the energy efficiency improves by 15 %. Figure 5 shows the layouts of the 5 bit FP and the 4 bit IB decoder.It is also worth noting that, when compared to the close-to-float 6 bit FP decoder, accepting a small loss of 0.2 dB in the error correction leads to improvements of 41 % in area efficiency and 31 % energy efficiency.We presented fully characterized Fast-SSC Polar Decoders with an optimized IB-based quantization scheme.Especially for ultra-high throughput we outperform decoders with comparable bit-width by 18 % in area efficiency and 15 % in energy efficiency.This effect can be explained by the savings in memory requirements of fully pipelined and unrolled decoders which is minimized with the IB-based quantization.

Fig. 5 .
Fig. 5. Layout pictures for FP and IB polar code decoders

Table
II presents the corresponding implementation results.
Synthesis only, scaled from 28 nm to 12 nm (numbers in brackets) with equations from *

TABLE III IMPLEMENTATION
RESULTS FOR P(1024, 512) DECODERS