A Method Based on Timing Weight Priority and Distance Optimization for Quantum Circuit Transformation

In order to implement a quantum circuit on an NISQ device, it must be transformed into a functionally equivalent circuit that satisfies the device’s connectivity constraints. However, NISQ devices are inherently noisy, and minimizing the number of SWAP gates added to the circuit is crucial for reducing computation errors. To achieve this, we propose a subgraph isomorphism algorithm based on the timing weight priority of quantum gates, which provides a better initial mapping for a specific two-dimensional quantum architecture. Additionally, we introduce a heuristic swap sequence selection optimization algorithm that uses a distance optimization measurement function to select the ideal sequence and reduce the number of SWAP gates, thereby optimizing the circuit transformation. Our experiments demonstrate that our proposed algorithm is effective for most benchmark quantum circuits, with a maximum optimization rate of up to 43.51% and an average optimization rate of 13.51%, outperforming existing related methods.


Introduction
Quantum computing, a new computing paradigm that leverages the superposition and entanglement features of quantum mechanics, has the potential to solve many problems faster than classical computers, such as integer factorization [1] and linear equations [2]. Currently, quantum computing has entered the era of noisy intermediate-scale quantum (NISQ) devices [3]. In contrast to the idealized quantum circuit model, physical quantum architectures have a connectivity constraint, limiting the set of allowable two-qubit gates between specific pairs of qubits. To ensure that a quantum circuit is functionally equivalent to the desired computation and satisfies the connectivity constraint, quantum circuit transformations must be applied. However, NISQ devices suffer from crosstalk noise, which results from unexpected interactions or uncorrected control of qubits. This noise compromises the fidelity of the final circuit execution results [4]. Therefore, minimizing the number of SWAP gates added to the circuit during the transformation process is a critical task for circuit optimization.
The process of transforming a quantum circuit can be divided into two sub-procedures. The first involves finding an initial mapping, which maps logical qubits to physical qubits. The second sub-procedure involves handling quantum gates that violate the interaction constraint in the current mapping by inserting SWAP gates to lead to neighboring qubits. However, determining the minimal number of SWAP gates required for the quantum circuit transformation is an NP complete problem [5]. To solve this problem, various methods have been proposed [6][7][8][9][10][11][12][13][14][15]. One type of method formulates the problem mathematically and uses solvers such as integer linear programming [16], satisfiability module theory [4], constraint planning [17], or Boolean solvers [18] to find solutions. These methods are effective for small quantum circuits. The second type of method uses heuristic algorithms to solve the problem. For example, the backward traversal-based mapping method SABRE [6], Monte Carlo tree search [8], A* search algorithm [7,19], good initial mapping generation [9], Bridge gate insertion [10], reversibility-based comparison of forward and reverse circuit transformation processes [11], greedy algorithm [12], simulated annealing [13], subgraph isomorphism-based mapping [14], and an algorithm based on dynamic look-ahead heuristic cost functions [15] have been proposed. These heuristic algorithms use different evaluation functions to determine the best mapping strategy, based on various factors such as the number of two-qubit quantum gates, the depth of the circuit, the distance between the control qubit and the target qubit, or the topology of the quantum circuit. Some methods also consider the dependency of quantum gates in the circuit and prioritize the execution of preceding gates.
In this paper, we follow a similar approach to the literature [14] by using the number of additional CNOT gates as a metric for measurement, and we utilize subgraph isomorphism as the basic algorithm in the initial mapping. However, in addition to this, we consider the execution order of the quantum gates in the logical quantum circuit during the initial mapping process. Furthermore, we propose a forward-looking heuristic algorithm during the routing process to compare the quantum gate interaction distances, particularly in cases where the interactability rates are equal, to find a better routing path. The proposed method achieves the final transformation of logical quantum circuits to executable physical quantum circuits.
The process of transforming a quantum circuit can be divided into two main steps: (i) initial qubit mapping and (ii) insertion of SWAP gates. In the initial qubit mapping step, we first assign a timing weight to each edge in the circuit's interaction graph and then use a subgraph isomorphism algorithm based on these timing weights to find an initial mapping between the logical qubits and physical qubits. In the SWAP gates insertion step, there may be several possible sequences of SWAP gates that can be applied. To determine the best sequence, we define an interactivity value and a distance optimization measure for each sequence. We propose a sequence selection optimization algorithm based on maximizing the distance measure optimization function, which selects the SWAP gates sequence with the highest value. The experimental results demonstrate the effectiveness of our algorithm.
The paper is structured as follows. In Section 2, we provide definitions and notations related to quantum gates and circuits. Section 3 presents our initial mapping algorithm based on timing weight subgraph isomorphism. In Section 4, we propose a SWAP gate sequence selection optimization algorithm for quantum circuit transformation. In Section 5, we evaluate our approach on benchmark quantum circuits and compare it with a state-ofthe-art method. We conclude the paper in Section 6.

Preliminaries
In this section, we provide the fundamental definitions and notations related to quantum circuits.

Quantum Gate and Quantum Circuit
In quantum computing, quantum bits (qubits) are the fundamental unit of quantum information [20]. In contrast to classical bits, which only have two states (0 and 1), the state |φ of a qubit is a superposition of the two states |φ = α|0 + β|1 , where |α| 2 + |β| 2 = 1. Quantum gates are used to operate on qubits in quantum computers. Single-qubit gates operate on a single qubit, while two-qubit gates operate on two qubits. A two-qubit gate g is denoted as g = p, q and indicates that g operates on qubits p and q. The CNOT gate (see Figure 1a) is an example of a two-qubit gate, where p is the control qubit and q is the target qubit. If p is in state 1, the CNOT gate flips the state of q, and if p is in state 0, q remains unchanged. A SWAP gate p, q exchanges the states of p and q, and can be realized by cascading three CNOT gates (see Figure 1b). Quantum circuits are used to describe quantum algorithms and are composed of qubits, quantum gates, measurement gates, classical registers, and so on. We use LC = (Q, C) to denote a quantum circuit, where Q and C represent the set of qubits and the set of quantum gates in the circuit, respectively. Since the CNOT gate and all single-qubit gates are widely used as universal quantum gates set, and the single-qubit gates are compliant with the connectivity constraint, we only consider quantum circuits composed of two-qubit gates in this paper. g 0 g 1 g 2 g 3 g 4 g 5 g 6 g 7 Figure 2. A quantum circuit with four qubits and eight CNOT gates.

Dependency Graph and Interaction Graph
Given a quantum circuit LC = (Q, C), we define two graphs: the dependency graph, DG, and the interaction graph, IG. DG is a directed acyclic graph whose nodes are the gates in C. There is a directed edge from gate g i to gate g j in DG if g i operates on a qubit q and g j is the next gate that operates on q after g i . IG is an undirected graph whose nodes are the qubits in Q. There is an edge between two qubits q i and q j in IG if they are operated by some gate. Figure 3 shows the dependency graph and interaction graph of the quantum circuit in Figure 2. The dependency graph captures the dependencies between gates in the circuit, while the interaction graph shows the connectivity of qubits in the circuit. Figure 3. The dependency graph and interaction graph of the quantum circuit in Figure 2. The dependency graph, shown in (a), is a directed acyclic graph with nodes representing gates in the circuit and directed edges representing dependencies between gates. The interaction graph, shown in (b), is an undirected graph with nodes representing qubits in the circuit and edges representing interactions between qubits.
The dependency graph is a useful tool to represent the execution order of quantum gates in a quantum circuit, while the interaction graph is commonly used to represent the interaction relationships between qubits in a quantum circuit [14].

Initial Qubit Mapping
A physical quantum device can be represented by its coupling graph CG, which is an undirected graph (V, E) where each qubit in the device is a node in V, and there is an edge (q i , q j ) ∈ E between two nodes q i and q j if they can be operated by a two-qubit gate in the device. For instance, Figure 4 shows the coupling graph of IBM QX20 Tokyo.  Given a quantum circuit LC = (Q, C) and a coupling graph CG = (V, E), an initial mapping π is an injection from Q to V. To find an effective initial mapping, it is important to consider the following two conditions when designing the algorithm: 1.
Logical qubits that interact frequently should be mapped to physically adjacent qubits.

2.
Qubits with high execution priority, based on the order of quantum gates in the circuit, should be mapped to adjacent physical qubits.
By taking into account these conditions, we can design an initial mapping algorithm that can improve the performance and efficiency of quantum circuit execution on physical devices.

Timing Weight
To further improve the effectiveness of the initial mapping algorithm, we can introduce another metric called timing weight. The timing weight takes into account the execution order of quantum gates and the interaction relationships between qubits in the quantum circuit. In this subsection, we define the timing weight for quantum gates and edges in the interaction graph and explain how it can be used to design an improved initial mapping algorithm. Definition 1. Given a quantum circuit LC = (Q, C), where Q = {q 0 , q 1 , . . . , q m } and C = {g 0 , . . . , g n−1 }, the timing weight, k i , for each quantum gate g i is where 0 ≤ i ≤ n − 1 is the execution order of g i .

Definition 2.
Let IG be the interaction graph of LC. For each edge (p, q) in IG, where p, q are qubits in LC, the timing weight, ω (p,q) , of (p, q) is where k i (k j ) is the timing weight of g i (g j ).
The timing weight measures the importance of a quantum gate in the execution order of a quantum circuit, with lower weights assigned to gates executed later. The timing weight of an edge in the interaction graph represents the total timing weight of the gates that interact through that edge. Figure 5 displays the timing weights of the gates in the circuit of Figure 2 and the timing weights of the edges in its interaction graph. The edge (q 0 , q 2 ) has the largest weight, indicating that the gates associated with these qubits are executed first in the circuit. As q 0 and q 2 contain the most CNOT gates in the circuit, they should be mapped as nearest neighbors.

Initial Mapping Based on Timing Weight
To construct an initial mapping for a quantum circuit LC and a coupling graph CG, we first compute the interaction graph IG of LC with timing weights assigned to each edge. If IG is isomorphic to a subgraph of CG, we can construct an initial mapping from the isomorphism without adding any SWAP gates. However, when IG cannot be directly mapped to CG, we use a partial subgraph isomorphism based on timing weight. This means that edges with larger timing weights are given higher priority in the mapping process.
The timing weight of each edge in IG not only indicates the qubits with more CNOT executions but also the execution order of the CNOT gates in the circuit. Thus, it is an important factor in finding an optimal initial mapping that provides a better precondition for subsequent quantum circuit transformations. We propose an initial mapping algorithm based on timing weight subgraph isomorphism, as outlined in Algorithm 1. The algorithm takes LC and CG as inputs and constructs an initial mapping by searching every edge from the one with the highest timing weight.
Algorithm 1 outlines the steps for constructing an initial mapping based on timing weight subgraph isomorphism. To begin, we initialize the set of edges Edge s et of IG. Lines 2-8 compute the interaction graph, IG, of LC with timing weights for all edges. Line 9 sorts the edges from the largest timing weight to the smallest timing weight. Lines 10-16 construct a graph ig starting from the edge with the largest timing weight and add the edge to ig if there is a subgraph isomorphism from ig to CG. If there is no subgraph isomorphism, the edge is skipped. This process is repeated until all the edges in Edge s et are traversed. Finally, an initial mapping is constructed from ig and saved in results. It is important to note that the initial mapping obtained may not be unique, as it depends on the subgraph isomorphism found from ig to CG in the algorithm.

Algorithm 1 Initial mapping based on timing weight subgraph isomorphism
Input: A quantum circuit LC = (Q, C) and a coupling graph CG = (V, E). Output: An initial mapping from Q to V.
1: Initialize: results ← ∅; Edge_set ← ∅ 2: for each gate g i ∈ LC do 3: if g i = p, q or g i = p, q then 5: end if 8: end for 9: Edge_set.sort() 10: while Edge_set = ∅ do 11: if ig ∪ Edge_set.pop() is isomorphic to a subgraph of CG then 12: ig ← ig ∪ Edge_set.pop()  Figure 2 and the coupling graph of IBM QX20 shown in Figure 4, we can obtain three initial mappings (colored in red) as shown in Figure 6. It is important to note that the initial mapping obtained may not be unique, as it depends on the subgraph isomorphism found from the algorithm. π 1 π 2 π 3 Figure 6. Three initial mappings from the circuit in Figure 2 to IBM QX20.

Quantum Circuit Transformation and Optimization
Given the quantum circuit LC, the coupling graph CG, and the mapping π from LC to CG, we need to ensure that every quantum gate in LC is mapped to adjacent qubits in CG. If a gate violates this interaction condition, we can add SWAP gates to the circuit to make the two qubits operated by the gate adjacent. This process can be repeated for every edge in CG. We use SWAP(e) to denote the application of a SWAP gate on the two ends of e. After performing a swap operation, a new mapping π can be obtained by updating π. For instance, in Figure 6, the initial mapping π 1 is {q 0 → 1, q 1 → 0, q 2 → 10, q 3 → 6}. We can apply SWAP(5, 6) and SWAP(1, 6) to obtain the mapping π 2 = {q 0 → 6, q 1 → 0, q 2 → 10, q 3 → 5}.

Swap Sequence Selection
During the quantum circuit transformation process, a sequence of SWAP gates is added to ensure that every gate in the circuit satisfies the interaction condition with respect to the coupling graph. However, this sequence is not unique, and we aim to find the shortest sequence that minimizes the number of gates in the resulting circuit.
Let π be a mapping from the quantum circuit LC to the coupling graph CG, and let a = (SWAP(e 1 ), SWAP(e 2 ), . . . , SWAP(e n )) be a sequence of SWAP gates, where each e i (1 ≤ i ≤ n) is an edge of CG. We use g ex to denote the number of gates in LC that are executable after applying the sequence a from mapping π. To measure the effectiveness of the transformation, we define the interactivity value: where len(a) = n is the number of SWAP gates in a. A larger value of G val (π, a) indicates that the sequence a is more effective in transforming the circuit. Therefore, we aim to find the sequence b that maximizes G val (π, b) for a given mapping π. Now let us consider an example to see how the swap sequence selection algorithm works in practice. Figure 2 and the initial mapping π 1 = q 0 → 1, q 1 → 0, q 2 → 10, q 3 → 6 in Figure 6. The first quantum gate that violates the interactive constraint is g 0 = q 2 , q 0 . To address this issue, we explore four different swap ways and the number of gates that can be executed for each one, as follows: We can then evaluate the validity of each sequence using the metric G val , and obtain G val (π 1 , 1) = 7/2, G val (π 1 , 2) = 7/2, G val (π 1 , 3) = 2, and G val (π 1 , 4) = 3. Based on these values, we conclude that the candidate sequences are (i) and (ii).

Sequence Selection Optimization
For large-scale quantum circuits, there are often multiple swap sequences that satisfy the interactivity constraint, as shown in Example 4. In this subsection, we propose a sequence selection optimization algorithm to find a better swap sequence from the candidate sequences.
Given the quantum circuit LC, the coupling graph CG, and the mapping π from LC to CG, we use dist ph (g, π) to denote the length of the shortest path between π(p) and π(q) in CG for every gate g = p, q in LC. Let a be a sequence of SWAP gates, and let π[a] denote the new mapping obtained by applying a to π. We define the set S = {g | dist ph (g, π[a]) < dist ph (g, π)}, which contains the gates whose execution order is affected by the sequence a. We then define the distance optimization measure as follows: where k i is the timing weight of g i . The value of Ω g (π, a) depends on the timing weight of every gate in S. A gate g i with a large value of k i means that g i has a high execution order. Therefore, Ω g (π, a) indicates the priority of the sequence a; a sequence with a larger Ω g (π, a) should be selected first. To select the best swap sequence, we compute the Ω g (π, a) values for each candidate sequence using Equation (4), and choose the sequence with the largest value. The swap sequence selection optimization algorithm is presented in Algorithm 2. The inputs of the algorithm are a quantum circuit, a coupling graph, and an initial mapping. The output is a transformed quantum circuit that is compliant with the connectivity constraint.

Algorithm 2 Sequence selection optimization algorithm
Input: A quantum circuit LC, a coupling graph CG, and an initial mapping π 0 . Output: A quantum circuit PC that is compliant with connectivity constraint of CG.

5:
PC ← PC.add(g) 6: else 7: max G val ← G val (π, (a, SWAP)).sort() 8: (compute the G val for all possible SWAP gates and save the largest ones) 9: for each SWAP ∈ max G val do 10: swap ← max Ω g (π, (a, SWAP)) 11: (compute the Ω g for all sequences in max G val and take one of the largest) 12: end for 13: a ← (a, swap) LC ← LC.remove(g) 18: end if 19: end for 20: return PC The algorithm starts by initializing the necessary variables. It adds all quantum gates that meet the connectivity constraint in PC and removes them from LC according to their execution order in the current mapping, as described in Lines 3-5. If no gate can be added to PC, indicating that SWAP gates must be inserted, the algorithm computes the G val for all possible SWAP gate sequences and saves those with the largest value in max G val , as shown in Line 7. Next, Lines 9-12 compute the Ω g for all sequences in max G val and selects the one that has the largest value. Finally, Lines 13-17 update LC, PC, π, and a based on the SWAP gates added.
To illustrate how the sequence selection optimization algorithm works, let us consider the following example.

Evaluation
To assess the effectiveness of the proposed methods, we now turn to evaluate their performance on a variety of quantum circuits. We provide experimental results and comparisons with existing approaches in this section.
The proposed methods were implemented in Python, and the experiments were conducted on a Windows 10 machine with an Intel Core i7 processor and 16 GB of RAM. The quantum circuits used in the experiments were publicly available benchmarks evaluated in [14]. The experimental comparison baseline is the number of CNOT gates inserted by the quantum circuit transformation. In this paper, we classify quantum circuits with less than 1000 gates as small scale, those with greater than 1000 and less than 10,000 gates as medium scale, and those with more than 10,000 gates as large scale. Tables 1-3 show the results of the experiments for small scale, medium scale, and large scale circuits, respectively. The first column in each table lists the benchmark, the second column "QubitNu" shows the number of qubits in the circuit, and the third column "GateNu" shows the number of CNOT gates in the circuit. The fourth and fifth columns, labeled "AuxGt", show the number of auxiliary CNOT gates added by the transformation algorithm in [6,14], respectively, and serve as the main comparative baseline for the experiments. The sixth column shows the number of auxiliary CNOT gates added by the algorithm proposed in this paper. The seventh and eighth columns, labeled "Comp.", show the optimization rate compared with the literature [6,14]. The last row of each table shows the average optimization rate.
In order to evaluate the effectiveness of the proposed quantum circuit transformation optimization algorithm, we compare the experimental results with two previous algorithms, Sabre [6] and Topgraph [14]. Sabre is integrated in the IBMQ quantum cloud platform, which represents the current optimal level of IBMQ, and Topgraph is the basis of algorithm improvement in this paper. Therefore, they are selected as the baselines for the experiments in this paper. From the experimental results in the three tables, it is evident that the quantum circuit transformation optimization algorithm in this paper outperforms Sabre, with the highest average optimization rate reaching 70.15%. In comparison with Topgraph, the algorithm proposed in this paper achieves a minimum average optimization rate of 4.30% on small-scale circuits and 21.79% on large-scale circuits. Although two quantum circuits in the medium-scale circuit are not optimized, the average optimization rate still reaches 22.04%. Overall, the proposed algorithm has a significant optimization effect on circuits of any scale, with the larger circuits showing more obvious optimization.