J. Low Power Electron. Appl.2014, 4(3), 214-230; doi:10.3390/jlpea4030214 - published 28 August 2014 Show/Hide Abstract
Abstract: Static random access memory (SRAM) is the most commonly employed semiconductor in the design of on-chip processor memory. However, it is unlikely that the SRAM technology will have a cell size that will continue to scale below 45 nm, due to the leakage current that is caused by the quantum tunneling effect. Magnetic random access memory (MRAM) is a candidate technology to replace SRAM, assuming appropriate dimensioning given an operating threshold voltage. The write current of spin transfer torque (STT)-MRAM is a known limitation; however, this has been recently mitigated by leveraging perpendicular magnetic tunneling junctions. In this article, we present a comprehensive comparison of spin transfer torque-MRAM (STT-MRAM) and SRAM cache set banks. The non-volatility of STT-MRAM allows the definition of new instant on/off policies and leakage current optimizations. Through our experiments, we demonstrate that STT-MRAM is a candidate for the memory hierarchy of embedded systems, due to the higher densities and reduced leakage of MRAM.We demonstrate that adopting STT-MRAM in L1 and L2 caches mitigates the impact of higher write latencies and increased current draw due to the use of MRAM. With the correct system-on-chip (SoC) design, we believe that STT-MRAM is a viable alternative to SRAM, which minimizes leakage current and the total power consumed by the SoC.
J. Low Power Electron. Appl.2014, 4(3), 201-213; doi:10.3390/jlpea4030201 - published 16 July 2014 Show/Hide Abstract
Abstract: The global variability of ultra-thin body and buried oxide (UTBB) MOSFETs in subthreshold and off regimes of operation is analyzed. The variability of the off-state drain current, subthreshold slope, drain-induced barrier lowering (DIBL), gate leakage current, threshold voltage and their correlations are considered. Two threshold voltage extraction techniques were used. It is shown that the transconductance over drain current (gm/Id) method is preferable for variability studies. It is demonstrated that the subthreshold drain current variability in short channel devices cannot be described by threshold voltage variability. It is suggested to include the effective body factor incorporating short channel effects in order to properly model the subthreshold drain current variability.
J. Low Power Electron. Appl.2014, 4(3), 188-200; doi:10.3390/jlpea4030188 - published 15 July 2014 Show/Hide Abstract
Abstract: Field programmable gate arrays (FPGAs) are one of the most widespread reconfigurable devices in which various functions can be implemented by storing circuit connection information and logic values into configuration memories. One of the most important issues in the modern FPGA is the reduction of its static leakage power consumption. Flex Power FPGA, which has been proposed to overcome this problem, uses a body biasing technique to implement the fine-grained threshold voltage (Vt) programmability in the FPGA. A low-Vt state can be assigned only to the component circuits along the critical path of the application design mapped on the FPGA, so that the static leakage power consumption can be reduced drastically. Flex Power FPGA is an important application target for the SOTB (silicon on thin buried oxide) device, which features a wide-range body biasing ability and the high sensitivity of Vt variation by body biasing, resulting in a drastic subthreshold leakage current reduction caused by static leakage power. In this paper, the Flex Power FPGA test chip is fabricated in SOTB technology, and the functional test and performance evaluation of a mapped 32-bit binary counter circuit are performed successfully. As a result, a three orders of magnitude static leakage reduction with a bias range of 2.1 V demonstrates the excellent Vt controllability of the SOTB transistors, and the 1.2 V bias difference achieves a 50× leakage reduction without degrading speed.
J. Low Power Electron. Appl.2014, 4(3), 168-187; doi:10.3390/jlpea4030168 - published 7 July 2014 Show/Hide Abstract
Abstract: Minimum energy per operation is typically achieved in the subthreshold region where low speed and low robustness are two challenging problems. This paper studies the impact of back biasing (BB) schemes on these features for 28 nm FDSOI technology at three levels of abstraction: gate, library and IP. We show that forward BB (FBB) can help cover a wider design space in terms of the optimal frequency of operation while keeping minimum energy. Asymmetric BB between NMOS and PMOS can mitigate the effect of systematic mismatch on the minimum energy point (MEP) and robustness. With optimal asymmetric BB, we achieve either a MEP reduction up to 18% or a 36× speedup at the MEP. At the IP level, we confirm the MEP configurability with BB with synthesis results of microcontrollers at 0.35 V.We show that the use of a mix of overdrive FBB voltages further improves the energy efficiency. Compared to bulk 65 nm CMOS, we were able 28 nm FDSOI to reduce the energy per cycle by 64% or to increase the frequency of operation by 7×, while maintaining energy per operation below 3 µW/MHz over a wide frequency range.
J. Low Power Electron. Appl.2014, 4(2), 153-167; doi:10.3390/jlpea4020153 - published 20 June 2014 Show/Hide Abstract
Abstract: The scaled charge trapping (CT) type silicon on insulator (SOI) FinFET flash memories with different blocking layer materials of Al2O3 and SiO2 have successfully been fabricated, and their electrical characteristics including short-channel effect (SCE) immunity, threshold voltage (Vt) variability, and the memory characteristics have been comparatively investigated. It was experimentally found that the better SCE immunity and a larger memory window are obtained by introducing a high-k Al2O3 blocking layer instead of a SiO2 blocking layer. It was also confirmed that the variability of Vt before and after one program/erase (P/E) cycle is almost independent of the blocking layer materials.
J. Low Power Electron. Appl.2014, 4(2), 138-152; doi:10.3390/jlpea4020138 - published 11 June 2014 Show/Hide Abstract
Abstract: Near threshold circuits (NTC) are an attractive and promising technology that provides significant power savings with some delay penalty. The combination of NTC technology with MOS current mode logic (MCML) is examined in this work. By combining MCML with NTC, the constant power consumption of MCML is reduced to leakage power levels that can be tolerated in certain modern applications. Additionally, the speed of NTC is improved due to the high speed nature of MCML technology. A 14 nm Fin field effect transistor (FinFET) technology is used to evaluate these combined circuit techniques. A 32-bit Kogge Stone adder is chosen as a demonstration vehicle for feasibility analysis. MCML with NTC is shown to yield enhanced power efficiency when operated above 1 GHz with a 100% activity factor as compared to standard CMOS. MCML with NTC is more power efficient than standard CMOS beyond 9 GHz over a wide range of activity factors. MCML with NTC also exhibits significantly lower noise levels as compared to standard CMOS. The results of the analysis demonstrate that pairing NTC and MCML is efficient when operating at high frequencies and activity factors.