Abstract: Ultra-low power applications often require several kb of embedded memory and are typically operated at the lowest possible operating voltage (VDD) to minimize both dynamic and static power consumption. Embedded memories can easily dominate the overall silicon area of these systems, and their leakage currents often dominate the total power consumption. Gain-cell based embedded DRAM arrays provide a high-density, low-leakage alternative to SRAM for such systems; however, they are typically designed for operation at nominal or only slightly scaled supply voltages. This paper presents a gain-cell array which, for the first time, targets aggressively scaled supply voltages, down into the subthreshold (sub-VT) domain. Minimum VDD design of gain-cell arrays is evaluated in light of technology scaling, considering both a mature 0.18 μm CMOS node, as well as a scaled 40 nm node. We first analyze the trade-offs that characterize the bitcell design in both nodes, arriving at a best-practice design methodology for both mature and scaled technologies. Following this analysis, we propose full gain-cell arrays for each of the nodes, operated at a minimum VDD. We find that an 0.18 μm gain-cell array can be robustly operated at a sub-VT supply voltage of 400mV, providing read/write availability over 99% of the time, despite refresh cycles. This is demonstrated on a 2 kb array, operated at 1 MHz, exhibiting full functionality under parametric variations. As opposed to sub-VT operation at the mature node, we find that the scaled 40 nm node requires a near-threshold 600mV supply to achieve at least 97% read/write availability due to higher leakage currents that limit the bitcell’s retention time. Monte Carlo simulations show that a 600mV 2 kb 40 nm gain-cell array is fully functional at frequencies higher than 50 MHz.
Abstract: Usually Wide Dynamic Range (WDR) sensors that autonomously adjust their integration time to fit intra-scene illumination levels use a separate digital memory unit. This memory contains the data needed for the dynamic range. Motivated by the demands for low power and chip area reduction, we propose a different implementation of the aforementioned WDR algorithm by replacing the external digital memory with an analog in-pixel memory. This memory holds the effective integration time represented by analog encoding voltage (AEV). In addition, we present a “ranging” scheme of configuring the pixel integration time in which the effective integration time is configured at the first half of the frame. This enables a substantial simplification of the pixel control during the rest of the frame and thus allows for a significantly more remarkable DR extension. Furthermore, we present the implementation of “ranging” and AEV concepts on two different designs, which are targeted to reach five and eight decades of DR, respectively. We describe in detail the operation of both systems and provide the post-layout simulation results for the second solution. The simulations show that the second design reaches DR up to 170 dBs. We also provide a comparative analysis in terms of the number of operations per pixel required by our solution and by other widespread WDR algorithms. Based on the calculated results, we conclude that the proposed two designs, using “ranging” and AEV concepts, are attractive, since they obtain a wide dynamic range at high operation speed and low power consumption.
Abstract: This paper presents an energy-efficient solar energy harvesting and sensing microsystem that harvests solar energy from a micro-power photovoltaic module for autonomous operation of a gas sensor. A fully integrated solar energy harvester stores the harvested energy in a rechargeable NiMH microbattery. Hydrogen concentration and temperature are measured and converted to a digital value with 12-bit resolution using a fully integrated sensor interface circuit, and a wireless transceiver is used to transmit the measurement results to a base station. As the harvested solar energy varies considerably in different lighting conditions, in order to guarantee autonomous operation of the sensor, the proposed area- and energy-efficient circuit scales the power consumption and performance of the sensor. The power management circuit dynamically decreases the operating frequency of digital circuits and bias currents of analog circuits in the sensor interface circuit and increases the idle time of the transceiver under reduced light intensity. The proposed microsystem has been implemented in a 0.18 µm complementary metal-oxide-semiconductor (CMOS) process and occupies a core area of only 0.25 mm2. This circuit features a low power consumption of 2.1 µW when operating at its highest performance. It operates with low power supply voltage in the 0.8V to 1.6 V range.
Abstract: Loop control is an essential area of electronics engineering that today’s professionals need to master. Rather than delving into extensive theory, this practical book focuses on what you really need to know for compensating or stabilizing a given control system. You can turn instantly to practical sections with numerous design examples and ready-made formulas to help you with your projects in the field. You also find coverage of the underpinnings and principles of control loops so you can gain a more complete understanding of the material. This authoritative volume explains how to conduct analysis of control systems and provides extensive details on practical compensators. It helps you measure your system, showing how to verify if a prototype is stable and features enough design margin. Moreover, you learn how to secure high-volume production by bench-verified safety margins.
Abstract: This paper presents an energy efficient bootstrapped CMOS driver to enhance the switching speed for driving large RC load for ultra-low-voltage CMOS VLSI. The proposed bootstrapped driver eliminates the leakage paths in the conventional bootstrapped driver to achieve and maintain more positive and negative boosted voltage levels of the boosted nodes, thus improving boosting efficiency and enhancing driver switching speed. Measured performance from test chips implemented with UMC 65 nm low-power CMOS technology (VTN ≈ VTP ≈ 0.5 V) indicates that the proposed driver provides a rising-delay improvement of 37%–50% and a falling-delay improvement of 25%–47% at 0.3 V for a loading ranging from a 0 to 24 mm long M6 metal line compared with the conventional bootstrapped driver. Although designed and optimized for subthreshold ultra low-voltage operation, the proposed bootstrapped driver is shown to be advantageous at higher nearly-threshold supply voltage as well. The proposed driver provides a rising delay improvement of 20% to 52% and a falling delay improvement of 23%–43% for VDD ranging from 0.3 V to 0.5 V, while consuming about 15% less average power than the conventional bootstrapped driver driving a 16 mm long M6 wire.
Abstract: This paper reviews the direct connection of sensors to microcontrollers without using any analogue circuit (such as an amplifier or analogue-to-digital converter) in the signal path, thus resulting in a low-cost, lower-power sensor electronic interface. It first discusses the operating principle and explains how resistive and capacitive sensors with different topologies (i.e., single, differential and bridge type) can be directly connected to a microcontroller to build the so-called direct interface circuit. It then shows some applications of the proposed circuits using commercial devices and discusses their performance. Finally, it deals with the power consumption and proposes some design guidelines to reduce the current consumption of such circuits in active mode.
