Open AccessArticle
SoC-Based Edge Computing Gateway in the Context of the Internet of Multimedia Things: Experimental Platform
J. Low Power Electron. Appl. 2018, 8(1), 1; doi:10.3390/jlpea8010001 -
Abstract
This paper presents an algorithm/architecture and Hardware/Software co-designs for implementing a digital edge computing layer on a Zynq platform in the context of the Internet of Multimedia Things (IoMT). Traditional cloud computing is no longer suitable for applications that require image processing due
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This paper presents an algorithm/architecture and Hardware/Software co-designs for implementing a digital edge computing layer on a Zynq platform in the context of the Internet of Multimedia Things (IoMT). Traditional cloud computing is no longer suitable for applications that require image processing due to cloud latency and privacy concerns. With edge computing, data are processed, analyzed, and encrypted very close to the device, which enable the ability to secure data and act rapidly on connected things. The proposed edge computing system is composed of a reconfigurable module to simultaneously compress and encrypt multiple images, along with wireless image transmission and display functionalities. A lightweight implementation of the proposed design is obtained by approximate computing of the discrete cosine transform (DCT) and by using a simple chaotic generator which greatly enhances the encryption efficiency. The deployed solution includes four configurations based on HW/SW partitioning in order to handle the compromise between execution time, area, and energy consumption. It was found with the experimental setup that by moving more components to hardware execution, a timing speedup of more than nine times could be achieved with a negligible amount of energy consumption. The power efficiency was then enhanced by a ratio of 7.7 times. Full article
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Open AccessArticle
A Low-Power CMOS Piezoelectric Transducer Based Energy Harvesting Circuit for Wearable Sensors for Medical Applications
J. Low Power Electron. Appl. 2017, 7(4), 33; doi:10.3390/jlpea7040033 -
Abstract
Piezoelectric vibration based energy harvesting systems have been widely utilized and researched as powering modules for various types of sensor systems due to their ease of integration and relatively high energy density compared to RF, thermal, and electrostatic based energy harvesting systems. In
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Piezoelectric vibration based energy harvesting systems have been widely utilized and researched as powering modules for various types of sensor systems due to their ease of integration and relatively high energy density compared to RF, thermal, and electrostatic based energy harvesting systems. In this paper, a low-power CMOS full-bridge rectifier is presented as a potential solution for an efficient energy harvesting system for piezoelectric transducers. The energy harvesting circuit consists of two n-channel MOSFETs (NMOS) and two p-channel MOSFETs (PMOS) devices implementing a full-bridge rectifier coupled with a switch control circuit based on a PMOS device driven by a comparator. With a load of 45 kΩ, the output rectifier voltage and the input piezoelectric transducer voltage are 694 mV and 703 mV, respectably, while the VOUT versus VIN conversion ratio is 98.7% with a PCE of 52.2%. The energy harvesting circuit has been designed using 130 nm standard CMOS process. Full article
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Open AccessArticle
Forwarding Path Limitation and Instruction Allocation for In-Order Processor with ALU Cascading
J. Low Power Electron. Appl. 2017, 7(4), 32; doi:10.3390/jlpea7040032 -
Abstract
Much research focuses on many-core processors, which possess a vast number of cores. Their area, energy consumption, and performance have a tendency to be proportional to the number of cores. It is better to utilize in-order (IO) execution for better area/energy efficiency. However,
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Much research focuses on many-core processors, which possess a vast number of cores. Their area, energy consumption, and performance have a tendency to be proportional to the number of cores. It is better to utilize in-order (IO) execution for better area/energy efficiency. However, expanding two-way IO to three-way IO offers very little improvement, since data dependency limits the effectiveness. In addition, if the core is changed from IO to out-of-order (OoO) execution to improve Instruction Per Cycle(IPC), area and energy consumption increases significantly. The combination of IO execution and Arithmetic Logic Unit(ALU) cascading is an effective solution to alleviate this problem. However, ALU cascading is implemented by complex bypass circuits because it requires a connection between all outputs and all inputs of all ALUs. The hardware complexity of the bypass circuits increases area, energy consumption, and delay. In this study, we proposed a mechanism that limits the number of the forwarding paths and allocates instructions to ALUs in accordance with the limited paths. This mechanism scales down bypass circuits to reduce the hardware complexity. Our evaluation results show that our proposed mechanism can reduce the area by 38.7%, the energy by 41.1%, and the delay by 23.2% with very little IPC loss on average, as compared with the conventional mechanism. Full article
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Open AccessArticle
Analysis of Sensitivity and Power Consumption of Chopping Techniques for Integrated Capacitive Sensor Interface Circuits
J. Low Power Electron. Appl. 2017, 7(4), 31; doi:10.3390/jlpea7040031 -
Abstract
In this paper, parameters related to the sensitivity of the interface circuits for capacitive sensors are determined. Both the input referred noise and capacitance of the input transistors are important for capacitive sensitivity. Chopping is an effective technique for signal conditioning circuits because
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In this paper, parameters related to the sensitivity of the interface circuits for capacitive sensors are determined. Both the input referred noise and capacitance of the input transistors are important for capacitive sensitivity. Chopping is an effective technique for signal conditioning circuits because of its capability of reducing circuit noise at low frequencies. The capacitive sensitivity and power consumption of various chopping techniques including the dual chopper amplifier (DCA), single chopper amplifier (SCA) and two-stage single chopper amplifier (TCA) are extracted for different values of total gain and sensor capacitance. The minimum sensitivity for each technique will be extracted based on the gain and sensor capacitance. It will be shown that designation of the amplifier and distribution of gain in the TCA and DCA are important for sensitivity. A design procedure for chopper amplifiers that illustrates the steps required to achieve either the best or the desired sensitivity while minimizing power consumption will be presented. It will be shown that for a small sensor capacitance and large total gain, the DCA has the best sensitivity, while for a large sensor capacitance and a lower gain, the SCA is preferable. The TCA is the desired architecture for an average total gain and a large sensor capacitance. Moreover, when the power consumption is the key requirement and the maximum sensitivity is not the goal; the TCA works best due to its potential to decrease the power consumption. Full article
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Open AccessArticle
Modified Hermite Pulse-Based Wideband Communication for High-Speed Data Transfer in Wireless Sensor Applications
J. Low Power Electron. Appl. 2017, 7(4), 30; doi:10.3390/jlpea7040030 -
Abstract
With technological advances in the field of communication, the need for reliable high-speed data transfer is increasing. The deployment of large number of wireless sensors for remote monitoring and control and streaming of high definition video, voice and image data, etc. are imposing
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With technological advances in the field of communication, the need for reliable high-speed data transfer is increasing. The deployment of large number of wireless sensors for remote monitoring and control and streaming of high definition video, voice and image data, etc. are imposing a challenge to the existing network bandwidth allocation for reliable communication. Two novel schemes for ultra-wide band (UWB) communication technology have been proposed in this paper with the key objective of intensifying the data rate by taking advantage of the orthogonal properties of the modified Hermite pulse (MHP). In the first scheme, a composite pulse is transmitted and in the second scheme, a sequence of multi-order orthogonal pulses is transmitted in the place of a single UWB pulse. The MHP pulses exhibit a mutually orthogonal property between different ordered pulses and due to this property, simultaneous transmission is achieved without collision in the UWB system, resulting in an increase in transmission capacity or improved bit error rate. The proposed schemes for enhanced data rate will offer high volume data monitoring, assessment, and control of wireless devices without overburdening the network bandwidth and pave the way for new platforms for future high-speed wireless sensor applications. Full article
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Open AccessArticle
Energy-Efficient FPGA-Based Parallel Quasi-Stochastic Computing
J. Low Power Electron. Appl. 2017, 7(4), 29; doi:10.3390/jlpea7040029 -
Abstract
The high performance of FPGA (Field Programmable Gate Array) in image processing applications is justified by its flexible reconfigurability, its inherent parallel nature and the availability of a large amount of internal memories. Lately, the Stochastic Computing (SC) paradigm has been found to
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The high performance of FPGA (Field Programmable Gate Array) in image processing applications is justified by its flexible reconfigurability, its inherent parallel nature and the availability of a large amount of internal memories. Lately, the Stochastic Computing (SC) paradigm has been found to be significantly advantageous in certain application domains including image processing because of its lower hardware complexity and power consumption. However, its viability is deemed to be limited due to its serial bitstream processing and excessive run-time requirement for convergence. To address these issues, a novel approach is proposed in this work where an energy-efficient implementation of SC is accomplished by introducing fast-converging Quasi-Stochastic Number Generators (QSNGs) and parallel stochastic bitstream processing, which are well suited to leverage FPGA’s reconfigurability and abundant internal memory resources. The proposed approach has been tested on the Virtex-4 FPGA, and results have been compared with the serial and parallel implementations of conventional stochastic computation using the well-known SC edge detection and multiplication circuits. Results prove that by using this approach, execution time, as well as the power consumption are decreased by a factor of 3.5 and 4.5 for the edge detection circuit and multiplication circuit, respectively. Full article
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Open AccessArticle
A Low-Power Active Self-Interference Cancellation Technique for SAW-Less FDD and Full-Duplex Receivers
J. Low Power Electron. Appl. 2017, 7(4), 27; doi:10.3390/jlpea7040027 -
Abstract
An active self-interference (SI) cancellation technique for SAW-less receiver linearity improvement is proposed. The active canceler combines programmable gain and phase in a single stage and is co-designed with a highly-linear LNA, achieving low noise and low power. A cross-modulation mechanism of the
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An active self-interference (SI) cancellation technique for SAW-less receiver linearity improvement is proposed. The active canceler combines programmable gain and phase in a single stage and is co-designed with a highly-linear LNA, achieving low noise and low power. A cross-modulation mechanism of the SI canceler is identified and strongly suppressed thanks to the introduction of an internal resistive feedback, enabling high effective receiver IIP3. TX leakage of up to −4 dBm of power is suppressed by over 30 dB at the input of the LNA, with benefits for the entire receiver in terms of IIP3, IIP2, and reciprocal mixing. The design was done in a 40 nm CMOS technology. The system, including receiver and active SI canceler, consumes less than 25 mW of power. When the canceler is enabled, it has an NF of 3.9–4.6 dB between 1.7 and 2.4 GHz and an effective IIP3 greater than 35 dBm. Full article
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Open AccessArticle
Sleep Stage Classification by a Combination of Actigraphic and Heart Rate Signals
J. Low Power Electron. Appl. 2017, 7(4), 28; doi:10.3390/jlpea7040028 -
Abstract
Although heart rate variability and actigraphic data have been used for sleep-wake or sleep stage classifications, there are few studies on the combined use of them. Recent wearable sensors, however, equip both pulse wave and actigraphic sensors. This paper presents results on the
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Although heart rate variability and actigraphic data have been used for sleep-wake or sleep stage classifications, there are few studies on the combined use of them. Recent wearable sensors, however, equip both pulse wave and actigraphic sensors. This paper presents results on the performance of sleep stage classification by a combination of heart rate and actigraphic signals. We studied 40,643 epochs (length 3 min) of polysomnographic data in 289 subjects. A combined model, consisting of autonomic functional indices from heart rate variability and body movement indices derived from actigraphic data, discriminated non-rapid-eye-movement (REM) sleep from waking/REM sleep with 76.9% sensitivity, 74.5% specificity, 75.8% accuracy, and a Cohen’s kappa of 0.514. The combination was also useful for discriminating between REM sleep and waking at 77.2% sensitivity, 72.3% specificity, 74.5% accuracy, and a kappa of 0.491. Full article
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Open AccessArticle
Inkjet Printed Fully-Passive Body-Worn Wireless Sensors for Smart and Connected Community (SCC)
J. Low Power Electron. Appl. 2017, 7(4), 26; doi:10.3390/jlpea7040026 -
Abstract
Future Smart and Connected Communities (SCC) will utilize distributed sensors and embedded computing to seamlessly generate meaningful data that can assist individuals, communities, and society with interlocking physical, social, behavioral, economic, and infrastructural interaction. SCC will require newer technologies for seamless and unobtrusive
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Future Smart and Connected Communities (SCC) will utilize distributed sensors and embedded computing to seamlessly generate meaningful data that can assist individuals, communities, and society with interlocking physical, social, behavioral, economic, and infrastructural interaction. SCC will require newer technologies for seamless and unobtrusive sensing and computation in natural settings. This work presents a new technology for health monitoring with low-cost body-worn disposable fully passive electronic sensors, along with a scanner, smartphone app, and web-server for a complete smart sensor system framework. The novel wireless resistive analog passive (WRAP) sensors are printed using an inkjet printing (IJP) technique on paper with silver inks (Novacentrix Ag B40, sheet resistance of 21 mΩ/sq) and incorporate a few discrete surface mounted electronic components (overall thickness of <1 mm). These zero-power flexible sensors are powered through a wireless inductive link from a low-power scanner (500 mW during scanning burst of 100 ms) by amplitude modulation at the carrier signal of 13.56 MHz. While development of various WRAP sensors is ongoing, this paper describes development of a WRAP temperature sensor in detail as an illustration. The prototypes were functionally verified at various temperatures with energy consumption of as low as 50 mJ per scan. The data is analyzed with a smartphone app that computes severity (Events-of-Interest, or EoI) using a real-time algorithm. The severity can then be anonymously shared with a custom web-server, and visualized either in temporal or spatial domains. This research aims to reduce ER visits of patients by enabling self-monitoring, thereby improving community health for SSC. Full article
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Open AccessArticle
Evaluating the Impact of Max Transition Constraint Variations on Power Reduction Capabilities in Cell-Based Designs
J. Low Power Electron. Appl. 2017, 7(4), 25; doi:10.3390/jlpea7040025 -
Abstract
Power optimization is a very important and challenging step in the physical design flow, and it is a critical success factor of an application-specific integrated circuit (ASIC) chip. Many techniques are used by the place and route (P&R) electronic design automation (EDA) tools
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Power optimization is a very important and challenging step in the physical design flow, and it is a critical success factor of an application-specific integrated circuit (ASIC) chip. Many techniques are used by the place and route (P&R) electronic design automation (EDA) tools to meet the power requirement. In this paper, we will evaluate, independently from the library file, the impact of redefining the max transition constraint (MTC) before the power optimization phase, and we will study the impact of over-constraining or under-constraining a design on power in order to find the best trade-off between design constraining and power optimization. Experimental results showed that power optimization depends on the applied MTC and that the MTC value corresponding to the best power reduction results is different from the default MTC. By using a new MTC definition method on several designs, we found that the power gain between the default methodology and the new one reaches 2.34%. Full article
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Open AccessArticle
Ultra-Low Power, Process-Tolerant 10T (PT10T) SRAM with Improved Read/Write Ability for Internet of Things (IoT) Applications
J. Low Power Electron. Appl. 2017, 7(3), 24; doi:10.3390/jlpea7030024 -
Abstract
In this paper, an ultra-low power (ULP) 10T static random access memory (SRAM) is presented for Internet of Things (IoT) applications, which operates at sub-threshold voltage. The proposed SRAM has the tendency to operate at low supply voltages with high static and dynamic
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In this paper, an ultra-low power (ULP) 10T static random access memory (SRAM) is presented for Internet of Things (IoT) applications, which operates at sub-threshold voltage. The proposed SRAM has the tendency to operate at low supply voltages with high static and dynamic noise margins. The IoT application requires battery-enabled low leakage memory architecture in a subthreshold regime. Therefore, to improve leakage power consumption and provide better cell stability, a power-gated robust 10T SRAM is presented in this paper. The proposed cell uses a power-gated p-MOS transistor to reduce the leakage power or static power in standby mode. Moreover, due to the stacking of n-MOS transistors in 10T SRAM latch and by separating the read path from the 10T SRAM latch, the static and dynamic noise margins in read and write operations has shown significant tolerance w.r.t. the variations in device process, voltage, and temperature (PVT) values. The proposed SRAM shows significantly improved performance in terms of leakage power, read static noise margin (RSNM), write static noise margin (WSNM), write ability or write trip point (WTP), read–write energy, and dynamic read margin (DRM). Furthermore, these parameters of the proposed cell are observed at 8-Kilo bit (Kb) SRAM and compared with existing SRAM architectures. From the Monte Carlo simulation results, it is observed that the leakage power of a proposed low threshold voltage-LVT 10T SRAM is reduced by 98.76%, 98.6%, 6.7%, and 98.2% as compared to the LVT C6T, RD8T, LP9T, and ST10T SRAM, respectively, at 0.3V VDD. Additionally, in the proposed 10T SRAM, parameters such as RSNM, WSNM, WTP, and DRM are improved by 3×, 2×, 1.11×, and 1.32×, respectively, as compared to C6T SRAM. Similarly, the proposed 10T SRAM shows an improvement of 1.48×, 1.25×, and 1.1× in RSNM, WSNM, and WTP, respectively, in the parameters as compared to RD8T SRAM at 0.3 V VDD. Full article
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Open AccessArticle
DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability
J. Low Power Electron. Appl. 2017, 7(3), 23; doi:10.3390/jlpea7030023 -
Abstract
To enable the design of large capacity memory structures, novel memory technologies such as non-volatile memory (NVM) and novel fabrication approaches, e.g., 3D stacking and multi-level cell (MLC) design have been explored. The existing modeling tools, however, cover only a few memory technologies,
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To enable the design of large capacity memory structures, novel memory technologies such as non-volatile memory (NVM) and novel fabrication approaches, e.g., 3D stacking and multi-level cell (MLC) design have been explored. The existing modeling tools, however, cover only a few memory technologies, technology nodes and fabrication approaches. We present DESTINY, a tool for modeling 2D/3D memories designed using SRAM, resistive RAM (ReRAM), spin transfer torque RAM (STT-RAM), phase change RAM (PCM) and embedded DRAM (eDRAM) and 2D memories designed using spin orbit torque RAM (SOT-RAM), domain wall memory (DWM) and Flash memory. In addition to single-level cell (SLC) designs for all of these memories, DESTINY also supports modeling MLC designs for NVMs. We have extensively validated DESTINY against commercial and research prototypes of these memories. DESTINY is very useful for performing design-space exploration across several dimensions, such as optimizing for a target (e.g., latency, area or energy-delay product) for a given memory technology, choosing the suitable memory technology or fabrication method (i.e., 2D v/s 3D) for a given optimization target, etc. We believe that DESTINY will boost studies of next-generation memory architectures used in systems ranging from mobile devices to extreme-scale supercomputers. The latest source-code of DESTINY is available from the following git repository: https://bitbucket.org/sparshmittal/destinyv2. Full article
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Open AccessArticle
Review and Comparison of Clock Jitter Noise Reduction Techniques for Lowpass Continuous-Time Delta-Sigma Modulators
J. Low Power Electron. Appl. 2017, 7(3), 22; doi:10.3390/jlpea7030022 -
Abstract
It is well known that continuous-time Delta-Sigma modulators are very sensitive to clock jitter effects. In literature, a number of techniques have been proposed to cope with them. In this brief, we present a detailed review and comparison of the reported techniques. While
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It is well known that continuous-time Delta-Sigma modulators are very sensitive to clock jitter effects. In literature, a number of techniques have been proposed to cope with them. In this brief, we present a detailed review and comparison of the reported techniques. While the effectiveness to reduce clock jitter effects may be of most importance in this comparison, we also consider other performance metrics such as circuit complexity and overhead to implement the technique, power consumption overhead of technique, synthesis complexity incurred in system-level design, extensibility of the technique from single-bit to multi-bit operation, and robustness to process variation. When clock jitter is relatively large, the fixed-width pulse feedback technique is most effective to reduce clock jitter effects among all techniques at high sampling frequency, while switched-capacitor-resistor and switched-shaped current techniques have best performance at medium frequency or below. Full article
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Open AccessArticle
Models and Techniques for Temperature Robust Systems on a Reconfigurable Platform
J. Low Power Electron. Appl. 2017, 7(3), 21; doi:10.3390/jlpea7030021 -
Abstract
This paper investigates the variability of various circuits and systems over temperature and presents several methods to improve their performance over temperature. The work demonstrates use of large scale reconfigurable System-On-Chip (SOC) for reducing the variability of circuits and systems compiled on a
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This paper investigates the variability of various circuits and systems over temperature and presents several methods to improve their performance over temperature. The work demonstrates use of large scale reconfigurable System-On-Chip (SOC) for reducing the variability of circuits and systems compiled on a Floating Gate (FG) based Field Programmable Analog Array (FPAA). Temperature dependencies of circuits are modeled using an open-source simulator built in the Scilab/XCOS environment and the results are compared with measurement data obtained from the FPAA. This comparison gives further insight into the temperature dependence of various circuits and signal processing systems and allows us to compensate as well as predict their behavior. Also, the work presents several different current and voltage references that could help in reducing the variability caused due to changes in temperature. These references are standard blocks in the Scilab/Xcos environment that could be easily compiled on the FPAA. An FG based current reference is then used for biasing a 12×1 Vector Matrix Multiplication (VMM) circuit and a second order GmC bandpass filter to demonstrate the compilation and usage of these voltage/current reference in a reconfigurable fabric. The large scale FG FPAA presented here is fabricated in a 350 nm CMOS process. Full article
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Open AccessArticle
Ultra-Low Power Consuming Direct Radiation Sensors Based on Floating Gate Structures
J. Low Power Electron. Appl. 2017, 7(3), 20; doi:10.3390/jlpea7030020 -
Abstract
In this paper, we report on ultra-low power consuming single poly floating gate direct radiation sensors. The developed devices are intended for total ionizing dose (TID) measurements and fabricated in a standard CMOS process flow. Sensor design and operation is discussed in detail.
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In this paper, we report on ultra-low power consuming single poly floating gate direct radiation sensors. The developed devices are intended for total ionizing dose (TID) measurements and fabricated in a standard CMOS process flow. Sensor design and operation is discussed in detail. Original array sensors were suggested and fabricated that allowed high statistical significance of the radiation measurements and radiation imaging functions. Single sensors and array sensors were analyzed in combination with the specially developed test structures. This allowed insight into the physics of sensor operations and exclusion of the phenomena related to material degradation under irradiation in the interpretation of the measurement results. Response of the developed sensors to various sources of ionizing radiation (Gamma, X-ray, UV, energetic ions) was investigated. The optimal design of sensor for implementation in dosimetry systems was suggested. The roadmap for future improvement of sensor performance is suggested. Full article
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Open AccessArticle
Characterization of an ISFET with Built-in Calibration Registers through Segmented Eight-Bit Binary Search in Three-Point Algorithm Using FPGA
J. Low Power Electron. Appl. 2017, 7(3), 19; doi:10.3390/jlpea7030019 -
Abstract
Sensors play the most important role in observing changes in an environment they are a part. They detect even the smallest changes and send the information to other electronic devices. Making sure that these sensors provide an accurate output is equally crucial, as
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Sensors play the most important role in observing changes in an environment they are a part. They detect even the smallest changes and send the information to other electronic devices. Making sure that these sensors provide an accurate output is equally crucial, as the data it measures and collects are used for analysis. Until now, calibrating sensors has been done manually by following a sequence of procedures, and is usually performed on-site or in a laboratory prior to deployment. To eliminate the manual procedure in the calibration (at the very least), an ion-sensitive field-effect transistor (ISFET) with a built-in calibration registers circuit was created through segmented eight-bit binary search in a three-point algorithm using a field-programmable gate array (FPGA). The circuit was created using a three-point calibration algorithm and three standard buffers (pH 4, pH 7, and pH 10). The block diagram, schematic diagram, and the number of logic gates were derived after synthesizing the Verilog program in Xilinx/FPGA. An average of 0.30% error was computed to prove the reliability of the created circuit using FPGA. Having an ISFET with built-in calibration registers will alleviate the work of experts in performing calibrations. This would follow the plug and play standard, hence its being a calibration-ready ISFET device. With this feature, it could be used as a pH level meter or a remote sensor node in several applications. Full article
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Open AccessEditorial
A Summary of the Special Issue “Emerging Network-on-Chip Architectures for Low Power Embedded Systems”
J. Low Power Electron. Appl. 2017, 7(3), 18; doi:10.3390/jlpea7030018 -
Abstract
The International Technology Roadmap for Semiconductors [1] foresees that the number of processing elements that will be integrated into a system-on-chip will be on the order of thousands by 2020.[...] Full article
Open AccessArticle
Starting Framework for Analog Numerical Analysis for Energy-Efficient Computing
J. Low Power Electron. Appl. 2017, 7(3), 17; doi:10.3390/jlpea7030017 -
Abstract
The focus of this work is to develop a starting framework for analog numerical analysis and related algorithm questions. Digital computation is enabled by a framework developed over the last 80 years. Having an analog framework enables wider capability while giving the designer
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The focus of this work is to develop a starting framework for analog numerical analysis and related algorithm questions. Digital computation is enabled by a framework developed over the last 80 years. Having an analog framework enables wider capability while giving the designer tools to make reasonable choices. Analog numerical analysis concerns computation on physical structures utilizing the real-valued representations of that physical system. This work starts the conversation of analog numerical analysis, including exploring the relevancy and need for this framework. A complexity framework based on computational strengths and weaknesses builds from addressing analog and digital numerical precision, as well as addresses analog and digital error propagation due to computation. The complimentary analog and digital computational techniques enable wider computational capabilities. Full article
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Open AccessArticle
Flexible, Scalable and Energy Efficient Bio-Signals Processing on the PULP Platform: A Case Study on Seizure Detection
J. Low Power Electron. Appl. 2017, 7(2), 16; doi:10.3390/jlpea7020016 -
Abstract
Ultra-low power operation and extreme energy efficiency are strong requirements for a number of high-growth application areas requiring near-sensor processing, including elaboration of biosignals. Parallel near-threshold computing is emerging as an approach to achieve significant improvements in energy efficiency while overcoming the performance
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Ultra-low power operation and extreme energy efficiency are strong requirements for a number of high-growth application areas requiring near-sensor processing, including elaboration of biosignals. Parallel near-threshold computing is emerging as an approach to achieve significant improvements in energy efficiency while overcoming the performance degradation typical of low-voltage operations. In this paper, we demonstrate the capabilities of the PULP (Parallel Ultra-Low Power) platform on an algorithm for seizure detection, representative of a wide range of EEG signal processing applications. Starting from the 28-nm FD-SOI (Fully Depleted Silicon On Insulator) technology implementation of the third embodiment of the PULP architecture, we analyze the energy-efficient implementation of the seizure detection algorithm on PULP. The proposed parallel implementation exploits the dynamic voltage and frequency scaling capabilities, as well as the embedded power knobs of the PULP platform, reducing energy consumption for a seizure detection by up to 10× with respect to a sequential implementation at the nominal supply voltage and by 4.2× with respect to a sequential implementation with voltage scaling. Moreover, we analyze the trans-precision optimization of the algorithm on PULP, by means of a hybrid fixed- and floating-point implementation. This approach reduces the energy consumption by up to 43% with respect to the plain fixed-point and floating-point implementations, leveraging the requirements in terms of the precision of the kernels composing the processing chain to improve energy efficiency. Thanks to the proposed architecture and system-level approach for optimization, we demonstrate that PULP reduces energy consumption by up to 140× with respect to commercial low-power microcontrollers, being able to satisfy the real-time constraints typical of bio-medical applications, breaking the barrier of microwatts for a 50-ms complete seizure detection and a few milliwatts for a 5-ms detection latency on a fully-programmable architecture. Full article
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Open AccessArticle
Predictive Direct Torque Control Application-Specific Integrated Circuit of an Induction Motor Drive with a Fuzzy Controller
J. Low Power Electron. Appl. 2017, 7(2), 15; doi:10.3390/jlpea7020015 -
Abstract
This paper proposes a modified predictive direct torque control (PDTC) application-specific integrated circuit (ASIC) of a motor drive with a fuzzy controller for eliminating sampling and calculating delay times in hysteresis controllers. These delay times degrade the control quality and increase both torque
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This paper proposes a modified predictive direct torque control (PDTC) application-specific integrated circuit (ASIC) of a motor drive with a fuzzy controller for eliminating sampling and calculating delay times in hysteresis controllers. These delay times degrade the control quality and increase both torque and flux ripples in a motor drive. The proposed fuzzy PDTC ASIC calculates the stator’s magnetic flux and torque by detecting the three-phase current, three-phase voltage, and rotor speed, and eliminates the ripples in the torque and flux by using a fuzzy controller and predictive scheme. The Verilog hardware description language was used to implement the hardware architecture, and the ASIC was fabricated by the Taiwan Semiconductor Manufacturing Company through a 0.18-μm 1P6M CMOS process that involved a cell-based design method. The measurements revealed that the proposed fuzzy PDTC ASIC of the three-phase induction motor yielded a test coverage of 96.03%, fault coverage of 95.06%, chip area of 1.81 × 1.81 mm2, and power consumption of 296 mW, at an operating frequency of 50 MHz and a supply voltage of 1.8 V. Full article
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