J. Low Power Electron. Appl.2015, 5(3), 151-164; doi:10.3390/jlpea5030151 - published 25 June 2015 Show/Hide Abstract
Abstract: This paper proposes a review of several circuits for communication and wireless sensing applications implemented on cellulose-based materials. These circuits have been developed during the last years exploiting the adhesive copper laminate method. Such a technique relies on a copper adhesive tape that is shaped by a photo-lithographic process and then transferred to the hosting substrate (i.e., paper) by means of a sacrificial layer. The presented circuits span from UHF oscillators to a mixer working at 24 GHz and constitute an almost complete set of building blocks that can be applied to a huge variety communication apparatuses. Each circuit is validated experimentally showing performance comparable with the state-of-the-art. This paper demonstrates that circuits on cellulose are capable of operating at record frequencies and that ultra- low cost, green i.e., recyclable and biodegradable) materials can be a viable solution to realize high frequency hardware for the upcoming Internet of Things (IoT) era.
J. Low Power Electron. Appl.2015, 5(2), 130-150; doi:10.3390/jlpea5020130 - published 23 June 2015 Show/Hide Abstract
Abstract: The pursuit of continuous scaling of electronic devices in the semiconductor industry has led to two unintended but significant outcomes: a rapid increase in susceptibility to radiation induced errors, and an overall rise in power consumption. Operating under low voltage to reduce power only aggravates radiation related reliability issues. The proposed “SEU Hardening Incorporating Extreme Low Power Bitcell Design” (SHIELD) addresses these two major concerns simultaneously. It is based on the concept of gating the conventional cross-coupled inverters while introducing a novel “cut-off” network. This creates redundant storage nodes and eliminates the internal feedback loop during radiation particle impact. The SHIELD bitcell tolerates upsets with charge deposits over 1 pC. Simulations confirm its advantages in terms of leakage power, with more than twofold lower leakage currents than previous solutions when operated at a 700mV supply voltage in a 65 nm process. To validate the bitcell’s robustness, several test cases and special concerns, including multiple node upsets (MNU) and half-select, are examined.
J. Low Power Electron. Appl.2015, 5(2), 116-129; doi:10.3390/jlpea5020116 - published 25 May 2015 Show/Hide Abstract
Abstract: In this study, we demonstrate near-0.1 V minimum operating voltage of a low-variability Silicon on Thin Buried Oxide (SOTB) process for one million logic gates on silicon. Low process variability is required to obtain higher energy efficiency during ultra-low-voltage operation with steeper subthreshold slope transistors. In this study, we verify the decrease in operating voltage of logic circuits via a variability-suppressed SOTB process. In our measurement results with test chips fabricated in 65-nm SOTB and bulk processes, the operating voltage at which the first failure is observed was lowered from 0.2 to 0.125 V by introducing a low-variability SOTB process. Even at 0.115 V, over 40% yield can be expected as per our measurement results on SOTB test chips.
J. Low Power Electron. Appl.2015, 5(2), 101-115; doi:10.3390/jlpea5020101 - published 21 May 2015 Show/Hide Abstract
Abstract: In this paper, we analyze the variability of III-V homojunction tunnel FET (TFET) and FinFET devices and 32-bit carry-lookahead adder (CLA) circuit operating in near-threshold region. The impacts of the most severe intrinsic device variations including work function variation (WFV) and fin line-edge roughness (fin LER) on TFET and FinFET device Ion, Ioff, Cg, 32-bit CLA delay and power-delay product (PDP) are investigated and compared using 3D atomistic TCAD mixed-mode Monte-Carlo simulations and HSPICE simulations with look-up table based Verilog-A models calibrated with TCAD simulation results. The results indicate that WFV and fin LER have different impacts on device Ion and Ioff. Besides, at low operating voltage (<0.3 V), the CLA circuit delay and power-delay product (PDP) of TFET are significantly better than FinFET due to its better Ion and Cg,ave and their smaller variability. However, the leakage power of TFET CLA is larger than FinFET CLA due to the worse Ioff variability of TFET devices.
J. Low Power Electron. Appl.2015, 5(2), 81-100; doi:10.3390/jlpea5020081 - published 18 May 2015 Show/Hide Abstract
Abstract: This paper develops an ultra-low power asynchronous circuit design methodology, called Multi-Threshold NULL Convention Logic (MTNCL), also known as Sleep Convention Logic (SCL), which combines Multi-Threshold CMOS (MTCMOS) with NULL Convention Logic (NCL), to yield significant power reduction without any of the drawbacks of applying MTCMOS to synchronous circuits. In contrast to other power reduction techniques that usually result in large area overhead, MTNCL circuits are actually smaller than their original NCL versions. MTNCL utilizes high-Vttransistors to gate power and ground of a low-Vtlogic block to provide for both fast switching and very low leakage power when idle. To demonstrate the advantages of MTNCL, a number of 32-bit IEEE single-precision floating-point co-processors were designed for comparison using the 1.2 V IBM 8RF-LM 130 nm CMOS process: original NCL, MTNCL with just combinational logic (C/L) slept, Bit-Wise MTNCL (BWMTNCL), MTNCL with C/L and completion logic slept, MTNCL with C/L, completion logic, and registers slept, MTNCL with Safe Sleep architecture, and synchronous MTCMOS. These designs are compared in terms of throughput, area, dynamic energy, and idle power, showing the tradeoffs between the various MTNCL architectures, and that the best MTNCL design is much better than the original NCL design in all aspects, and much better than the synchronous MTCMOS design in terms of area, energy per operation, and idle power, although the synchronous design can operate faster.
J. Low Power Electron. Appl.2015, 5(2), 69-80; doi:10.3390/jlpea5020069 - published 29 April 2015 Show/Hide Abstract
Abstract: This work presents an analysis about the influence of the gate and source/drain underlap length (LUL) on UTBB FDSOI (UltraThin-Body-and-Buried-oxide Fully-Depleted-Silicon-On-Insulator) devices operating in conventional (VB = 0 V), dynamic threshold (DT, VB = VG), and the enhanced DT (eDT, VB = kVG) configurations, focusing on low power applications. It is shown that the underlap devices present a lower off-state current (IOFF at VG = 0 V), lower subthreshold swing (S), lower gate-induced drain leakage (GIDL), higher transconductance over drain current (gm/ID) ratio and higher intrinsic voltage gain (|AV|) due to their longer effective channel length in weak inversion and lower lateral electric field, while the eDT mode presents higher on-state current (ION) with the same IOFF, lower S, higher maximum transconductance (gmmax), lower threshold voltage (VT), higher gm/ID ratio and higher |AV| due to the dynamically reduced threshold voltage and stronger transversal electric field.