J. Low Power Electron. Appl.2016, 6(2), 8; doi:10.3390/jlpea6020008 - published 24 May 2016 Show/Hide Abstract
Abstract: We present an ultra-low power (ULP) 1 KB SRAM macro for Internet of Things (IoT) battery-less systems-on-chip (SoCs) operating under varying energy harvesting conditions. The unique combination of features within this array allows battery-less SoCs to retain important information for a significantly longer period of time when energy harvesting conditions are poor. The array uses 8T high-threshold (high-VT) static random access memory (SRAM) cells with word line boosting to eliminate write failures coupled with a read-before-write scheme to address read-disturb in half-selected cells. Due to the reduced on current in high-VT devices, read word line boosting is implemented to improve the drive strength of the read buffer, and to eliminate read failures. Leakage currents through the unselected cells during a read operation is addressed by boosting the footer virtual VSS (VVSS) of the read port to the supply voltage (VDD). To reduce the power consumption of instruction memories in battery-less SoCs, two features were utilized in this array: a read burst mode is used when reading consecutive addresses to reduce the read energy, and instructions with higher percentages of “1” data are defined since reading a “1” is less costly than reading a “0” in 8T cells. The proposed array can operate at a wide range of supply voltages (350–700 mV) and has two ULP modes: standby with retention (1.5 pW/bit) and shutdown without retention (0.13 pW/bit). Aggressive power gating of all peripherals during the standby state reduces the array power consumption down to 12.29 nW/KB at 320 mV with data retention. Compared to previously published 8T arrays, the proposed design provides the lowest standby power. The complete shutdown of the array allows further reduction down to 1.09 nW/KB and is suitable for reducing the power consumption of data memories in battery-less SoCs. The measured results from a commercial 130 nm chip show that the proposed array consumes a minimum of 6.24 pJ/access with a 17.16 nW standby power at 400 mV. The read burst mode allows up to 22% reduction in energy/access at 400 mV.
J. Low Power Electron. Appl.2016, 6(2), 7; doi:10.3390/jlpea6020007 - published 16 May 2016 Show/Hide Abstract
Abstract: We propose a fully on-chip clock-source system in which an ultra-low-power diode-based temperature-uncompensated oscillator (OSCdiode) serves as the main clock source and frequency locks to a higher-power temperature-compensated oscillator (OSCcmp) that is disabled after each locking event to save power. The locking allows the stability of the uncompensated oscillator to stay within the stability bound of the compensated design. This paper demonstrates the functionality of a locking controller that uses a periodic (counter-based) scheme implemented on-chip and a prediction (temperature-drift-based) scheme. The flexible clock source platform is validated in a 130 nm CMOS technology. In the demonstrated system, it achieves an effective average temperature stability of 7 ppm/°C in the human body temperature range from 20 °C to 40 °C with a power consumption of 36 nW at 0.7 V. It achieves a frequency range of 12 kHz to 150 kHz at 0.7 V.
J. Low Power Electron. Appl.2016, 6(2), 6; doi:10.3390/jlpea6020006 - published 6 May 2016 Show/Hide Abstract
Abstract: Observations of peak and average currents are important for designed circuits, as faulty circuits have abnormal peaks and average currents. Using current bounds to detect faulty chips is a comparatively innovative idea, and many advanced schemes without them use it as a component in statistical outlier analysis. However, these previous research works have focused on the discussion of the testing impact without a proposed method to define reference current bounds to find faulty chips. A software framework is proposed to synthesize high-performance, power-performance optimized, noise-immune, and low-power circuits with current-bound estimations for testing. This framework offers a rapid methodology to quickly screen potential faulty chips by using the peak and average current bounds for different purposed circuits. The proposed estimation technique generates suitable reference current bounds from transistor threshold voltage and size adjustments. The SPICE-level simulation leads to the most accurate estimations. However, such simulations are not feasible for a large digital circuit. Hence, this work proposes constructing a feasible gate-level software framework for large digital circuits that will serve all of simulation purposes. In comparison with transistor-level Nanosim simulations, the proposed gate-level simulation framework has a margin of error of less than 2% in the peak current, and the computation time is 334 times faster.
J. Low Power Electron. Appl.2016, 6(2), 5; doi:10.3390/jlpea6020005 - published 28 April 2016 Show/Hide Abstract
Abstract: With increasing core-count, the cache demand of modern processors has also increased. However, due to strict area/power budgets and presence of poor data-locality workloads, blindly scaling cache capacity is both infeasible and ineffective. Cache bypassing is a promising technique to increase effective cache capacity without incurring power/area costs of a larger sized cache. However, injudicious use of cache bypassing can lead to bandwidth congestion and increased miss-rate and hence, intelligent techniques are required to harness its full potential. This paper presents a survey of cache bypassing techniques for CPUs, GPUs and CPU-GPU heterogeneous systems, and for caches designed with SRAM, non-volatile memory (NVM) and die-stacked DRAM. By classifying the techniques based on key parameters, it underscores their differences and similarities. We hope that this paper will provide insights into cache bypassing techniques and associated tradeoffs and will be useful for computer architects, system designers and other researchers.
J. Low Power Electron. Appl.2016, 6(1), 4; doi:10.3390/jlpea6010004 - published 11 March 2016 Show/Hide Abstract
Abstract: An ultra-low-voltage low-power switched-capacitor (SC) delta-sigma (ΔΣ) modulator running at a supply voltage as low as 300 mV is presented for biomedical implant devices, e.g., cardiac pacemakers. To reduce the supply voltage, an inverter-based amplifier is used in the integrators, whose DC gain and gain-bandwidth (GBW) are boosted by a simple current-mirror output stage. The full input-feedforward loop topology offers low integrators internal swing, supporting ultra-low-voltage operation. To demonstrate the concept, a second-order loop topology was chosen. The entire modulator operates reliably against process, voltage and temperature (PVT) variations from a 300 mV ± 10% supply voltage only, while the switches are driven by a charge pump clock boosting scheme. Designed in a 65 nm CMOS technology and clocked at 256 kHz, the simulation results show that the modulator can achieve a 64.4 dB signal-to-noise ratio (SNR) and a 60.7 dB signal-to-noise and distortion ratio (SNDR) over a 1.0 kHz signal bandwidth while consuming 0.85 μW of power.
J. Low Power Electron. Appl.2016, 6(1), 3; doi:10.3390/jlpea6010003 - published 4 February 2016 Show/Hide Abstract
Abstract: This paper presents an analog-digital hardware-software co-design environment for simulating and programming reconfigurable systems. The tool simulates, designs, as well as enables experimental measurements after compiling to configurable systems in the same integrated design tool framework. High level software in Scilab/Xcos (open-source programs similar to MATLAB/Simulink) that converts the high-level block description by the user to blif format (sci2blif), which acts as an input to the modified VPR tool, including the code v p r 2 s w c s , encoding the specific platform through specific architecture files, resulting in a targetable switch list on the resulting configurable analog–digital system. The resulting tool uses an analog and mixed-signal library of components, enabling users and future researchers access to the basic analog operations/computations that are possible.