J. Low Power Electron. Appl.2016, 6(3), 16; doi:10.3390/jlpea6030016 - published 24 August 2016 Show/Hide Abstract
Abstract: Static Random Access Memory (SRAM) has recently been developed into a physical unclonable function (PUF) for generating chip-unique signatures for hardware cryptography. The most compelling issue in designing a good SRAM-based PUF (SPUF) is that while maximizing the mismatches between the transistors in the cross-coupled inverters improves the quality of the SPUF, this ironically also gives rise to increased memory read/write failures. For this reason, the memory cells of existing SPUFs cannot be reused as storage elements, which increases the overheads of cryptographic system where long signatures and high-density storage are both required. This paper presents a novel design methodology for dual-mode SRAM cell optimization. The design conflicts are resolved by using word-line voltage modulation, dynamic voltage scaling, negative bit-line and adaptive body bias techniques to compensate for reliability degradation due to transistor downsizing. The augmented circuit-level techniques expand the design space to achieve a good solution to fulfill several otherwise contradicting key design qualities for both modes of operation, as evinced by our statistical analysis and simulation results based on complementary metal–oxide–semiconductor (CMOS) 45 nm bulk Predictive Technology Model.
J. Low Power Electron. Appl.2016, 6(3), 15; doi:10.3390/jlpea6030015 - published 12 August 2016 Show/Hide Abstract
Abstract: This paper describes the stochastic-based Spin-Programmable Gate Array (SPGA), an innovative architecture attempting to exploit the stochastic switching behavior newly found in emerging spintronic devices for reconfigurable computing. While many recently studies have investigated using Spin Transfer Torque Memory (STTM) devices to replace configuration memory in field programmable gate arrays (FPGAs), our study, for the first time, attempts to use the quantum-induced stochastic property exhibited by spintronic devices directly for reconfiguration and logic computation. Specifically, the SPGA was designed from scratch for high performance, routability, and ease-of-use. It supports variable-granularity multiple-input-multiple-output (MIMO) logic blocks and variable-length bypassing interconnects with a symmetrical structure. Due to its unconventional architectural features, the SPGA requires several major modifications to be made in the standard VPR placement/routing CAD flow, which include a new technology mapping algorithm based on computing (k, l)-cut, a new placement algorithm, and a modified delay-based routing procedure.Previous studies have shown that, simply replacing reconfiguration memory bits with spintronic devices, the conventional 2D island-style FPGA architecture can achieve approximately 5 times area savings, 2 times speedup and 1.6 times power savings. Our mixed-mode simulation results have shown that, with FPGA architecture innovations, on average, a SPGA can further achieve more than 10 times improvement in logic density, about 5 times improvement in average net delay, and about 5 times improvement in the critical-path delay for the largest 12 MCNC benchmark circuits over an island-style baseline FPGA with spintronic configuration bits.
J. Low Power Electron. Appl.2016, 6(3), 14; doi:10.3390/jlpea6030014 - published 28 July 2016 Show/Hide Abstract
Abstract: We present a novel remote test system, an integrated remote testing system requiring minimal technology support overhead, enabled by configurable analog–digital Integrated Circuits (IC) to create a simple interface for a wide range of experiments. Our remote test system requires no additional setup, resulting both from using highly configurable devices, as well as from the advancement of straight-forward digital interfaces (i.e., USB) for the resulting experimental system. The system overhead requirements require simple email handling, available over almost all network systems with no additional requirements. The system is empowered through large-scale Field Programmable Analog Array (FPAA) devices and Baseline Tool Framework (BTF), where we present a range of experimentally measured examples illustrating the range of user interfacing available for the remote user.
J. Low Power Electron. Appl.2016, 6(3), 13; doi:10.3390/jlpea6030013 - published 27 July 2016 Show/Hide Abstract
Abstract: This paper presents scaling of Floating-Gate (FG) devices, and the resulting implication to large-scale Field Programmable Analog Arrays (FPAA) systems. The properties of FG circuits and systems in one technology (e.g., 350 nm CMOS) are experimentally shown to roughly translate to FG circuits in scaled down processes in a way predictable through MOSFET physics concepts. Scaling FG devices results in higher frequency response, (e.g., FPAA fabric) as well as lower parasitic capacitance and lower power consumption. FPAA architectures, limited to 50–100 MHz frequency ranges could be envisioned to operate at 500 MHz–1 GHz for 130 nm line widths, and operate around 4 GHz for 40 nm line widths.
J. Low Power Electron. Appl.2016, 6(3), 12; doi:10.3390/jlpea6030012 - published 14 July 2016 Show/Hide Abstract
Abstract: Energy efficiency is a primary design goal for future green wireless communication technologies. Multiple-input multiple-output (MIMO) schemes have been proposed in the literature to improve the throughput of communication systems, and they are expected to play a prominent role in the upcoming fifth generation (5G) standard. This paper presents a novel, high-efficiency MIMO decoder based on the K-Best algorithm with lattice reduction. We have designed a novel hardware architecture for this decoder, which was implemented using 32 nm standard CMOS technology. Our results show that the proposed decoder can achieve on average a four-fold reduction in the power costs compared to recently published designs for 5G networks. The throughput of the design is 506 Mbits/s, which is comparable to existing designs.
J. Low Power Electron. Appl.2016, 6(3), 11; doi:10.3390/jlpea6030011 - published 23 June 2016 Show/Hide Abstract
Abstract: This paper presents an ultra-low swing level converter with integrated charge pumps that shows measured conversion in a 130-nm CMOS test chip from an input at a 145-mV swing to a 1.2-V output. Lowering the input allowable for a single-ended level converter supports energy harvesting systems that need to use very low voltages.