Open AccessCorrection
Correction: Alateeq, A. et al. Performance of the Soft-Charging Operation in Series of Step-Up Power Switched-Capacitor Converters. J. Low Power Electron. Appl. 2018, 8, 8
J. Low Power Electron. Appl. 2018, 8(2), 11; doi:10.3390/jlpea8020011 (registering DOI) -
Abstract
After publication of the research paper [1] (http://www.mdpi.com/2079-9268/8/1/8/htm), a confusion of the charge flow direction in Section 2 makes some analysis unclear and confusing [...] Full article
Open AccessArticle
An Ultra-Low Power 28 nm FD-SOI Low Noise Amplifier Based on Channel Aware Receiver System Analysis
J. Low Power Electron. Appl. 2018, 8(2), 10; doi:10.3390/jlpea8020010 -
Abstract
This study investigates the benefit of an optimal and energy-efficient reconfiguration technique for the design of channel-aware receiver aiming Internet of Things (IoT) applications. First, it demonstrates the interest for adaptive receivers based on an estimation of the received power and compares the
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This study investigates the benefit of an optimal and energy-efficient reconfiguration technique for the design of channel-aware receiver aiming Internet of Things (IoT) applications. First, it demonstrates the interest for adaptive receivers based on an estimation of the received power and compares the proposed channel-aware receiver with the State Of the Art. It is shown that the lifetime of the Wireless Sensor (WS) battery can be extended by a factor of five with the optimization of operating points of the tunable receiver while maintaining similar performances than industrial modules. The design of an Ultra-Low Power (ULP) inductorless Low Noise Amplifier (LNA), which fits the low power mode of the tunable receiver, is then optimized and described. The back-gate biasing of Fully Depleted Silicon-On-Insulator (FD-SOI) technology to lower the power consumption by more than 25% still maintaining performances is evaluated. The proposed LNA has been implemented in ST-Microelectronics 28 nm FD-SOI Technology, its active area is only 0.0015 mm2. The measured performances at 2.4 GHz exhibit more than 16 dB of voltage Gain (Gv), 7.3 dB of Noise Figure (NF), and a −16 dBm Input referred third-order Intercept Point (IIP3). The LNA consumes 300 µW from a 0.6 V supply. Full article
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Open AccessFeature PaperArticle
Opportunistic Design Margining for Area and Power Efficient Processor Pipelines in Real Time Applications
J. Low Power Electron. Appl. 2018, 8(2), 9; doi:10.3390/jlpea8020009 -
Abstract
The semiconductor industry is strategically focusing on automotive markets, and significant investment is targeted to addressing these markets. Runtime better-than-worst-case designs like Razor lead to massive timing errors upon breaching the critical operating point and have significant area overheads. As we scale to
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The semiconductor industry is strategically focusing on automotive markets, and significant investment is targeted to addressing these markets. Runtime better-than-worst-case designs like Razor lead to massive timing errors upon breaching the critical operating point and have significant area overheads. As we scale to higher-reliability automotive and industrial markets we need alternative techniques that will allow full extraction of the power benefits without sacrificing reliability. The proposed method utilizes positive slack available in the pipeline stages and re-distributes it to the preceding critical logic stage using Slack Balancing Flip-Flops (SBFFs). We use opportunistic under designing to get rid of the area, power and error correction overheads associated with the speculative hardware of runtime techniques. The proposed logic reshaping results in 12 percent and eight percent power and area savings respectively compared to the worst-case design approach. Compared to runtime better-than-worst-case designs, we get 51 percent and 10 percent power and area savings, respectively. In addition, the timing budgeting and timing correction using opportunistic slack eliminate critical operating point behavior, metastability issues and hold buffer overheads encountered in existing runtime resilience techniques. Full article
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Open AccessArticle
A Performance of the Soft-Charging Operation in Series of Step-Up Power Switched-Capacitor Converters
J. Low Power Electron. Appl. 2018, 8(1), 8; doi:10.3390/jlpea8010008 -
Abstract
Due to their high power density and appropriateness for small circuits integration, switched-capacitor (SC) converters have gotten more interests. Applying the soft-charging technique effectively eliminates the current transient that results in a higher power density and a higher fundamental efficiency. Achieving the complete
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Due to their high power density and appropriateness for small circuits integration, switched-capacitor (SC) converters have gotten more interests. Applying the soft-charging technique effectively eliminates the current transient that results in a higher power density and a higher fundamental efficiency. Achieving the complete soft-charging operation is impossible by using the conventional control diagram for any SC converter topology. In this paper, we proposed a split-phase control to achieve the complete soft-charging operation in a power switched-capacitor (PSC) converter. The proposed control diagram was designed for a 1-to-4 PSC converter (two-level of the PSC converter). The implemented split-phase diagram successfully controls eight switches to exhibit eight modes of operation. In addition to the current transient elimination, the complete soft-charging allows us to reduce capacitor sizes. However, reducing capacitor size negatively increases the output voltage ripple; hence, an output LC filter is needed. The complete soft-charging achievement accomplishes a 96% efficiency due to the lower output impedance and the dead time switching. LT-Spice software has been used to verify the proposed control and the results were compared with hard-charging and incomplete soft-charging operations. Full article
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Open AccessFeature PaperCommunication
An Efficient Connected Component Labeling Architecture for Embedded Systems
J. Low Power Electron. Appl. 2018, 8(1), 7; doi:10.3390/jlpea8010007 -
Abstract
Connected component analysis is one of the most fundamental steps used in several image processing systems. This technique allows for distinguishing and detecting different objects in images by assigning a unique label to all pixels that refer to the same object. Most of
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Connected component analysis is one of the most fundamental steps used in several image processing systems. This technique allows for distinguishing and detecting different objects in images by assigning a unique label to all pixels that refer to the same object. Most of the previous published algorithms have been designed for implementation by software. However, due to the large number of memory accesses and compare, lookup, and control operations when executed on a general-purpose processor, they do not satisfy the speed performance required by the next generation high performance computer vision systems. In this paper, we present the design of a new Connected Component Labeling hardware architecture suitable for high performance heterogeneous image processing of embedded designs. When implemented on a Zynq All Programmable-System on Chip (AP-SOC) 7045 chip, the proposed design allows a throughput rate higher of 220 Mpixels/s to be reached using less than 18,000 LUTs and 5000 FFs, dissipating about 620 μJ. Full article
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Open AccessReview
Multiple Input Energy Harvesting Systems for Autonomous IoT End-Nodes
J. Low Power Electron. Appl. 2018, 8(1), 6; doi:10.3390/jlpea8010006 -
Abstract
The Internet-of-Things (IoT) paradigm is under constant development and is being enabled by the latest research work from both industrial and academic communities. Among the many contributions in such diverse areas as sensor manufacturing, network protocols, and wireless communications, energy harvesting techniques stand
[...] Read more.
The Internet-of-Things (IoT) paradigm is under constant development and is being enabled by the latest research work from both industrial and academic communities. Among the many contributions in such diverse areas as sensor manufacturing, network protocols, and wireless communications, energy harvesting techniques stand out as a key enabling technology for the realization of batteryless IoT end-node systems. In this paper, we give an overview of the recent developments in circuit design for ultra-low power management units (PMUs), focusing mainly in the architectures and techniques required for energy harvesting from multiple heterogeneous sources. The paper starts by discussing a general structure for IoT end-nodes and the main characteristics of PMUs for energy harvesting. Then, an overview is given of different published works for multisource power harvesting, observing their main advantages and disadvantages and comparing their performance. Finally, some open areas of research in multisource harvesting are observed and relevant conclusions are given. Full article
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Open AccessFeature PaperArticle
The Advances, Challenges and Future Possibilities of Millimeter-Wave Chip-to-Chip Interconnections for Multi-Chip Systems
J. Low Power Electron. Appl. 2018, 8(1), 5; doi:10.3390/jlpea8010005 -
Abstract
With aggressive scaling of device geometries, density of manufacturing faults is expected to increase. Therefore, yield of complex Multi-Processor Systems-on-Chips (MP-SoCs) will decrease due to higher probability of manufacturing defects especially, in dies with large area. Therefore, disintegration of large SoCs into smaller
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With aggressive scaling of device geometries, density of manufacturing faults is expected to increase. Therefore, yield of complex Multi-Processor Systems-on-Chips (MP-SoCs) will decrease due to higher probability of manufacturing defects especially, in dies with large area. Therefore, disintegration of large SoCs into smaller chips called chiplets will improve yield and cost of complex platform-based systems. This will also provide functional flexibility, modular scalability as well as the capability to integrate heterogeneous architectures and technologies in a single unit. However, with scaling of the number of chiplets in such a system, the shared resources in the system such as the interconnection fabric and memory modules will become performance bottlenecks. Additionally, the integration of heterogeneous chiplets operating at different frequencies and voltages can be challenging. State-of-the-art inter-chip communication requires power-hungry high-speed I/O circuits and data transfer over long wired traces on substrates. This increases energy consumption and latency while decreasing data bandwidth for chip-to-chip communication. In this paper, we explore the advances and the challenges of interconnecting a multi-chip system with millimeter-wave (mm-wave) wireless interconnects from a variety of perspectives spanning multiple aspects of the wireless interconnection design. Our discussion on the recent advances include aspects such as interconnection topology, physical layer, Medium Access Control (MAC) and routing protocols. We also present some potential paradigm-shifting applications as well as complementary technologies of wireless inter-chip communications. Full article
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Open AccessEditorial
Acknowledgement to Reviewers of Journal of Low Power Electronics and Applications in 2017
J. Low Power Electron. Appl. 2018, 8(1), 4; doi:10.3390/jlpea8010004 -
Abstract
Peer review is an essential part in the publication process, ensuring that Journal of Low Power Electronics and Applications maintains high quality standards for its published papers [...] Full article
Open AccessArticle
Design of a Programmable Passive SoC for Biomedical Applications Using RFID ISO 15693/NFC5 Interface
J. Low Power Electron. Appl. 2018, 8(1), 3; doi:10.3390/jlpea8010003 -
Abstract
Low power, low cost inductively powered passive biotelemetry system involving fully customized RFID/NFC interface base SoC has gained popularity in the last decades. However, most of the SoCs developed are application specific and lacks either on-chip computational or sensor readout capability. In this
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Low power, low cost inductively powered passive biotelemetry system involving fully customized RFID/NFC interface base SoC has gained popularity in the last decades. However, most of the SoCs developed are application specific and lacks either on-chip computational or sensor readout capability. In this paper, we present design details of a programmable passive SoC in compliance with ISO 15693/NFC5 standard for biomedical applications. The integrated system consists of a 32-bit microcontroller, a sensor readout circuit, a 12-bit SAR type ADC, 16 kB RAM, 16 kB ROM and other digital peripherals. The design is implemented in a 0.18 μm CMOS technology and used a die area of 1.52 mm × 3.24 mm. The simulated maximum power consumption of the analog block is 592 μW. The number of external components required by the SoC is limited to an external memory device, sensors, antenna and some passive components. The external memory device contains the application specific firmware. Based on the application, the firmware can be modified accordingly. The SoC design is suitable for medical implants to measure physiological parameters like temperature, pressure or ECG. As an application example, the authors have proposed a bioimplant to measure arterial blood pressure for patients suffering from Peripheral Artery Disease (PAD). Full article
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Open AccessArticle
A Bond Graph Approach for the Modeling and Simulation of a Buck Converter
J. Low Power Electron. Appl. 2018, 8(1), 2; doi:10.3390/jlpea8010002 -
Abstract
This paper deals with the modeling of bond graph buck converter systems. The bond graph formalism, which represents a heterogeneous formalism for physical modeling, is used to design a sub-model of a power MOSFET and PiN diode switchers. These bond graph models are
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This paper deals with the modeling of bond graph buck converter systems. The bond graph formalism, which represents a heterogeneous formalism for physical modeling, is used to design a sub-model of a power MOSFET and PiN diode switchers. These bond graph models are based on the device’s electrical elements. The application of these models to a bond graph buck converter permit us to obtain an invariant causal structure when the switch devices change state. This paper shows the usefulness of the bond graph device’s modeling to simulate an implicit bond graph buck converter. Full article
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Open AccessArticle
SoC-Based Edge Computing Gateway in the Context of the Internet of Multimedia Things: Experimental Platform
J. Low Power Electron. Appl. 2018, 8(1), 1; doi:10.3390/jlpea8010001 -
Abstract
This paper presents an algorithm/architecture and Hardware/Software co-designs for implementing a digital edge computing layer on a Zynq platform in the context of the Internet of Multimedia Things (IoMT). Traditional cloud computing is no longer suitable for applications that require image processing due
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This paper presents an algorithm/architecture and Hardware/Software co-designs for implementing a digital edge computing layer on a Zynq platform in the context of the Internet of Multimedia Things (IoMT). Traditional cloud computing is no longer suitable for applications that require image processing due to cloud latency and privacy concerns. With edge computing, data are processed, analyzed, and encrypted very close to the device, which enable the ability to secure data and act rapidly on connected things. The proposed edge computing system is composed of a reconfigurable module to simultaneously compress and encrypt multiple images, along with wireless image transmission and display functionalities. A lightweight implementation of the proposed design is obtained by approximate computing of the discrete cosine transform (DCT) and by using a simple chaotic generator which greatly enhances the encryption efficiency. The deployed solution includes four configurations based on HW/SW partitioning in order to handle the compromise between execution time, area, and energy consumption. It was found with the experimental setup that by moving more components to hardware execution, a timing speedup of more than nine times could be achieved with a negligible amount of energy consumption. The power efficiency was then enhanced by a ratio of 7.7 times. Full article
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Open AccessArticle
A Low-Power CMOS Piezoelectric Transducer Based Energy Harvesting Circuit for Wearable Sensors for Medical Applications
J. Low Power Electron. Appl. 2017, 7(4), 33; doi:10.3390/jlpea7040033 -
Abstract
Piezoelectric vibration based energy harvesting systems have been widely utilized and researched as powering modules for various types of sensor systems due to their ease of integration and relatively high energy density compared to RF, thermal, and electrostatic based energy harvesting systems. In
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Piezoelectric vibration based energy harvesting systems have been widely utilized and researched as powering modules for various types of sensor systems due to their ease of integration and relatively high energy density compared to RF, thermal, and electrostatic based energy harvesting systems. In this paper, a low-power CMOS full-bridge rectifier is presented as a potential solution for an efficient energy harvesting system for piezoelectric transducers. The energy harvesting circuit consists of two n-channel MOSFETs (NMOS) and two p-channel MOSFETs (PMOS) devices implementing a full-bridge rectifier coupled with a switch control circuit based on a PMOS device driven by a comparator. With a load of 45 kΩ, the output rectifier voltage and the input piezoelectric transducer voltage are 694 mV and 703 mV, respectably, while the VOUT versus VIN conversion ratio is 98.7% with a PCE of 52.2%. The energy harvesting circuit has been designed using 130 nm standard CMOS process. Full article
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Open AccessArticle
Forwarding Path Limitation and Instruction Allocation for In-Order Processor with ALU Cascading
J. Low Power Electron. Appl. 2017, 7(4), 32; doi:10.3390/jlpea7040032 -
Abstract
Much research focuses on many-core processors, which possess a vast number of cores. Their area, energy consumption, and performance have a tendency to be proportional to the number of cores. It is better to utilize in-order (IO) execution for better area/energy efficiency. However,
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Much research focuses on many-core processors, which possess a vast number of cores. Their area, energy consumption, and performance have a tendency to be proportional to the number of cores. It is better to utilize in-order (IO) execution for better area/energy efficiency. However, expanding two-way IO to three-way IO offers very little improvement, since data dependency limits the effectiveness. In addition, if the core is changed from IO to out-of-order (OoO) execution to improve Instruction Per Cycle(IPC), area and energy consumption increases significantly. The combination of IO execution and Arithmetic Logic Unit(ALU) cascading is an effective solution to alleviate this problem. However, ALU cascading is implemented by complex bypass circuits because it requires a connection between all outputs and all inputs of all ALUs. The hardware complexity of the bypass circuits increases area, energy consumption, and delay. In this study, we proposed a mechanism that limits the number of the forwarding paths and allocates instructions to ALUs in accordance with the limited paths. This mechanism scales down bypass circuits to reduce the hardware complexity. Our evaluation results show that our proposed mechanism can reduce the area by 38.7%, the energy by 41.1%, and the delay by 23.2% with very little IPC loss on average, as compared with the conventional mechanism. Full article
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Open AccessArticle
Analysis of Sensitivity and Power Consumption of Chopping Techniques for Integrated Capacitive Sensor Interface Circuits
J. Low Power Electron. Appl. 2017, 7(4), 31; doi:10.3390/jlpea7040031 -
Abstract
In this paper, parameters related to the sensitivity of the interface circuits for capacitive sensors are determined. Both the input referred noise and capacitance of the input transistors are important for capacitive sensitivity. Chopping is an effective technique for signal conditioning circuits because
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In this paper, parameters related to the sensitivity of the interface circuits for capacitive sensors are determined. Both the input referred noise and capacitance of the input transistors are important for capacitive sensitivity. Chopping is an effective technique for signal conditioning circuits because of its capability of reducing circuit noise at low frequencies. The capacitive sensitivity and power consumption of various chopping techniques including the dual chopper amplifier (DCA), single chopper amplifier (SCA) and two-stage single chopper amplifier (TCA) are extracted for different values of total gain and sensor capacitance. The minimum sensitivity for each technique will be extracted based on the gain and sensor capacitance. It will be shown that designation of the amplifier and distribution of gain in the TCA and DCA are important for sensitivity. A design procedure for chopper amplifiers that illustrates the steps required to achieve either the best or the desired sensitivity while minimizing power consumption will be presented. It will be shown that for a small sensor capacitance and large total gain, the DCA has the best sensitivity, while for a large sensor capacitance and a lower gain, the SCA is preferable. The TCA is the desired architecture for an average total gain and a large sensor capacitance. Moreover, when the power consumption is the key requirement and the maximum sensitivity is not the goal; the TCA works best due to its potential to decrease the power consumption. Full article
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Open AccessArticle
Modified Hermite Pulse-Based Wideband Communication for High-Speed Data Transfer in Wireless Sensor Applications
J. Low Power Electron. Appl. 2017, 7(4), 30; doi:10.3390/jlpea7040030 -
Abstract
With technological advances in the field of communication, the need for reliable high-speed data transfer is increasing. The deployment of large number of wireless sensors for remote monitoring and control and streaming of high definition video, voice and image data, etc. are imposing
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With technological advances in the field of communication, the need for reliable high-speed data transfer is increasing. The deployment of large number of wireless sensors for remote monitoring and control and streaming of high definition video, voice and image data, etc. are imposing a challenge to the existing network bandwidth allocation for reliable communication. Two novel schemes for ultra-wide band (UWB) communication technology have been proposed in this paper with the key objective of intensifying the data rate by taking advantage of the orthogonal properties of the modified Hermite pulse (MHP). In the first scheme, a composite pulse is transmitted and in the second scheme, a sequence of multi-order orthogonal pulses is transmitted in the place of a single UWB pulse. The MHP pulses exhibit a mutually orthogonal property between different ordered pulses and due to this property, simultaneous transmission is achieved without collision in the UWB system, resulting in an increase in transmission capacity or improved bit error rate. The proposed schemes for enhanced data rate will offer high volume data monitoring, assessment, and control of wireless devices without overburdening the network bandwidth and pave the way for new platforms for future high-speed wireless sensor applications. Full article
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Open AccessArticle
Energy-Efficient FPGA-Based Parallel Quasi-Stochastic Computing
J. Low Power Electron. Appl. 2017, 7(4), 29; doi:10.3390/jlpea7040029 -
Abstract
The high performance of FPGA (Field Programmable Gate Array) in image processing applications is justified by its flexible reconfigurability, its inherent parallel nature and the availability of a large amount of internal memories. Lately, the Stochastic Computing (SC) paradigm has been found to
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The high performance of FPGA (Field Programmable Gate Array) in image processing applications is justified by its flexible reconfigurability, its inherent parallel nature and the availability of a large amount of internal memories. Lately, the Stochastic Computing (SC) paradigm has been found to be significantly advantageous in certain application domains including image processing because of its lower hardware complexity and power consumption. However, its viability is deemed to be limited due to its serial bitstream processing and excessive run-time requirement for convergence. To address these issues, a novel approach is proposed in this work where an energy-efficient implementation of SC is accomplished by introducing fast-converging Quasi-Stochastic Number Generators (QSNGs) and parallel stochastic bitstream processing, which are well suited to leverage FPGA’s reconfigurability and abundant internal memory resources. The proposed approach has been tested on the Virtex-4 FPGA, and results have been compared with the serial and parallel implementations of conventional stochastic computation using the well-known SC edge detection and multiplication circuits. Results prove that by using this approach, execution time, as well as the power consumption are decreased by a factor of 3.5 and 4.5 for the edge detection circuit and multiplication circuit, respectively. Full article
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Open AccessArticle
Sleep Stage Classification by a Combination of Actigraphic and Heart Rate Signals
J. Low Power Electron. Appl. 2017, 7(4), 28; doi:10.3390/jlpea7040028 -
Abstract
Although heart rate variability and actigraphic data have been used for sleep-wake or sleep stage classifications, there are few studies on the combined use of them. Recent wearable sensors, however, equip both pulse wave and actigraphic sensors. This paper presents results on the
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Although heart rate variability and actigraphic data have been used for sleep-wake or sleep stage classifications, there are few studies on the combined use of them. Recent wearable sensors, however, equip both pulse wave and actigraphic sensors. This paper presents results on the performance of sleep stage classification by a combination of heart rate and actigraphic signals. We studied 40,643 epochs (length 3 min) of polysomnographic data in 289 subjects. A combined model, consisting of autonomic functional indices from heart rate variability and body movement indices derived from actigraphic data, discriminated non-rapid-eye-movement (REM) sleep from waking/REM sleep with 76.9% sensitivity, 74.5% specificity, 75.8% accuracy, and a Cohen’s kappa of 0.514. The combination was also useful for discriminating between REM sleep and waking at 77.2% sensitivity, 72.3% specificity, 74.5% accuracy, and a kappa of 0.491. Full article
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Open AccessArticle
A Low-Power Active Self-Interference Cancellation Technique for SAW-Less FDD and Full-Duplex Receivers
J. Low Power Electron. Appl. 2017, 7(4), 27; doi:10.3390/jlpea7040027 -
Abstract
An active self-interference (SI) cancellation technique for SAW-less receiver linearity improvement is proposed. The active canceler combines programmable gain and phase in a single stage and is co-designed with a highly-linear LNA, achieving low noise and low power. A cross-modulation mechanism of the
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An active self-interference (SI) cancellation technique for SAW-less receiver linearity improvement is proposed. The active canceler combines programmable gain and phase in a single stage and is co-designed with a highly-linear LNA, achieving low noise and low power. A cross-modulation mechanism of the SI canceler is identified and strongly suppressed thanks to the introduction of an internal resistive feedback, enabling high effective receiver IIP3. TX leakage of up to −4 dBm of power is suppressed by over 30 dB at the input of the LNA, with benefits for the entire receiver in terms of IIP3, IIP2, and reciprocal mixing. The design was done in a 40 nm CMOS technology. The system, including receiver and active SI canceler, consumes less than 25 mW of power. When the canceler is enabled, it has an NF of 3.9–4.6 dB between 1.7 and 2.4 GHz and an effective IIP3 greater than 35 dBm. Full article
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Open AccessArticle
Inkjet Printed Fully-Passive Body-Worn Wireless Sensors for Smart and Connected Community (SCC)
J. Low Power Electron. Appl. 2017, 7(4), 26; doi:10.3390/jlpea7040026 -
Abstract
Future Smart and Connected Communities (SCC) will utilize distributed sensors and embedded computing to seamlessly generate meaningful data that can assist individuals, communities, and society with interlocking physical, social, behavioral, economic, and infrastructural interaction. SCC will require newer technologies for seamless and unobtrusive
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Future Smart and Connected Communities (SCC) will utilize distributed sensors and embedded computing to seamlessly generate meaningful data that can assist individuals, communities, and society with interlocking physical, social, behavioral, economic, and infrastructural interaction. SCC will require newer technologies for seamless and unobtrusive sensing and computation in natural settings. This work presents a new technology for health monitoring with low-cost body-worn disposable fully passive electronic sensors, along with a scanner, smartphone app, and web-server for a complete smart sensor system framework. The novel wireless resistive analog passive (WRAP) sensors are printed using an inkjet printing (IJP) technique on paper with silver inks (Novacentrix Ag B40, sheet resistance of 21 mΩ/sq) and incorporate a few discrete surface mounted electronic components (overall thickness of <1 mm). These zero-power flexible sensors are powered through a wireless inductive link from a low-power scanner (500 mW during scanning burst of 100 ms) by amplitude modulation at the carrier signal of 13.56 MHz. While development of various WRAP sensors is ongoing, this paper describes development of a WRAP temperature sensor in detail as an illustration. The prototypes were functionally verified at various temperatures with energy consumption of as low as 50 mJ per scan. The data is analyzed with a smartphone app that computes severity (Events-of-Interest, or EoI) using a real-time algorithm. The severity can then be anonymously shared with a custom web-server, and visualized either in temporal or spatial domains. This research aims to reduce ER visits of patients by enabling self-monitoring, thereby improving community health for SSC. Full article
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Open AccessArticle
Evaluating the Impact of Max Transition Constraint Variations on Power Reduction Capabilities in Cell-Based Designs
J. Low Power Electron. Appl. 2017, 7(4), 25; doi:10.3390/jlpea7040025 -
Abstract
Power optimization is a very important and challenging step in the physical design flow, and it is a critical success factor of an application-specific integrated circuit (ASIC) chip. Many techniques are used by the place and route (P&R) electronic design automation (EDA) tools
[...] Read more.
Power optimization is a very important and challenging step in the physical design flow, and it is a critical success factor of an application-specific integrated circuit (ASIC) chip. Many techniques are used by the place and route (P&R) electronic design automation (EDA) tools to meet the power requirement. In this paper, we will evaluate, independently from the library file, the impact of redefining the max transition constraint (MTC) before the power optimization phase, and we will study the impact of over-constraining or under-constraining a design on power in order to find the best trade-off between design constraining and power optimization. Experimental results showed that power optimization depends on the applied MTC and that the MTC value corresponding to the best power reduction results is different from the default MTC. By using a new MTC definition method on several designs, we found that the power gain between the default methodology and the new one reaches 2.34%. Full article
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