Open AccessArticle
A 4.1 W/mm2 Hybrid Inductive/Capacitive Converter for 2–140 mA-DVS Load under Inductor
J. Low Power Electron. Appl. 2016, 6(3), 18; doi:10.3390/jlpea6030018 -
Abstract
This work presents a fully integrated hybrid inductive/capacitive converter maintaining high efficiency for a load range of 2 mA to 140 mA (70×) suitable for the dynamic voltage scaling (DVS) based loads. This high efficiency is achieved by using an inductive converter [...] Read more.
This work presents a fully integrated hybrid inductive/capacitive converter maintaining high efficiency for a load range of 2 mA to 140 mA (70×) suitable for the dynamic voltage scaling (DVS) based loads. This high efficiency is achieved by using an inductive converter for higher loads (15–140 mA, 0.50–0.9 V) and a capacitive converter for lighter loads (2–5 mA, 0.40–0.55 V) with a 50 mV hysteresis margin. A digital state machine activates the appropriate converter based on the power efficiency and enables the converter hand-over. The functional feasibility of implementing digital circuits as representative loads under the inductor is shown thereby increasing the peak converter power density from 0.387 W/mm2 to 4.1 W/mm2 with only a minor hit on the efficiency. The maximum measured efficiency is achieved in inductive mode of operation and decreases from 76.4% to 71% when digital circuits are present under the inductor. The design was fabricated in IBM’s 32 nm SOI technology. Full article
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Open AccessArticle
A Fully Integrated 2:1 Self-Oscillating Switched-Capacitor DC–DC Converter in 28 nm UTBB FD-SOI
J. Low Power Electron. Appl. 2016, 6(3), 17; doi:10.3390/jlpea6030017 -
Abstract
The importance of energy-constrained processors continues to grow especially for ultra-portable sensor-based platforms for the Internet-of-Things (IoT). Processors for these IoT applications primarily operate at near-threshold (NT) voltages and have multiple power modes. Achieving high conversion efficiency within the DC–DC converter that [...] Read more.
The importance of energy-constrained processors continues to grow especially for ultra-portable sensor-based platforms for the Internet-of-Things (IoT). Processors for these IoT applications primarily operate at near-threshold (NT) voltages and have multiple power modes. Achieving high conversion efficiency within the DC–DC converter that supplies these processors is critical since energy consumption of the DC–DC/processor system is proportional to the DC–DC converter efficiency. The DC–DC converter must maintain high efficiency over a large load range generated from the multiple power modes of the processor. This paper presents a fully integrated step-down self-oscillating switched-capacitor DC–DC converter that is capable of meeting these challenges. The area of the converter is 0.0104 mm2 and is designed in 28 nm ultra-thin body and buried oxide fully-depleted SOI (UTBB FD-SOI). Back-gate biasing within FD-SOI is utilized to increase the load power range of the converter. With an input of 1 V and output of 460 mV, measurements of the converter show a minimum efficiency of 75% for 79 nW to 200 µW loads. Measurements with an off-chip NT processor load show efficiency up to 86%. The converter’s large load power range and high efficiency make it an excellent fit for energy-constrained processors. Full article
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Open AccessFeature PaperArticle
Sizing of SRAM Cell with Voltage Biasing Techniques for Reliability Enhancement of Memory and PUF Functions
J. Low Power Electron. Appl. 2016, 6(3), 16; doi:10.3390/jlpea6030016 -
Abstract
Static Random Access Memory (SRAM) has recently been developed into a physical unclonable function (PUF) for generating chip-unique signatures for hardware cryptography. The most compelling issue in designing a good SRAM-based PUF (SPUF) is that while maximizing the mismatches between the transistors [...] Read more.
Static Random Access Memory (SRAM) has recently been developed into a physical unclonable function (PUF) for generating chip-unique signatures for hardware cryptography. The most compelling issue in designing a good SRAM-based PUF (SPUF) is that while maximizing the mismatches between the transistors in the cross-coupled inverters improves the quality of the SPUF, this ironically also gives rise to increased memory read/write failures. For this reason, the memory cells of existing SPUFs cannot be reused as storage elements, which increases the overheads of cryptographic system where long signatures and high-density storage are both required. This paper presents a novel design methodology for dual-mode SRAM cell optimization. The design conflicts are resolved by using word-line voltage modulation, dynamic voltage scaling, negative bit-line and adaptive body bias techniques to compensate for reliability degradation due to transistor downsizing. The augmented circuit-level techniques expand the design space to achieve a good solution to fulfill several otherwise contradicting key design qualities for both modes of operation, as evinced by our statistical analysis and simulation results based on complementary metal–oxide–semiconductor (CMOS) 45 nm bulk Predictive Technology Model. Full article
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Open AccessArticle
Stochastic-Based Spin-Programmable Gate Array with Emerging MTJ Device Technology
J. Low Power Electron. Appl. 2016, 6(3), 15; doi:10.3390/jlpea6030015 -
Abstract
This paper describes the stochastic-based Spin-Programmable Gate Array (SPGA), an innovative architecture attempting to exploit the stochastic switching behavior newly found in emerging spintronic devices for reconfigurable computing. While many recently studies have investigated using Spin Transfer Torque Memory (STTM) devices to [...] Read more.
This paper describes the stochastic-based Spin-Programmable Gate Array (SPGA), an innovative architecture attempting to exploit the stochastic switching behavior newly found in emerging spintronic devices for reconfigurable computing. While many recently studies have investigated using Spin Transfer Torque Memory (STTM) devices to replace configuration memory in field programmable gate arrays (FPGAs), our study, for the first time, attempts to use the quantum-induced stochastic property exhibited by spintronic devices directly for reconfiguration and logic computation. Specifically, the SPGA was designed from scratch for high performance, routability, and ease-of-use. It supports variable-granularity multiple-input-multiple-output (MIMO) logic blocks and variable-length bypassing interconnects with a symmetrical structure. Due to its unconventional architectural features, the SPGA requires several major modifications to be made in the standard VPR placement/routing CAD flow, which include a new technology mapping algorithm based on computing (k, l)-cut, a new placement algorithm, and a modified delay-based routing procedure.Previous studies have shown that, simply replacing reconfiguration memory bits with spintronic devices, the conventional 2D island-style FPGA architecture can achieve approximately 5 times area savings, 2 times speedup and 1.6 times power savings. Our mixed-mode simulation results have shown that, with FPGA architecture innovations, on average, a SPGA can further achieve more than 10 times improvement in logic density, about 5 times improvement in average net delay, and about 5 times improvement in the critical-path delay for the largest 12 MCNC benchmark circuits over an island-style baseline FPGA with spintronic configuration bits. Full article
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Open AccessArticle
Remote System Setup Using Large-Scale Field Programmable Analog Arrays (FPAA) to Enabling Wide Accessibility of Configurable Devices
J. Low Power Electron. Appl. 2016, 6(3), 14; doi:10.3390/jlpea6030014 -
Abstract
We present a novel remote test system, an integrated remote testing system requiring minimal technology support overhead, enabled by configurable analog–digital Integrated Circuits (IC) to create a simple interface for a wide range of experiments. Our remote test system requires no additional [...] Read more.
We present a novel remote test system, an integrated remote testing system requiring minimal technology support overhead, enabled by configurable analog–digital Integrated Circuits (IC) to create a simple interface for a wide range of experiments. Our remote test system requires no additional setup, resulting both from using highly configurable devices, as well as from the advancement of straight-forward digital interfaces (i.e., USB) for the resulting experimental system. The system overhead requirements require simple email handling, available over almost all network systems with no additional requirements. The system is empowered through large-scale Field Programmable Analog Array (FPAA) devices and Baseline Tool Framework (BTF), where we present a range of experimentally measured examples illustrating the range of user interfacing available for the remote user. Full article
Open AccessArticle
Scaling Floating-Gate Devices Predicting Behavior for Programmable and Configurable Circuits and Systems
J. Low Power Electron. Appl. 2016, 6(3), 13; doi:10.3390/jlpea6030013 -
Abstract
This paper presents scaling of Floating-Gate (FG) devices, and the resulting implication to large-scale Field Programmable Analog Arrays (FPAA) systems. The properties of FG circuits and systems in one technology (e.g., 350 nm CMOS) are experimentally shown to roughly translate to FG [...] Read more.
This paper presents scaling of Floating-Gate (FG) devices, and the resulting implication to large-scale Field Programmable Analog Arrays (FPAA) systems. The properties of FG circuits and systems in one technology (e.g., 350 nm CMOS) are experimentally shown to roughly translate to FG circuits in scaled down processes in a way predictable through MOSFET physics concepts. Scaling FG devices results in higher frequency response, (e.g., FPAA fabric) as well as lower parasitic capacitance and lower power consumption. FPAA architectures, limited to 50–100 MHz frequency ranges could be envisioned to operate at 500 MHz–1 GHz for 130 nm line widths, and operate around 4 GHz for 40 nm line widths. Full article
Open AccessArticle
Energy-Efficient Hardware Implementation of an LR-Aided K-Best MIMO Decoder for 5G Networks
J. Low Power Electron. Appl. 2016, 6(3), 12; doi:10.3390/jlpea6030012 -
Abstract
Energy efficiency is a primary design goal for future green wireless communication technologies. Multiple-input multiple-output (MIMO) schemes have been proposed in the literature to improve the throughput of communication systems, and they are expected to play a prominent role in the upcoming [...] Read more.
Energy efficiency is a primary design goal for future green wireless communication technologies. Multiple-input multiple-output (MIMO) schemes have been proposed in the literature to improve the throughput of communication systems, and they are expected to play a prominent role in the upcoming fifth generation (5G) standard. This paper presents a novel, high-efficiency MIMO decoder based on the K-Best algorithm with lattice reduction. We have designed a novel hardware architecture for this decoder, which was implemented using 32 nm standard CMOS technology. Our results show that the proposed decoder can achieve on average a four-fold reduction in the power costs compared to recently published designs for 5G networks. The throughput of the design is 506 Mbits/s, which is comparable to existing designs. Full article
Open AccessArticle
A Design and Theoretical Analysis of a 145 mV to 1.2 V Single-Ended Level Converter Circuit for Ultra-Low Power Low Voltage ICs
J. Low Power Electron. Appl. 2016, 6(3), 11; doi:10.3390/jlpea6030011 -
Abstract
This paper presents an ultra-low swing level converter with integrated charge pumps that shows measured conversion in a 130-nm CMOS test chip from an input at a 145-mV swing to a 1.2-V output. Lowering the input allowable for a single-ended level converter [...] Read more.
This paper presents an ultra-low swing level converter with integrated charge pumps that shows measured conversion in a 130-nm CMOS test chip from an input at a 145-mV swing to a 1.2-V output. Lowering the input allowable for a single-ended level converter supports energy harvesting systems that need to use very low voltages. Full article
Open AccessArticle
A 0.2 V, 23 nW CMOS Temperature Sensor for Ultra-Low-Power IoT Applications
J. Low Power Electron. Appl. 2016, 6(2), 10; doi:10.3390/jlpea6020010 -
Abstract
We propose a fully on-chip CMOS temperature sensor in which a sub-threshold (sub-VT) proportional-to-absolute-temperature (PTAT) current element starves a current-controlled oscillator (CCO). Sub-VT design enables ultra-low-power operation of this temperature sensor. However, such circuits are highly sensitive to process [...] Read more.
We propose a fully on-chip CMOS temperature sensor in which a sub-threshold (sub-VT) proportional-to-absolute-temperature (PTAT) current element starves a current-controlled oscillator (CCO). Sub-VT design enables ultra-low-power operation of this temperature sensor. However, such circuits are highly sensitive to process variations, thereby causing varying circuit currents from die to die. We propose a bit-weighted current mirror (BWCM) architecture to resist the effect of process-induced variation in the PTAT current. The analog core constituting the PTAT, the CCO, and the BWCM is operational down to 0.2 V supply voltage. A digital block operational at 0.5 V converts the temperature information into a digital code that can be processed and used by other components in a system-on-chip (SoC). The proposed temperature sensor system also supports resolution-power trade-off for Internet-of-things (IoT) applications with different sampling rates and energy needs. The system power consumption is 23 nW and the maximum temperature inaccuracy is +1.5/−1.7 °C from 0 °C to 100 °C with a two-point calibration. The temperature sensor system was designed in a 130 nm CMOS technology and its total area is 250 × 250 μm2. Full article
Open AccessReview
Mastering the Art of High Mobility Material Integration on Si: A Path towards Power-Efficient CMOS and Functional Scaling
J. Low Power Electron. Appl. 2016, 6(2), 9; doi:10.3390/jlpea6020009 -
Abstract
In this work, we will review the current progress in integration and device design of high mobility devices. With main focus on (Si)Ge for PMOS and In(Ga)As for NMOS, the benefits and challenges of integrating these materials on a Si platform will [...] Read more.
In this work, we will review the current progress in integration and device design of high mobility devices. With main focus on (Si)Ge for PMOS and In(Ga)As for NMOS, the benefits and challenges of integrating these materials on a Si platform will be discussed for both density scaling (“more Moore”) and functional scaling to enhance on-chip functionality (“more than Moore”). Full article
Open AccessArticle
A Sub-Threshold 8T SRAM Macro with 12.29 nW/KB Standby Power and 6.24 pJ/access for Battery-Less IoT SoCs
J. Low Power Electron. Appl. 2016, 6(2), 8; doi:10.3390/jlpea6020008 -
Abstract
We present an ultra-low power (ULP) 1 KB SRAM macro for Internet of Things (IoT) battery-less systems-on-chip (SoCs) operating under varying energy harvesting conditions. The unique combination of features within this array allows battery-less SoCs to retain important information for a significantly [...] Read more.
We present an ultra-low power (ULP) 1 KB SRAM macro for Internet of Things (IoT) battery-less systems-on-chip (SoCs) operating under varying energy harvesting conditions. The unique combination of features within this array allows battery-less SoCs to retain important information for a significantly longer period of time when energy harvesting conditions are poor. The array uses 8T high-threshold (high-VT) static random access memory (SRAM) cells with word line boosting to eliminate write failures coupled with a read-before-write scheme to address read-disturb in half-selected cells. Due to the reduced on current in high-VT devices, read word line boosting is implemented to improve the drive strength of the read buffer, and to eliminate read failures. Leakage currents through the unselected cells during a read operation is addressed by boosting the footer virtual VSS (VVSS) of the read port to the supply voltage (VDD). To reduce the power consumption of instruction memories in battery-less SoCs, two features were utilized in this array: a read burst mode is used when reading consecutive addresses to reduce the read energy, and instructions with higher percentages of “1” data are defined since reading a “1” is less costly than reading a “0” in 8T cells. The proposed array can operate at a wide range of supply voltages (350–700 mV) and has two ULP modes: standby with retention (1.5 pW/bit) and shutdown without retention (0.13 pW/bit). Aggressive power gating of all peripherals during the standby state reduces the array power consumption down to 12.29 nW/KB at 320 mV with data retention. Compared to previously published 8T arrays, the proposed design provides the lowest standby power. The complete shutdown of the array allows further reduction down to 1.09 nW/KB and is suitable for reducing the power consumption of data memories in battery-less SoCs. The measured results from a commercial 130 nm chip show that the proposed array consumes a minimum of 6.24 pJ/access with a 17.16 nW standby power at 400 mV. The read burst mode allows up to 22% reduction in energy/access at 400 mV. Full article
Open AccessArticle
A 36 nW, 7 ppm/°C on-Chip Clock Source Platform for Near-Human-Body Temperature Applications
J. Low Power Electron. Appl. 2016, 6(2), 7; doi:10.3390/jlpea6020007 -
Abstract
We propose a fully on-chip clock-source system in which an ultra-low-power diode-based temperature-uncompensated oscillator (OSCdiode) serves as the main clock source and frequency locks to a higher-power temperature-compensated oscillator (OSCcmp) that is disabled after each locking event to [...] Read more.
We propose a fully on-chip clock-source system in which an ultra-low-power diode-based temperature-uncompensated oscillator (OSCdiode) serves as the main clock source and frequency locks to a higher-power temperature-compensated oscillator (OSCcmp) that is disabled after each locking event to save power. The locking allows the stability of the uncompensated oscillator to stay within the stability bound of the compensated design. This paper demonstrates the functionality of a locking controller that uses a periodic (counter-based) scheme implemented on-chip and a prediction (temperature-drift-based) scheme. The flexible clock source platform is validated in a 130 nm CMOS technology. In the demonstrated system, it achieves an effective average temperature stability of 7 ppm/°C in the human body temperature range from 20 °C to 40 °C with a power consumption of 36 nW at 0.7 V. It achieves a frequency range of 12 kHz to 150 kHz at 0.7 V. Full article
Open AccessArticle
Toward a Faster Screening of Faulty Digital Chips via Current-Bound Estimation Based on Device Size and Threshold Voltage
J. Low Power Electron. Appl. 2016, 6(2), 6; doi:10.3390/jlpea6020006 -
Abstract
Observations of peak and average currents are important for designed circuits, as faulty circuits have abnormal peaks and average currents. Using current bounds to detect faulty chips is a comparatively innovative idea, and many advanced schemes without them use it as a [...] Read more.
Observations of peak and average currents are important for designed circuits, as faulty circuits have abnormal peaks and average currents. Using current bounds to detect faulty chips is a comparatively innovative idea, and many advanced schemes without them use it as a component in statistical outlier analysis. However, these previous research works have focused on the discussion of the testing impact without a proposed method to define reference current bounds to find faulty chips. A software framework is proposed to synthesize high-performance, power-performance optimized, noise-immune, and low-power circuits with current-bound estimations for testing. This framework offers a rapid methodology to quickly screen potential faulty chips by using the peak and average current bounds for different purposed circuits. The proposed estimation technique generates suitable reference current bounds from transistor threshold voltage and size adjustments. The SPICE-level simulation leads to the most accurate estimations. However, such simulations are not feasible for a large digital circuit. Hence, this work proposes constructing a feasible gate-level software framework for large digital circuits that will serve all of simulation purposes. In comparison with transistor-level Nanosim simulations, the proposed gate-level simulation framework has a margin of error of less than 2% in the peak current, and the computation time is 334 times faster. Full article
Open AccessArticle
A Survey of Cache Bypassing Techniques
J. Low Power Electron. Appl. 2016, 6(2), 5; doi:10.3390/jlpea6020005 -
Abstract
With increasing core-count, the cache demand of modern processors has also increased. However, due to strict area/power budgets and presence of poor data-locality workloads, blindly scaling cache capacity is both infeasible and ineffective. Cache bypassing is a promising technique to increase effective [...] Read more.
With increasing core-count, the cache demand of modern processors has also increased. However, due to strict area/power budgets and presence of poor data-locality workloads, blindly scaling cache capacity is both infeasible and ineffective. Cache bypassing is a promising technique to increase effective cache capacity without incurring power/area costs of a larger sized cache. However, injudicious use of cache bypassing can lead to bandwidth congestion and increased miss-rate and hence, intelligent techniques are required to harness its full potential. This paper presents a survey of cache bypassing techniques for CPUs, GPUs and CPU-GPU heterogeneous systems, and for caches designed with SRAM, non-volatile memory (NVM) and die-stacked DRAM. By classifying the techniques based on key parameters, it underscores their differences and similarities. We hope that this paper will provide insights into cache bypassing techniques and associated tradeoffs and will be useful for computer architects, system designers and other researchers. Full article
Open AccessArticle
A 300-mV ΔΣ Modulator Using a Gain-Enhanced, Inverter-Based Amplifier for Medical Implant Devices
J. Low Power Electron. Appl. 2016, 6(1), 4; doi:10.3390/jlpea6010004 -
Abstract
An ultra-low-voltage low-power switched-capacitor (SC) delta-sigma (ΔΣ) modulator running at a supply voltage as low as 300 mV is presented for biomedical implant devices, e.g., cardiac pacemakers. To reduce the supply voltage, an inverter-based amplifier is used in the integrators, whose DC [...] Read more.
An ultra-low-voltage low-power switched-capacitor (SC) delta-sigma (ΔΣ) modulator running at a supply voltage as low as 300 mV is presented for biomedical implant devices, e.g., cardiac pacemakers. To reduce the supply voltage, an inverter-based amplifier is used in the integrators, whose DC gain and gain-bandwidth (GBW) are boosted by a simple current-mirror output stage. The full input-feedforward loop topology offers low integrators internal swing, supporting ultra-low-voltage operation. To demonstrate the concept, a second-order loop topology was chosen. The entire modulator operates reliably against process, voltage and temperature (PVT) variations from a 300 mV ± 10% supply voltage only, while the switches are driven by a charge pump clock boosting scheme. Designed in a 65 nm CMOS technology and clocked at 256 kHz, the simulation results show that the modulator can achieve a 64.4 dB signal-to-noise ratio (SNR) and a 60.7 dB signal-to-noise and distortion ratio (SNDR) over a 1.0 kHz signal bandwidth while consuming 0.85 μW of power. Full article
Open AccessArticle
An Open-Source Tool Set Enabling Analog-Digital-Software Co-Design
J. Low Power Electron. Appl. 2016, 6(1), 3; doi:10.3390/jlpea6010003 -
Abstract
This paper presents an analog-digital hardware-software co-design environment for simulating and programming reconfigurable systems. The tool simulates, designs, as well as enables experimental measurements after compiling to configurable systems in the same integrated design tool framework. High level software in Scilab/Xcos (open-source [...] Read more.
This paper presents an analog-digital hardware-software co-design environment for simulating and programming reconfigurable systems. The tool simulates, designs, as well as enables experimental measurements after compiling to configurable systems in the same integrated design tool framework. High level software in Scilab/Xcos (open-source programs similar to MATLAB/Simulink) that converts the high-level block description by the user to blif format (sci2blif), which acts as an input to the modified VPR tool, including the code v p r 2 s w c s , encoding the specific platform through specific architecture files, resulting in a targetable switch list on the resulting configurable analog–digital system. The resulting tool uses an analog and mixed-signal library of components, enabling users and future researchers access to the basic analog operations/computations that are possible. Full article
Open AccessEditorial
Acknowledgement to Reviewers of Journal of Low Power Electronics and Applications in 2015
J. Low Power Electron. Appl. 2016, 6(1), 2; doi:10.3390/jlpea6010002 -
Abstract The editors of Journal of Low Power Electronics and Applications would like to express their sincere gratitude to the following reviewers for assessing manuscripts in 2015. [...] Full article
Open AccessArticle
A Technique for Improving Lifetime of Non-Volatile Caches Using Write-Minimization
J. Low Power Electron. Appl. 2016, 6(1), 1; doi:10.3390/jlpea6010001 -
Abstract
While non-volatile memories (NVMs) provide high-density and low-leakage, they also have low write-endurance. This, along with the write-variation introduced by the cache management policies, can lead to very small cache lifetime. In this paper, we propose ENLIVE, a technique for ENhancing the [...] Read more.
While non-volatile memories (NVMs) provide high-density and low-leakage, they also have low write-endurance. This, along with the write-variation introduced by the cache management policies, can lead to very small cache lifetime. In this paper, we propose ENLIVE, a technique for ENhancing the LIfetime of non-Volatile cachEs. Our technique uses a small SRAM (static random access memory) storage, called HotStore. ENLIVE detects frequently written blocks and transfers them to the HotStore so that they can be accessed with smaller latency and energy. This also reduces the number of writes to the NVM cache which improves its lifetime. We present microarchitectural schemes for managing the HotStore. Simulations have been performed using an x86-64 simulator and benchmarks from SPEC2006 suite. We observe that ENLIVE provides higher improvement in lifetime and better performance and energy efficiency than two state-of-the-art techniques for improving NVM cache lifetime. ENLIVE provides 8.47×, 14.67× and 15.79× improvement in lifetime or two, four and eight core systems, respectively. In addition, it works well for a range of system and algorithm parameters and incurs only small overhead. Full article
Open AccessFeature PaperArticle
An FSK and OOK Compatible RF Demodulator for Wake Up Receivers
J. Low Power Electron. Appl. 2015, 5(4), 274-290; doi:10.3390/jlpea5040274 -
Abstract
This work proposes a novel demodulation circuit to address the implementation of Wake-Up Receivers (Wu-Rx) in Wireless Sensor Nodes (WSN). This RF demodulator, namely Modulated Oscillator for envelOpe Detection (MOOD), is compatible with both FSK and OOK/ASK modulation schemes. The system embeds [...] Read more.
This work proposes a novel demodulation circuit to address the implementation of Wake-Up Receivers (Wu-Rx) in Wireless Sensor Nodes (WSN). This RF demodulator, namely Modulated Oscillator for envelOpe Detection (MOOD), is compatible with both FSK and OOK/ASK modulation schemes. The system embeds an LC oscillator, an envelope detector and a base-band amplifier. To optimize the trade-off between RF performances and power consumption, the cross-coupled based oscillator is biased in moderate inversion region. The proof of concept is implemented in a 65 nm CMOS technology and is intended for the 2.4 GHz ISM band. With a supply voltage of 0.5 V, the demodulator consumes 120 μW and demonstrates the demodulation of OOK and FSK at a data rate of 500 kbps. Full article
Open AccessFeature PaperArticle
Reconfigurable RF Energy Harvester with Customized Differential PCB Antenna
J. Low Power Electron. Appl. 2015, 5(4), 257-273; doi:10.3390/jlpea5040257 -
Abstract
In this work, a Radio Frequency (RF) Energy Harvester comprised of a differential Radio Frequency-to-Direct Current (RF-DC) converter realized in ST130 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology and a customized broadband Printed Circuit Board (PCB) antenna with inductive coupling feeding is presented. Experimental [...] Read more.
In this work, a Radio Frequency (RF) Energy Harvester comprised of a differential Radio Frequency-to-Direct Current (RF-DC) converter realized in ST130 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology and a customized broadband Printed Circuit Board (PCB) antenna with inductive coupling feeding is presented. Experimental results show that the system can work with different carrier frequencies and thanks to its reconfigurable architecture the proposed converter is able to provide a regulated output voltage of 2 V over a 14 dB of RF input power range. The conversion efficiency of the whole system peaks at 18% under normal outdoor working conditions. Full article