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Proceedings 2017, 1(4), 338; doi:10.3390/proceedings1040338

Linear-Logarithmic CMOS Image Sensor with Reduced FPN Using Photogate and Cascode MOSFET

1
School of Electronics Engineering, Kyungpook National University, Daegu 41566, Korea
2
Department of Sensor and Display Engineering, Kyungpook National University, Daegu 41566, Korea
Presented at the Eurosensors 2017 Conference, Paris, France, 3–6 September 2017.
*
Author to whom correspondence should be addressed.
Published: 18 August 2017
Download PDF [661 KB, uploaded 18 August 2017]

Abstract

We propose a linear-logarithmic CMOS image sensor with reduced fixed pattern noise (FPN). The proposed linear-logarithmic pixel based on a conventional 3-transistor active pixel sensor (APS) structure has additional circuits in which a photogate and a cascade MOSFET are integrated with the pixel structure in conjunction with the photodiode. To improve FPN, we applied the PMOSFET hard reset method as a reset transistor instead of NMOSFET reset normally used in APS. The proposed pixel has been designed and fabricated using 0.18-μm 1-poly 6-metal standard CMOS process. A 120 × 240 pixel array of test chip was divided into 2 different subsections with 60 × 240 sub-arrays, so that the proposed linear-logarithmic pixel with reduced FPN could be compared with the conventional linear-logarithmic pixel. We confirmed a reduction of pixel response variation which affected image quality.
Keywords: CMOS image sensor; hard reset; photogate; cascode MOSFET CMOS image sensor; hard reset; photogate; cascode MOSFET
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. (CC BY 4.0).

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MDPI and ACS Style

Bae, M.; Choi, B.-S.; Kim, S.-H.; Lee, J.; Oh, C.-W.; Choi, P.; Shin, J.-K. Linear-Logarithmic CMOS Image Sensor with Reduced FPN Using Photogate and Cascode MOSFET. Proceedings 2017, 1, 338.

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