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Proceedings 2017, 1(4), 337; doi:10.3390/proceedings1040337

A Monolithic Three-Axis Accelerometer with Wafer-Level Package by CMOS MEMS Process

National Chip Implementation Center, Natioanl Applied Research Laboratories, Taiwan
Presented at the Eurosensors 2017 Conference, Paris, France, 3–6 September 2017.
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Published: 11 August 2017
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Abstract

This paper presents a monolithic three-axis accelerometer with wafer-level package by CMOS MEMS process. The compositions of the microstructure are selected from CMOS layers in order to suppress the in-plane and out-of-plane bending deflection caused by the residual stresses in multiple layers. A switched-capacitor sensing circuit with a trimming mechanism is used to amplify the capacitive signal, and decrease the output dc offset voltage to ensure the desired output voltage swing. The CMOS MEMS wafer is capped with a silicon wafer using a polymer-based material. The measured sensitivities with and without a wafer-level package range from 113 mV/G to 124 mV/G for the in-plane (x-axis, y-axis) accelerometer, and from 50 mV/G to 53 mV/G for the z-axis accelerometer, respectively.
Keywords: monolithic; wafer-level package; CMOS MEMS; accelerometer monolithic; wafer-level package; CMOS MEMS; accelerometer
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. (CC BY 4.0).

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MDPI and ACS Style

Tseng, S.H.; Yeh, C.Y.; Chang, A.Y.; Wang, Y.J.; Chen, P.C.; Tsai, H.H.; Juang, Y.Z. A Monolithic Three-Axis Accelerometer with Wafer-Level Package by CMOS MEMS Process. Proceedings 2017, 1, 337.

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