Analysis, Design, and Experimental Validation of a Primary Side Current-Sensing Flyback Converter for Use in a Battery Management System

Abstract

The purpose of the presented flyback converter is to equalise the voltage between the cells in a series string within a battery pack providing an active cell-balancing system. This would be an important part of a battery management system (BMS) for charging li-ion batteries in electric vehicles. The converter is based on primary side current sensing, where the conventional feedback circuit is omitted. The purpose of this converter is to improve efficiency by decreasing losses and to increase battery power density by decreasing the number of elements which constitute the power electronics; these are important factors for the future development of electric vehicle battery packs. Analysis of the circuit and the design procedure of the DC-DC flyback converter with primary current sensing is presented in this paper. Finally, several experimental converters have been built and tested to validate the authors’ approach.

1. Introduction

Electric vehicles are gaining significant interest as part of the solution for mitigating anthropogenic climate change and poor air quality in cities. The batteries to power these vehicles are the object of significant research [1,2,3,4] as multinational automobile manufacturers seek to grow their electric/hybrid vehicle range.

The battery management system (BMS) is an essential component of the on-board power electronics. Their primary purpose is safety, where the battery pack is prevented from over-charging or over-discharging. Additionally, they can be designed to ensure the long life of the battery pack by balancing the energy amongst the individual cells, and to provide information about the battery charge level or State of Charge (SoC).

Over the course of many charge/discharge cycles, the SoC of cells, and hence their respective voltages, connected in series within a string will become imbalanced [1,2,3]. This is caused by many unavoidable factors, such as slight differences during manufacture (i.e., no two cells are exactly alike), battery aging, temperature variations, and sudden changes in the energy. Eventually, such a mismatch causes an overall reduction in the battery capacity. It has been shown in [1] that for n cells connected in series, the overall string capacity depends on the cell with the lowest SoC. Active cell balancing is the term used to describe the process of transferring energy between the cells. In [5], a BMS with such balancing, based on a microcontroller and buck converter, is presented for two lead-acid batteries. Several network communication systems used in different BMSs are given in [6,7,8] and important functional and thermal analysis, respectively, in [9,10].

An electronic DC-DC converter is necessary for the active cell-balancing schematic proposed in this paper. The purpose of this converter is to charge a single cell separately from the string when its voltage is under a defined threshold. The basic schematic is shown in Figure 1. This schematic is based on a specialised BMS circuit [4], which is used for the voltage measurement of each cell within a series string. When one cell has a lower voltage than the others within the same string (e.g., cell 4 in Figure 1), the DC-DC converter, controlled by the BMS, charges that cell separately from the rest of the string.

A flyback DC-DC converter with primary side current sensing was chosen due to these unique features: the feedback circuit is omitted, resulting in a system with fewer elements; good efficiency (75–85%) for this class of converters; galvanic electrical isolation between the primary and secondary side, which makes it possible for the converter to be powered from the vehicle battery; good power density, which is a basic requirement of the electric vehicle’s on-board electronics; and it does not suffer from the current transfer ratio degradation that arises from the temperature rise found in low-cost optocouplers. Based on these advantages, this particular flyback converter has been the object of significant research. A primary side current regulation flyback converter used as a battery charger is shown in [11]. The design procedure is well-explained and the experimental results from the charging process are shown. However, the converter is proposed to work with only one separate battery and it is not part of a BMS.

Another highly efficient AC-DC converter is given in [12], but its function as a DC-DC converter is not considered in this research. Several control systems based on Application-Specific Integrated Circuits (ASICs), fuzzy logic, and digital control systems are given, respectively, in [13,14,15]. These sources offer good explanation of the basic control concepts without connection to the specific load. Several applicable design procedures are shown in the manufacturers’ design specifications [16,17,18,19,20,21]. Sophisticated approaches for the design of flyback converters with primary side current sensing are given, but they are based on off-line AC-DC schematics where the basic application is as LED lamp power supplies. Usually, their overall efficiency is around 75–78% for low output voltage (3.3–12 V) and 80–82% for high output voltage (12–24V) applications. In the developed converter, the input rectifier, the boost capacitor, and the input common mode filter must be excluded from the schematic for the DC-DC on-board charger, and this improves the efficiency for a flyback low (3.3 ÷ 5 V) output voltage converter. Another problem is how the constant current (CC) and constant voltage (CV) modes of operation of the primary side sensing converter will match the battery CC and CV charging. Currently, comprehensive research about the design of flyback primary current sensing working as an electric vehicle on-board battery charger is not available in the literature.

This paper proposes a flyback converter with primary side current sensing used as part of an electric vehicle battery management system. This requires the design procedures [16,17,19,20] to be altered according to the necessary DC-DC converter schematic. The analysed and designed converter is verified experimentally and the achieved efficiency is shown.

2. Analysis

The proposed schematic shown in Figure 1 contains the following elements:

• The Battery Management System can be based on one of the ASICs LTC6802-2, MAX1894, MAX11068, MAX11080, DS2726, BQ29330, AD7280, and ATA6870 [22,23,24]. This system monitors the overall battery voltage and controls the automatic switch (2) and the flyback converter (3). The BMS is not the object of research in this paper.
• The automatic switch system. This provides mechanical switching between the cells of the battery, and is also not the object of research in this paper.
• Primary side current flyback converter. The schematic is based on ASICs, for example AP3706, FAN104W, FL103, or MP020-5 [16,17,19,20]. This converter is used for the charging of a single cell (within a series string within a battery pack) if its voltage is lower than that of the other cells in the string. The charging process is conducted according to the CC (constant current) and CV (constant voltage) procedure shown in Figure 2.

Figure 3 shows the schematic of the proposed converter (Figure 3B) and its derivation from a classical flyback converter (Figure 3A) with a feedback circuit. In the former, the omitted feedback schematic requires information about the output voltage to be taken from the auxiliary winding (L₃) and about the output current from the current sense resistor (${\mathrm{R}}_5$).

Figure 3C–E show the discontinuous conduction mode of operation (DCM), the V-I characteristic of the converter, and the time sequence of operation required for the DCM, respectively. The secondary voltage measurement is based on the oscillation process occurring over the transistor ${\mathrm{Q}}_1$ (Drain-Source) during the current pause, ${\mathrm{t}}_{\mathrm{OFF}}$. It can be seen in Figure 3C that the voltage across ${\mathrm{Q}}_1$ (the Drain-Source), ${\mathrm{V}}_{\mathrm{DS}}$, is the sum of the input voltage, ${\mathrm{V}}_{\mathrm{in}}$, the output reflecting voltage, ${\mathrm{V}}_{\mathrm{R}.\mathrm{out}}$, and the over voltage, ${\mathrm{V}}_{\mathrm{DS}.\mathrm{over}}$. The output voltage reference can be obtained through the auxiliary winding (${\mathrm{L}}_3$), which is normally used as a power supply for the ASIC (Figure 3A). The voltage from the winding ${\mathrm{L}}_3$ and the divider ${\mathrm{R}}_{11}-{\mathrm{R}}_{12}$ must meet the ASIC range, which is usually between 2 and 5 V depending on the manufacturer’s requirements. In this way, a reference for the output voltage is given to the control system without the classical feedback circuit shown in Figure 3A.

The operation of the converter follows the next time sequence (Figure 3E):

• Time ${\mathrm{t}}_{\mathrm{ON}}$: the input voltage ${\mathrm{V}}_{\mathrm{DC}.\mathrm{in}}$ is applied across the primary side of the transformer (${\mathrm{L}}_1$, Figure 3B), which increases the primary side current from zero to the peak value (${\mathrm{I}}_{\mathrm{DC}.\mathrm{pk}}$).
• Time ${\mathrm{t}}_{\mathrm{DIS}}$: the primary side transistor (${\mathrm{Q}}_1$) is turned off and the rectifier on the secondary side (${\mathrm{D}}_4$) is turned on. The secondary side current decreases linearly to zero. At its zero point, the accumulated energy in the transformer is depleted.
• The time ${\mathrm{t}}_{\mathrm{OFF}}$: the primary side voltage across ${\mathrm{Q}}_1$ and the voltage across ${\mathrm{L}}_3$ begins to oscillate on the resonance frequency between the primary side inductance and the parasitic output capacitor.

Figure 3D shows the Constant Voltage (CV) and Constant Current (CC) operational area described earlier in Figure 2. Assuming that the converter works only as an additional charger for SoC equalisation, this suggests that an entire cycle of charging from 0% to 100% will not be done from this charger. It can be proposed that the operation mode coincides with point A where fast charging is possible. This means that the converter must operate with higher efficiency at that point. The other two points, point B 50% of nominal output voltage and point C minimum output voltage, are also an important part of the calculation procedure.

3. Design Procedure

The design procedure depends on the parameters of the specific ASIC [16,17,19,20], which vary depending on the manufacturer. Because of this, the design procedure suggested here shows the common application of a DC-DC flyback converter with primary side sensing. The design procedure is now described in detail.

3.1. Input Parameters

The successful design requires precise input parameters: ${\mathrm{V}}_{\mathrm{in}.\mathrm{nom}}$ is the nominal input voltage. In this case, this is the voltage from the vehicle battery where the minimum and maximum tolerances must also be given as ${\mathrm{V}}_{\mathrm{in}.\min }$ and ${\mathrm{V}}_{\mathrm{in}.\max }$. ${\mathrm{V}}_{\mathrm{out}.\mathrm{nom}}$ and ${\mathrm{I}}_{\mathrm{out}.\mathrm{nom}}$ are the nominal output voltage and current, respectively, considered according to the cell parameters shown in Figure 2. The output power is defined as ${\mathrm{P}}_{\mathrm{out}.\mathrm{nom}}={\mathrm{I}}_{\mathrm{out}.\mathrm{nom}}\times {\mathrm{V}}_{\mathrm{out}.\mathrm{nom}}$. Other parameters, such as temperature tolerances, size, weight, power density, and price, currently are not under consideration.

3.2. Estimation of the Efficiency

The input nominal power ${\mathrm{P}}_{\mathrm{in}.\mathrm{nom}}$ is given as:

$${\mathrm{P}}_{\mathrm{in}.\mathrm{nom}}=\frac{{\mathrm{V}}_{\mathrm{out}.\mathrm{nom}}\times {\mathrm{I}}_{\mathrm{out}.\mathrm{nom}}}{\mathsf{\eta }}.$$

(1)

The overall nominal efficiency at the beginning can be assumed to be within a wide range ${\mathsf{\eta }}_{\mathrm{overall}}\approx 75-85\%$. Although there is no input rectifier and filter due to the relatively low output voltage, a greater efficiency than 85% for this class of converter cannot be expected.

From Equation (1), the input power at point B (${\mathrm{P}}_{\mathrm{in}.\mathrm{B}}$) and point C (${\mathrm{P}}_{\mathrm{in}.\mathrm{C}}$) can be derived according to the next assumption: at point B, the output voltage drops to 50% of the nominal voltage and the overall efficiency falls to ${\mathsf{\eta }}_{\mathrm{overall}.\mathrm{B}}=50\%$; at point C, the efficiency and the input power depend on the minimum output voltage. With these assumptions, Equation (1) can be written for ${\mathrm{P}}_{\mathrm{in}.\mathrm{nom}.\mathrm{B}}$ efficiency at point B, ${\mathsf{\eta }}_{\mathrm{overall}.\mathrm{B}}$, as follows:

$${\mathrm{P}}_{\mathrm{in}.\mathrm{nom}.\mathrm{B}}=\frac{0.5\times {\mathrm{V}}_{\mathrm{out}.\mathrm{nom}}\times {\mathrm{I}}_{\mathrm{out}.\mathrm{nom}}}{{\mathsf{\eta }}_{\mathrm{overall}.\mathrm{B}}}$$

(2)

where the efficiency at point B, ${\mathsf{\eta }}_{\mathrm{overall}.\mathrm{B}}$, can be calculated from the overall efficiency, ${\mathsf{\eta }}_{\mathrm{overall}}$, and the secondary side diode forward-voltage drop, ${\mathrm{V}}_{\mathrm{F}}$, as:

$${\mathsf{\eta }}_{\mathrm{overall}.\mathrm{B}}\cong {\mathsf{\eta }}_{\mathrm{overall}}\times \frac{0.5\times {\mathrm{V}}_{\mathrm{out}.\mathrm{nom}}}{\left(0.5\times {\mathrm{V}}_{\mathrm{out}.\mathrm{nom}}+{\mathrm{V}}_{\mathrm{F}}\right)}\times \frac{\left({\mathrm{V}}_{\mathrm{out}.\mathrm{nom}}+{\mathrm{V}}_{\mathrm{F}}\right)}{{\mathrm{V}}_{\mathrm{out}.\mathrm{nom}}}.$$

(3)

At point C, the converter works at the minimum output voltage, ${\mathrm{V}}_{\mathrm{out}.\min }$, where the input power and the efficiency at this point, ${\mathsf{\eta }}_{\mathrm{overall}.\mathrm{C}}$, are respectively:

$${\mathrm{P}}_{\mathrm{in}.\mathrm{C}}=\frac{{\mathrm{V}}_{\mathrm{out}.\min }\times {\mathrm{I}}_{\mathrm{out}.\mathrm{nom}}}{{\mathsf{\eta }}_{\mathrm{overall}.\mathrm{C}}}$$

(4)

$${\mathsf{\eta }}_{\mathrm{overall}.\mathrm{C}}\cong {\mathsf{\eta }}_{\mathrm{overall}}\times \frac{{\mathrm{V}}_{\mathrm{out}.\min }}{\left({\mathrm{V}}_{\mathrm{out}.\min }+{\mathrm{V}}_{\mathrm{F}}\right)}\times \frac{\left({\mathrm{V}}_{\mathrm{out}.\mathrm{nom}}+{\mathrm{V}}_{\mathrm{F}}\right)}{{\mathrm{V}}_{\mathrm{out}.\mathrm{nom}}}.$$

(5)

Point A is the working point for the converter if it works on fast charge mode. The input power at that point will be:

$${\mathrm{P}}_{\mathrm{in}.\mathrm{A}}=\frac{{\mathrm{V}}_{\mathrm{out}.\mathrm{out}}\times {\mathrm{I}}_{\mathrm{out}.\mathrm{nom}}}{{\mathsf{\eta }}_{\mathrm{overall}}}=\frac{{\mathrm{V}}_{\mathrm{out}.\mathrm{out}}\times {\mathrm{I}}_{\mathrm{out}.\mathrm{nom}}}{75-85\%}$$

(6)

where as a first assumption 80% overall efficiency can be accepted.

3.3. Determination of the Transformer Turns Ratio

The suggested design procedure begins with transformer turns ratio determination as opposite to the established flyback design procedures [25,26] with optical feedback connections (Figure 3A). The transformer turn ratio parameter represents the ratio between the primary and secondary turns ${\mathrm{N}}_{\mathrm{P}}/{\mathrm{N}}_{\mathrm{S}}$. It must be chosen as a compromise between the primary and secondary voltage stress, respectively, over the transistor (${\mathrm{Q}}_1$, Figure 3B) and the diode (${\mathrm{D}}_4$, Figure 3B).

As can be seen in Figure 3C, when the transistor is turned off, the voltage drain-source (${\mathrm{V}}_{\mathrm{DS}}$) will be the sum of the input voltage (${\mathrm{V}}_{\mathrm{DC}.\mathrm{in}}$) and the reflected output voltage (${\mathrm{V}}_{\mathrm{R}.\mathrm{out}}$):

$${\mathrm{V}}_{\mathrm{DS}}={\mathrm{V}}_{\mathrm{DC}.\mathrm{in}}+{\mathrm{V}}_{\mathrm{R}.\mathrm{out}}+{\mathrm{V}}_{\mathrm{DS}.\mathrm{over}}$$

(7)

where the reflected output voltage (${\mathrm{V}}_{\mathrm{R}.\mathrm{out}}$) can be calculated according to the transformer turn ratio $\left({\mathrm{N}}_{\mathrm{S}}/{\mathrm{N}}_{\mathrm{P}}\right)$, i.e., secondary, ${\mathrm{N}}_{\mathrm{S}}$, and primary, ${\mathrm{N}}_{\mathrm{P}}$:

$${\mathrm{V}}_{\mathrm{R}.\mathrm{out}}=\frac{{\mathrm{N}}_{\mathrm{S}}}{{\mathrm{N}}_{\mathrm{P}}}\times \left({\mathrm{V}}_{\mathrm{out}}+{\mathrm{V}}_{\mathrm{F}}\right).$$

(8)

${\mathrm{V}}_{\mathrm{DS}.\mathrm{over}}$ is the overvoltage caused by the leakage inductance. In this design, ${\mathrm{N}}_{\mathrm{P}}/{\mathrm{N}}_{\mathrm{S}}$ is estimated according to the desired MOSFET type with respect to its nominal voltage drain-source. The calculation algorithm and the primary side voltage stress over ${\mathrm{Q}}_1$ are shown in Figure 4 according to the parameters assumed in Figure 3C.

The overvoltage ${\mathrm{V}}_{\mathrm{DS}.\mathrm{over}}$ and the entire oscillating process depend on several parameters, including random factors, such as primary side and leakage inductance, transistor output capacitance, and PCB (Printed Circuit Board) layout issues, which cannot be precisely determined. This means that the overvoltage must be verified experimentally.

The transformer turns ratio between the auxiliary winding ${\mathrm{L}}_3$ and the secondary winding ${\mathrm{L}}_2$ (${\mathrm{N}}_{\mathrm{A}}/{\mathrm{N}}_{\mathrm{S}}$) depends on the ASIC voltage supply range. Because fast charging is a heavy load, a relatively high overvoltage ${\mathrm{V}}_{\mathrm{DS}.\mathrm{over}}$ can be expected, and this must be taken into consideration. With the minimum, ${\mathrm{V}}_{\mathrm{DD}.\min }$, and maximum, ${\mathrm{V}}_{\mathrm{DD}.\max }$, voltages the auxiliary winding can be calculated from:

$${\mathrm{V}}_{\mathrm{DD}.\min }=\frac{{\mathrm{N}}_{\mathrm{A}}}{{\mathrm{N}}_{\mathrm{S}}}\times \left({\mathrm{V}}_{\mathrm{out}.\min }+{\mathrm{V}}_{\mathrm{F}}+\frac{{\mathrm{N}}_{\mathrm{S}}}{{\mathrm{N}}_{\mathrm{P}}}\times {\mathrm{V}}_{\mathrm{DS}.\mathrm{over}}\right)-{\mathrm{V}}_{\mathrm{F}.\mathrm{aux}}$$

(9)

$${\mathrm{V}}_{\mathrm{DD}.\max }=\frac{{\mathrm{N}}_{\mathrm{A}}}{{\mathrm{N}}_{\mathrm{S}}}\times \left({\mathrm{V}}_{\mathrm{out}.\mathrm{nom}}+{\mathrm{V}}_{\mathrm{F}}+\frac{{\mathrm{N}}_{\mathrm{S}}}{{\mathrm{N}}_{\mathrm{P}}}\times {\mathrm{V}}_{\mathrm{DS}.\mathrm{over}}\right)-{\mathrm{V}}_{\mathrm{F}.\mathrm{aux}}$$

(10)

where ${\mathrm{V}}_{\mathrm{F}.\mathrm{aux}}$ is the forward voltage drop across the diode (${\mathrm{D}}_4$, Figure 3B).

3.4. Design of the Transformer

According to the time periods shown in Figure 3E, the sum of the primary side (transistor ${\mathrm{Q}}_1$) and the secondary side (rectifier ${\mathrm{D}}_4$) conduction time at point B (Figure 3D), i.e., 50% of the output voltage ${\mathrm{V}}_{\mathrm{out}.\mathrm{nom}}$, is given by:

$${\mathrm{t}}_{\mathrm{ON}.\mathrm{B}}+{\mathrm{t}}_{\mathrm{DIS}.\mathrm{B}}=\frac{\frac{1}{{\mathrm{f}}_{\mathrm{S}}}-{\mathrm{t}}_{\mathrm{OFF}.\mathrm{B}}}{\left(1+\frac{{\mathrm{N}}_{\mathrm{S}}}{{\mathrm{N}}_{\mathrm{P}}}\times \frac{{\mathrm{V}}_{\mathrm{DC}.\min .\mathrm{B}}}{0.5\times {\mathrm{V}}_{\mathrm{out}.\min }+{\mathrm{V}}_{\mathrm{F}.\mathrm{aux}}}\right)}\times \left(1+\frac{{\mathrm{N}}_{\mathrm{S}}}{{\mathrm{N}}_{\mathrm{P}}}\times \frac{{\mathrm{V}}_{\mathrm{DC}.\min .\mathrm{B}}}{0.5\times {\mathrm{V}}_{\mathrm{out}.\min }+{\mathrm{V}}_{\mathrm{F}.\mathrm{aux}}}\right)$$

(11)

where ${\mathrm{V}}_{\mathrm{DC}.\min .\mathrm{B}}$ is the minimum input voltage at point B.

From here, the sum of ${\mathrm{t}}_{\mathrm{ON}.\mathrm{B}}+{\mathrm{t}}_{\mathrm{DIS}.\mathrm{B}}$ is derived as:

$${\mathrm{t}}_{\mathrm{ON}.\mathrm{B}}+{\mathrm{t}}_{\mathrm{DIS}.\mathrm{B}}=\frac{1}{{\mathrm{f}}_{\mathrm{S}}}-{\mathrm{t}}_{\mathrm{OFF}.\mathrm{B}}$$

(12)

where ${\mathrm{f}}_{\mathrm{s}}$ is the switching frequency. The primary transformer inductance, ${\mathrm{L}}_{\mathrm{m}}$, is given by:

$${\mathrm{L}}_{\mathrm{m}}=\frac{{\left({\mathrm{V}}_{\mathrm{in}.\mathrm{B}\times }{\mathrm{t}}_{\mathrm{ON}.\mathrm{B}}\right)}^2\times {\mathrm{f}}_{\mathrm{S}}}{2\times {\mathrm{P}}_{\mathrm{in}.\mathrm{nom}.\mathrm{B}}}.$$

(13)

The maximum primary side peak current, ${\mathrm{I}}_{\mathrm{DS}.\mathrm{pk}}$, (Drain-Source) is given by:

$${\mathrm{I}}_{\mathrm{DS}.\mathrm{pk}}=\sqrt{\frac{2\times {\mathrm{P}}_{\mathrm{in}.\mathrm{nom}}}{{\mathrm{L}}_{\mathrm{m}}\times {\mathrm{f}}_{\mathrm{s}}}}.$$

(14)

The minimum number of turns required to avoid core saturation is given by:

$${\mathrm{N}}_{\mathrm{p}.\min }=\frac{{\mathrm{L}}_{\mathrm{m}}\times {\mathrm{I}}_{\mathrm{DS}.\mathrm{pk}}}{{\mathrm{B}}_{\mathrm{sat}}\times {\mathrm{A}}_{\mathrm{e}}}$$

(15)

where ${\mathrm{B}}_{\mathrm{sat}}$ is the flux density (T), and ${\mathrm{A}}_{\mathrm{e}}$ is the cross-sectional area $({\mathrm{m}}^2)$.

At point C, the converter operates in discontinuous conducting mode and the ON $({\mathrm{t}}_{\mathrm{ON}.\mathrm{C}})$ and OFF $({\mathrm{t}}_{\mathrm{OFF}.\mathrm{C}})$ times at this point must be checked according to:

$${\mathrm{t}}_{\mathrm{ON}.\mathrm{C}}=\frac{1}{{\mathrm{V}}_{\mathrm{bus}.\min .\mathrm{C}}}\times \sqrt{\frac{2\times {\mathrm{P}}_{\mathrm{in}.\mathrm{C}}\times {\mathrm{L}}_{\mathrm{m}}}{{\mathrm{f}}_{\mathrm{s}.\mathrm{r}}}}$$

(16)

$${\mathrm{t}}_{\mathrm{OFF}.\mathrm{C}}=\frac{1}{{\mathrm{f}}_{\mathrm{s}.\mathrm{r}}}-{\mathrm{t}}_{\mathrm{ON}.\mathrm{C}}\left(1+\frac{{\mathrm{N}}_{\mathrm{P}}}{{\mathrm{N}}_{\mathrm{S}}}\times \frac{{\mathrm{V}}_{\mathrm{in}.\min .\mathrm{C}}}{{\mathrm{V}}_{\mathrm{out}.\min }+{\mathrm{V}}_{\mathrm{F}}}\right)$$

(17)

where ${\mathrm{f}}_{\mathrm{s}.\mathrm{r}}$ is the switching frequency after its reduction (Figure 3B).

The transformer turns ratio between the auxiliary winding ${\mathrm{N}}_{\mathrm{A}}$ and the secondary winding ${\mathrm{N}}_{\mathrm{S}}$ depends on the supply voltage (${\mathrm{V}}_{\mathrm{DD}}$) of the ASIC used. As the voltage on the auxiliary winding varies with the output load, it is important to operate within the permissible voltage range. In the case that the voltage ${\mathrm{V}}_{\mathrm{DD}}$ drops down below the minimum threshold, ${\mathrm{V}}_{\mathrm{DD}.\min }$, the converter must stop working. The following condition must be satisfied:

$${\mathrm{V}}_{\mathrm{DD}.\min }=\left(\frac{{\mathrm{N}}_{\mathrm{A}}}{{\mathrm{N}}_{\mathrm{S}}}\left({\mathrm{V}}_{\mathrm{o}}+{\mathrm{V}}_{\mathrm{F}}\right)-{\mathrm{V}}_{\mathrm{F}.\mathrm{aux}}\right)>{\mathrm{V}}_{\mathrm{DD}.\max }+\left(2-3\mathrm{V}\right)$$

(18)

where ${\mathrm{V}}_{\mathrm{DD}.\max }$ is the maximum allowable voltage and $\left(2-3\mathrm{V}\right)$ is a safety merging.

The transformer core, usually ferrite for flyback converters [18,19], must be selected according to the output power. Its selection can be made from the product parameter ${\mathrm{A}}_{\mathrm{E}}{\mathrm{A}}_{\mathrm{W}}$:

$${\mathrm{A}}_{\mathrm{E}}{\mathrm{A}}_{\mathrm{W}}=\left(\frac{{\mathrm{L}}_{\mathrm{m}}\times {\mathrm{I}}_{\mathrm{DS}.\mathrm{pk}}\times {\mathrm{I}}_{\mathrm{DS}.\mathrm{rms}}\times {10}^4}{{\mathrm{B}}_{\max }\times {\mathrm{K}}_{\mathrm{u}}\times {\mathrm{K}}_{\mathrm{j}}\times {\mathrm{f}}_{\mathrm{S}.\min }}\right)$$

(19)

where ${\mathrm{A}}_{\mathrm{E}}$ is the core cross-sectional area, ${\mathrm{A}}_{\mathrm{W}}$ the window area available for winding, ${\mathrm{K}}_{\mathrm{u}}$ the winding factor (0.25–0.3), ${\mathrm{K}}_{\mathrm{j}}$ the current density coefficient (400–600), ${\mathrm{B}}_{\max }$ the maximum flux density or saturation flux density of the core material, and ${\mathrm{f}}_{\mathrm{S}.\min }$ the minimum frequency.

With a given core size, the primary winding turns, ${\mathrm{N}}_{\mathrm{p}}$, is given by:

$${\mathrm{N}}_{\mathrm{p}}=\frac{{\mathrm{L}}_{\mathrm{m}}\times {\mathrm{I}}_{\mathrm{DS}.\mathrm{pk}}}{{\mathrm{A}}_{\mathrm{E}}\times {\mathrm{B}}_{\max }}.$$

(20)

The wire size can be chosen according to the RMS (Root Mean Square) primary current $2.5-3\mathrm{A}/{\mathrm{mm}}^2$. Multiple strands with diameters $∆\mathrm{d}$ depend on the frequency:

$$∆\mathrm{d}=\sqrt{\frac{1}{\mathsf{\pi }.{\mathrm{f}}_{\mathrm{s}}.{\mathsf{\mu }}_0.\mathsf{\sigma }}}$$

(21)

where: ${\mathsf{\mu }}_0=4\times \mathsf{\pi }\times {10}^{-7}\mathrm{H}/\mathrm{m}$ is the permeability in vacuum and $\mathsf{\sigma }=6\times {10}^7\mathrm{S}/\mathrm{m}$ is the conductivity of the copper. The magnetic air gap length in the core is:

$${\mathrm{l}}_{\mathrm{gap}}={\mathsf{\mu }}_{\mathrm{o}}.{\mathrm{A}}_{\mathrm{E}}.\frac{{\mathrm{N}}_{\mathrm{p}}^2}{{\mathrm{L}}_{\mathrm{m}}}-\frac{{\mathrm{l}}_{\mathrm{c}}}{{\mathsf{\mu }}_{\mathrm{r}}}\approx {\mathsf{\mu }}_{\mathrm{o}}.{\mathrm{A}}_{\mathrm{E}}.\frac{{\mathrm{N}}_{\mathrm{p}}^2}{{\mathrm{L}}_{\mathrm{m}}}$$

(22)

where ${\mathsf{\mu }}_{\mathrm{r}}$ is the relative magnetic permeability of the core material and ${\mathrm{l}}_{\mathrm{c}}$ the core magnetic length.

The stored energy, ${\mathrm{E}}_{\mathrm{st}}$, in the flyback transformer is given from:

$${\mathrm{E}}_{\mathrm{st}}=\frac{1}{2}.{\mathrm{L}}_{\mathrm{m}}.{\mathrm{I}}_{\mathrm{DC}.\mathrm{pk}}^2.{\mathrm{f}}_{\mathrm{s}}.$$

(23)

3.5. Current Sense Resistor

The current sense resistor (${\mathrm{R}}_5$) value is calculated by:

$${\mathrm{R}}_5=\frac{{\mathrm{N}}_{\mathrm{p}}}{\mathrm{K}\times {\mathrm{I}}_{\mathrm{out}}\times {\mathrm{N}}_{\mathrm{s}}}$$

(24)

where K is the design parameter of the ASIC. The voltage divider ${\mathrm{R}}_{11}$ − ${\mathrm{R}}_{12}$ can be calculated from:

$$\frac{{\mathrm{R}}_{11}}{{\mathrm{R}}_{12}}=\frac{{\mathrm{V}}_{\mathrm{out}.\mathrm{nom}}}{{\mathrm{V}}_{\mathrm{ref}}}\times \frac{{\mathrm{N}}_{\mathrm{A}}}{{\mathrm{N}}_{\mathrm{s}}}-1.$$

(25)

The capacitor C6 must be chosen in the range $22÷68\mathrm{pF}$ [19].

3.6. Calculating the Parameters of the Primary Side MOSFET Transistor

The voltage stress of the primary side transistor is given in Figure 4. The Drain-Source primary RMS current, ${\mathrm{I}}_{\mathrm{DS}.\mathrm{rms}}$, is calculated from:

$${\mathrm{I}}_{\mathrm{DS}.\mathrm{rms}}={\mathrm{I}}_{\mathrm{DS}.\mathrm{pk}}\times \sqrt{\frac{{\mathrm{t}}_{\mathrm{ON}}\times {\mathrm{f}}_{\mathrm{s}}}{3}}.$$

(26)

3.7. Calculating the Parameters of the Secondary Side Rectifier

The maximum reverse voltage and the RMS current of the secondary side rectifier are given from:

$${\mathrm{V}}_{\mathrm{F}}={\mathrm{V}}_{\mathrm{out}.\mathrm{nom}}\times \frac{{\mathrm{N}}_{\mathrm{S}}}{{\mathrm{N}}_{\mathrm{P}}}\times {\mathrm{V}}_{\mathrm{in}.\max }$$

(27)

$${\mathrm{I}}_{\mathrm{F}.\mathrm{rms}}={\mathrm{I}}_{\mathrm{DS}.\mathrm{rms}}\times \sqrt{\frac{{\mathrm{V}}_{\mathrm{DC}.\mathrm{in}.\min }}{{\mathrm{V}}_{\mathrm{R}.\mathrm{out}}}}\times \frac{{\mathrm{N}}_{\mathrm{P}}}{{\mathrm{N}}_{\mathrm{S}}}.$$

(28)

Equation (28) is based on ${\mathrm{I}}_{\mathrm{DS}.\mathrm{rms}}$ and the transformer turn ratio.

The relationship between the primary and the secondary side peak current is:

$${\mathrm{I}}_{\mathrm{DS}.\mathrm{pk}}=\frac{{\mathrm{I}}_{\mathrm{F}.\mathrm{pk}}}{{\mathrm{N}}_{\mathrm{p}}}$$

(29)

where ${\mathrm{I}}_{\mathrm{F}.\mathrm{pk}}$ is the secondary side peak current. The dependence between the ideal output current, ${\mathrm{I}}_{\mathrm{out}}$, and ${\mathrm{I}}_{\mathrm{F}.\mathrm{pk}}$ is given by:

$${\mathrm{I}}_{\mathrm{out}}=\frac{1}{2}\times {\mathrm{I}}_{\mathrm{F}.\mathrm{pk}}\times \frac{{\mathrm{t}}_{\mathrm{ON}}}{{\mathrm{t}}_{\mathrm{s}}}.$$

(30)

3.8. Design of the Clamping Systems

The parasitic components, such as leakage inductance ${\mathrm{L}}_{\mathrm{LK}}$, secondary leakage inductance ${\mathrm{L}}_{\mathrm{LKS}}$, output MOSFETs capacitance ${\mathrm{C}}_{\mathrm{oss}}$, and secondary rectifier capacitance ${\mathrm{C}}_{\mathrm{DS}}$, are analysed [26,27,28] and included in this design procedure.

The primary side RCD clamping circuit (${\mathrm{R}}_2$, ${\mathrm{C}}_1$, ${\mathrm{D}}_1$) prevents the excessive voltage spike which results from the transformer leakage inductance (${\mathrm{L}}_{\mathrm{LK}}$). The maximum voltage stress of the MOSFET is given by Equation (7). The previously considered safety voltage margin of 15% shows that the clamping system must restrict the voltage spike in this range. The peak clamping current is given from:

$${\mathrm{I}}_{\mathrm{CL}.\mathrm{pk}}=\sqrt{{\left(\frac{2.{\mathrm{P}}_{\mathrm{IN}.\mathrm{A}}}{{\mathrm{L}}_{\mathrm{m}}.{\mathrm{f}}_{\mathrm{s}}}\right)}^2-\frac{{\mathrm{C}}_{\mathrm{oss}}}{{\mathrm{L}}_{\mathrm{LK}}}{\mathrm{V}}_{\mathrm{DC}.\mathrm{over}}^2}$$

(31)

where ${\mathrm{C}}_{\mathrm{oss}}$ is the output capacitance of the transistor ${\mathrm{Q}}_1$ taken from the manufacturer’s catalog.

The dissipated power from the RCD network, ${\mathrm{P}}_{\mathrm{RCD}}$, is given by:

$${\mathrm{P}}_{\mathrm{RCD}}=\frac{1}{2}{\mathrm{f}}_{\mathrm{S}}.{\mathrm{L}}_{\mathrm{LK}}.{\mathrm{I}}_{\mathrm{CL}.\mathrm{pk}}^2.\frac{{\mathrm{V}}_{\mathrm{R}.\mathrm{out}}+{\mathrm{V}}_{\mathrm{DC}.\mathrm{over}}}{{\mathrm{V}}_{\mathrm{DC}.\mathrm{over}}}.$$

(32)

The resistance ${\mathrm{R}}_2$ and the capacitor ${\mathrm{C}}_1$ are given by:

$${\mathrm{R}}_2=\frac{{\left({\mathrm{V}}_{\mathrm{R}.\mathrm{out}}+{\mathrm{V}}_{\mathrm{DS}.\mathrm{over}}\right)}^2}{{\mathrm{P}}_{\mathrm{RCD}}}$$

(33)

$${\mathrm{C}}_1>\frac{{\mathrm{V}}_{\mathrm{R}.\mathrm{out}}+{\mathrm{V}}_{\mathrm{DS}.\mathrm{over}}}{{\mathrm{V}}_{\mathrm{rip}}.{\mathrm{R}}_{\mathrm{RCD}}.{\mathrm{f}}_{\mathrm{s}}}.$$

(34)

3.9. Design of the Output Filter

The peak-to-peak ripple, $∆{\mathrm{I}}_{\mathrm{C}.\mathrm{rip}}$, of the output capacitor (${\mathrm{C}}_5$) is calculated from:

$$∆{\mathrm{I}}_{\mathrm{C}.\mathrm{rip}}=\frac{{\mathrm{N}}_{\mathrm{p}}}{{\mathrm{N}}_{\mathrm{s}}}{\mathrm{I}}_{\mathrm{DS}.\mathrm{pk}},$$

(35)

and the voltage ripple on the output from:

$$∆{\mathrm{V}}_{\mathrm{out}.\mathrm{rip}}=\frac{{\mathrm{t}}_{\mathrm{DIS}.\mathrm{A}}}{2.{\mathrm{C}}_5}\times \frac{{\left(∆{\mathrm{I}}_{\mathrm{C}.\mathrm{rip}}-{\mathrm{I}}_{\mathrm{out}.\mathrm{nom}}\right)}^2}{∆{\mathrm{I}}_{\mathrm{C}.\mathrm{rip}}}+∆{\mathrm{I}}_{\mathrm{C}.\mathrm{rip}}\times {\mathrm{R}}_{\mathrm{ESR}}$$

(36)

where ${\mathrm{R}}_{\mathrm{ESR}}$ is the equivalent series resistor of ${\mathrm{C}}_5$.

3.10. Design of the RC Snubber

The resistor ${\mathrm{R}}_7$ is given by:

$${\mathrm{R}}_7=\sqrt{\frac{{\mathrm{L}}_{\mathrm{LKS}}}{{\mathrm{C}}_{\mathrm{DS}}}}$$

(37)

where ${\mathrm{L}}_{\mathrm{LKS}}$ is the secondary leakage inductance and ${\mathrm{C}}_{\mathrm{DS}}$ is the secondary side rectifier parasitic capacitance.

Normally ${\mathrm{C}}_4$ is 2–3 times ${\mathrm{C}}_{\mathrm{DS}}$.

4. Experimental Results

Based on the presented design procedure, an experimental converter was designed, built, and tested. Its parameters are presented in

Table 1. Parameters of the experimentally tested converter.

Parameter	Value
${\mathrm{V}}_{\mathrm{in}.\min }$	350 V
${\mathrm{V}}_{\mathrm{in}.\max }$	400 V
${\mathrm{V}}_{\mathrm{in}.\mathrm{nom}}$	380 V
${\mathrm{V}}_{\mathrm{out}.\max }$	5 V
${\mathrm{I}}_{\mathrm{out}.\max }$	10 A
${\mathrm{f}}_{\mathrm{s}}$	66 kHz

.

The experimental results are presented as follows:

• Figure 5. The oscillogram shows the primary side of the converter, where: (1) is the voltage Drain-Source, ${\mathrm{V}}_{\mathrm{DS}}$, across the MOSFET with specific oscillation after full energy transfer; (2) is the primary side current, ${\mathrm{I}}_{\mathrm{pk}}$, through ${\mathrm{L}}_1$, ${\mathrm{Q}}_1$, and ${\mathrm{R}}_5$; (3) is the secondary side current through the rectifier, which represents the energy transfer at the zero point; and (4) is the voltage on the auxiliary winding, which repeats the shape of (1) but with a smaller amplitude.
• Figure 6 shows the secondary side of the converter, where (1) and (2) are the secondary side current and voltage, respectively, over ${\mathrm{D}}_4$; (3) is the voltage on the auxiliary winding; and (4) is the output voltage.
• Figure 7 shows the primary side of the converter under an open circuit. Although the tested battery charger is not supposed to work under this condition, this experiment shows the process of reducing the switching frequency from 50–100 kHz to 20–35 kHz (Figure 3D).
• The maximum obtained efficiency of the converter is 84% as shown in Figure 8.
• Some specific parameters are given in Figure 9. The primary side current has a peak value immediately after the transistor is turned on. When it is turned off, its process has a typical oscillation in ${\mathrm{V}}_{\mathrm{DS}}$. Although these features are assumed to be normal, they have to be considered alongside the control system parameters. Two delay times are necessary for its correct operation, respectively, in ranges 100–200 ns and 300–400 ns as Figure 10 shows.

A photo of the experimental converter and a battery string is shown in Figure 10.

5. Conclusions

In this paper, the essential points of the design procedure of a flyback converter with primary current sensing is presented. The same converter can be used as part of a BMS for active cell balancing. From the obtained results, the following conclusions can be formulated:

• The presented design procedure for a DC-DC flyback converter is correct and it can be used as part of the overall design of the converter.
• The schematic of the flyback converter with primary current sensing (Figure 3B) can be used as a battery charger and is particularly suitable for battery equalisation as part of a BMS. The schematic works under constant current and constant voltage (Figure 3D) and meets the battery charging requirements (Figure 2).
• The efficiency of the circuit reaches 82–84% for a low-voltage output converter (Figure 8). If fast charging of a cell is necessary, the converter must be designed to work at the working point A from the output V-I characteristic (Figure 3 D).
• The experimental verification shown in Figure 5, Figure 6 and Figure 7 entirely meets the theoretical analysis shown in Figure 3.
• As Figure 9 shows, the two delay times in the turn-on and turn-off processes are necessary.