Next Article in Journal
Introduction to the Special Issue on Intelligent and Cooperative Vehicles
Next Article in Special Issue
Scalable Fabrication of 2D Semiconducting Crystals for Future Electronics
Previous Article in Journal
A Technique for Mitigating Thermal Stress and Extending Life Cycle of Power Electronic Converters Used for Wind Turbines
Previous Article in Special Issue
Towards the Realization of Graphene Based Flexible Radio Frequency Receiver
 
 
Font Type:
Arial Georgia Verdana
Font Size:
Aa Aa Aa
Line Spacing:
Column Width:
Background:
Article

Electrical Compact Modeling of Graphene Base Transistors

by
Sébastien Frégonèse
1,*,
Stefano Venica
2,
Francesco Driussi
2 and
Thomas Zimmer
1
1
CNRS and University of Bordeaux, IMS UMR 5218, Talence 33400, France
2
DIEGM—University of Udine via delle Scienze, 208 22100 Udine, Italy
*
Author to whom correspondence should be addressed.
Electronics 2015, 4(4), 969-978; https://doi.org/10.3390/electronics4040969
Submission received: 30 July 2015 / Revised: 22 October 2015 / Accepted: 2 November 2015 / Published: 18 November 2015
(This article belongs to the Special Issue Two-Dimensional Electronics - Prospects and Challenges)

Abstract

:
Following the recent development of the Graphene Base Transistor (GBT), a new electrical compact model for GBT devices is proposed. The transistor model includes the quantum capacitance model to obtain a self-consistent base potential. It also uses a versatile transfer current equation to be compatible with the different possible GBT configurations and it account for high injection conditions thanks to a transit time based charge model. Finally, the developed large signal model has been implemented in Verilog-A code and can be used for simulation in a standard circuit design environment such as Cadence or ADS. This model has been verified using advanced numerical simulation.

1. Introduction

The physical properties of graphene are of highest interest for electronic applications and its properties have been used by several research groups to develop radio frequency (RF) and microwave Graphene Field Effect Transistors (GFET) [1,2,3]. Unfortunately, the lack of energy bandgap in graphene induces poor DC electrical characteristics and GFETs are still under evaluation [4] and optimization. Also, new transistor concepts are explored such as the Graphene Barristor [5] or the hot electron graphene base transistor (GBT) [6,7]. As explained by the inventors [7], compared to the GFET where the carrier transport is within the plane of the graphene sheet, “the GBT is based on a vertical arrangement of emitter (E), base (B), and collector (C), just like a hot electron transistor or a vacuum triode”. This vertical stack considers an emitter-base and a base-collector energy barrier that are controlled by the graphene base and the collector potentials. In the off-state, the carriers face a large barrier potential, while, in the on-state, this barrier vanishes when a sufficient positive bias is applied to the base and collector. The transistor concept has been demonstrated in [7] and it is under optimization to improve the GBT electrical performance [8].
Venica et al. and Driussi et al. [9,10] have developed physics based device simulators with different level of accuracy in order to improve the understanding of the GBT operation, and to optimize the transistor as a single element [11]. A small signal model has been proposed in [6]. In order to evaluate this transistor in circuit configuration, a large signal compact model is necessary.
In this paper, we propose a large signal compact model, whose verification is done by means of comparison with numerical simulation [9,11]. The paper is organized in two parts: the developed transistor compact model is described in the first part; then the second part compares compact model results to numerical simulation data.

2. Compact Model

The GBT transistor structure is presented in Figure 1. The vertical stack comprises the emitter, the emitter-base region EBi, the graphene base, the base-collector region BCi and the collector. The barrier potential height of the EBi and BCi regions controls the carrier transport mode such as tunneling or thermionic transport. Hence, the choice of the material used for the EBi and BCi region is of major importance. EBi and BCi can be either an insulator material such as SiO2 or high-k dielectrics to exploit a tunneling transport [6] or a semiconductor such as Ge or Si to foster a thermionic current [12].
Figure 1. Schematic representation of the transistor structure.
Figure 1. Schematic representation of the transistor structure.
Electronics 04 00969 g001
According to the transistor structure (see Figure 1), the following equivalent circuit is proposed (see Figure 2). The extrinsic circuit is composed of three access resistances RB, RC, RE. Concerning the intrinsic part, the core of the model is based on the self-consistent calculation of the internal base potential VBi, which is a function of the charge in the emitter, the collector and within the graphene layer. These charges are modeled through different capacitances. First, CQ capacitance models the quantum capacitance of the graphene layer, while CBE0 and CBC0 describe the EBi and BCi capacitances, respectively. Finally, CDC and CDE are diffusion capacitances that take into account the additional charge due to carrier transport in the EBi and BCi regions. These capacitances are of interest for medium to high injection conditions [9]. Finally, two diodes IBE and IBC are modeling the base-emitter and base-collector current, respectively, and one voltage controlled current source ICE is introduced for the collector-emitter transfer current. Each element is described in the next section.
Figure 2. Equivalent circuit of the Graphene Base Transistor (GBT) electrical compact model.
Figure 2. Equivalent circuit of the Graphene Base Transistor (GBT) electrical compact model.
Electronics 04 00969 g002

2.1. Self-Consistent Calculation of the Internal Base Potential

The charge in the graphene layer can be computed by combining the specific density of states of graphene with the Fermi approach for the carrier distribution. Assuming that the potential drop into the graphene base |VBBi| ≫ kT/q (k is the Boltzmann constant, T is the absolute temperature and q is the elementary charge), the total charge density can be approximated as follows [13]:
Q G q ( q 2 π ( v f ) 2 | V B B i | V B B i ) = 1 2 C Q V B B i
with ћ the reduced Planck constant, vf the Fermi velocity and C Q = κ | V B B i | , κ = 2 q 2 π ( v f ) 2 .
Introducing the graphene charge in the equivalent circuit, the internal base potential can be calculated by solving the following equation:
Q G + C B C V B i C + C B E V B i E = 0
where VBiC = VBiVC, VBiE = VBiVE, CBC = CBC0 + CDC, CBE = CBE0 + CDE (see Figure 2) and C B C 0 = ε B C A E e B C , C B E 0 = ε B E A E e B E are the oxide capacitances. eBC and eBE are the insulator thicknesses of EBi and BCi regions, respectively, and εBE and εBC are the associated permittivity. AE is the emitter area. The diffusion capacitances CDE and CDC will be described in Section II-C.
Substituting Equation (1) in Equation (2), the VBBi potential is introduced in the equation:
1 2 κ | V B B i | V B B i + C B C ( V B B i + V B C ) + C B E ( V B B i + V B E ) = 0
Equation (3) is a second order polynomial that can be solved and gives the following solution [6]:
V B B i = ( C B C + C B E ) + ( C B C + C B E ) 2 2 κ ( C B C V B C + C B E V B E ) ± κ

2.1.1. Description of Diodes and Transfer Current Source

As described above, the EBi and BCi material can be either insulator or semiconductor and the charge transport can be dominated by tunneling emission or thermionic transport. In order to obtain a versatile compact model, the diode and transfer current source equations will be based on flexible and simple relationships.
For the base-emitter and base-collector tunnel or semiconductor-graphene diodes, an exponential equation is used (see [14]) and modified to gain in adaptability:
I B E = A E J S B E exp ( V B i E ϕ B E B B E )
I B C = A E J S B C exp ( V B i C ϕ B C B B C )
where JSBE and JSBC are the corresponding saturation currents, ϕBE and ϕBC are the barrier heights and BBE and BBC are fitting parameters of the slope of the exponential function.
For the transfer current source, a modified Landauer based equation is used [15].
I C E = A E J S F [ ln ( 1 + exp ( V B i E ϕ B E B B E ) ) ln ( 1 + exp ( V B i C ϕ B C B B C ) ) ] × f C E f C E = { 0 i f V C E < ϕ C E 1 i f V C E > ϕ C E
JSF is a saturation current and the fCE parameter allows zeroing the current if the collector-emitter barrier ϕCE is too high to be crossed by the carrier at low VCE. ϕCE is used as a fitting parameter for the low VCE bias regime.

2.1.2. Medium to High Current Injection Effects

At medium to high current conditions, the charge injected through the transfer current in the EBi and BCi junctions needs to be taken into account. This charge will modify the charge equilibrium in the intrinsic transistor and will induce a shift of the internal base potential. Hence, as suggested in Figure 2, diffusion capacitances are included in the equivalent circuit and this will affect the potential drop VBBi through the Equation (4).
The diffusion charge within the two regions is computed by considering a transit time approach. At medium injection level, the charge can be approximated by
Q D C = τ C B I C E , Q D E = τ E B I C E
τ C B , τ E B are the transit times of the BCi and EBi region at medium injection, respectively. At high injection, an additional charge Δ Q K [9,12], with respect to QDE appears when the transfer current ICE overpass the critical current ICK:
Δ Q K = Δ τ K ( I C E I C K ) γ I C E
Δ τ K is the additive transit time at high injection and γ is a fitting parameter.
Combining Equations (8) and (9) and deriving the equation, the related capacitance can be deduced:
C D C = d Q D C d V C E , C D E = d ( Q D E + Q K ) d V B i E
These elements can be either derived analytically or directly computed using a derivative function in Verilog language.

2.2. Comparison to Numerical Simulation

In order to validate our model and to demonstrate its physical basis, a comparison between physics-based numerical simulations and our compact model is provided. The 1-D numerical model of [9] solves the electrostatics of the GBT self-consistently with the calculated tunneling current and estimates the transit frequency fT. Concerning the currents, since the physical origin of the base current is still unclear and debated [7,16], a perfectly transparent graphene layer is assumed and the base current is neglected. Hence, we assume a priori that the collector current is the current due to electrons injected from the emitter and, consistently, crossing the whole device.
The simulated device assumes that the EBi and BCi layers are made of two insulators [11]: the EBi region has a 2 nm high permittivity insulator (εr = 25) while the BCi region has a 12 nm oxide with εr = 2.5. Only the intrinsic device is simulated and one would need to consider parasitic elements to have a realistic circuit simulation.
First, a comparison between numerical simulations and compact model simulations of the calculated graphene base charge is provided in Figure 3. Despite a deviation at large ICE mainly due to different modeling approaches for the high injection effects (model in [9] solves the potential along the device self-consistently with the traveling electrons), a fairly good agreement is found between the two models. This verifies the adequate calculation of the intrinsic base potential VBi by the compact model (see Figure 4).
The transfer characteristics of the device are simulated in Figure 5. At low injection condition, a similar behavior is observed despite a small disagreement. A good agreement is observed at medium to high electron injection levels. Figure 6, instead, shows the associated transconductance, which is of major importance for RF circuit simulation. A very good agreement is observed for low and medium bias, a reasonable agreement can be found for high bias. Finally, Figure 7 compares the output curves confirming a good matching between the two models. It should be underlined that the slope gCE (see Figure 8) is properly modeled; this is mandatory to correctly model the voltage gain of an amplifier circuit.
Figure 3. Charge QG versus ICE curves for different VCB (2, 3, 4, 5 V), numerical simulation and compact model simulation.
Figure 3. Charge QG versus ICE curves for different VCB (2, 3, 4, 5 V), numerical simulation and compact model simulation.
Electronics 04 00969 g003
Figure 4. Graphene Fermi potential versus VBE curves for different VCB (2, 3, 4, 5 V), numerical simulation and compact model simulation.
Figure 4. Graphene Fermi potential versus VBE curves for different VCB (2, 3, 4, 5 V), numerical simulation and compact model simulation.
Electronics 04 00969 g004
Figure 5. ICE versus VBE curves for different VCB values (2, 3, 4, 5 V) simulated with the numerical model and the compact model.
Figure 5. ICE versus VBE curves for different VCB values (2, 3, 4, 5 V) simulated with the numerical model and the compact model.
Electronics 04 00969 g005
Figure 6. gM versus IC curves for different VCB (2, 3, 4, 5 V) simulated with the numerical model and the compact model.
Figure 6. gM versus IC curves for different VCB (2, 3, 4, 5 V) simulated with the numerical model and the compact model.
Electronics 04 00969 g006
Figure 7. ICE versus VCE curves for different VBE values (0.75, 1, 1.25 V), numerical simulation and compact model simulation.
Figure 7. ICE versus VCE curves for different VBE values (0.75, 1, 1.25 V), numerical simulation and compact model simulation.
Electronics 04 00969 g007
Figure 8. gCE versus VCE curves for different VBE values (0.75, 1, 1.25 V), numerical simulation and compact model simulation.
Figure 8. gCE versus VCE curves for different VBE values (0.75, 1, 1.25 V), numerical simulation and compact model simulation.
Electronics 04 00969 g008
In addition, S parameter simulations have been performed to extract the transit frequency; fT is then compared to numerical simulation results (see Figure 9). A good agreement is observed up to peak fT, which is the optimum bias condition for circuit applications. At higher current levels, a deviation is observed. Again this can be due to the different modeling strategies adopted to model the high current effects in the GBT.
Table 1 summarizes the used compact model parameters. eBC, eBE, εBE and εBC are those used in the physics based simulations, while the others have been extracted by fitting in Figure 3, Figure 4, Figure 5, Figure 6, Figure 7 and Figure 8.
Table 1. Parameters used in the compact model simulation.
Table 1. Parameters used in the compact model simulation.
Parameter Name/UnitParameter Value
JSF (mA/µm2)437
BBE (mV)35.3
BBC (mV)94.2
ΦCE (V)0.57
eBE (nm)2
eBC (nm)12
εBE25
εBC2.5
τBE (fs)0.35
τBC (fs)6
ΦBE (V)0.893
ΦBC (V)1.2
γ1.55
κ (µF/cm²)25
ICK (A/µm²)0.7
ΔτK (fs)8 × 10−3
Figure 9. fT versus VBE curves for different VCB (2, 3, 4, 5 V), numerical simulation and compact model simulation.
Figure 9. fT versus VBE curves for different VCB (2, 3, 4, 5 V), numerical simulation and compact model simulation.
Electronics 04 00969 g009

3. Conclusions

We have developed a compact large signal model for GBT devices. Our model represents a good trade-off in terms of physics soundness and implementation complexity. Its accuracy relies on a self-consistent base potential calculation and a physics based charge model associated with an empirical and versatile transfer current equation. The model has been directly implemented in Verilog-A code. Hence, this model can be used to predict circuit performances based on GBT devices. Finally, the compact model accuracy has been verified by comparison with a physics-based electrical model, showing a good agreement with the numerical simulations.

Acknowledgments

This work is part of the GRADE project (317839) supported by the European Commission through the Seventh Framework Program for Research and Technological Development. The authors thank P. Palestri for fruitful discussions.

Author Contributions

S.F. and T.Z. developed the compact model equations. S.V., F.D. developed and performed the physics based simulations. All authors discussed the data and interpretation, and contributed during the writing of the manuscript. All authors have given approval to the final version of the manuscript.

Conflicts of Interest

The authors declare no conflict of interest.

References

  1. Lin, Y.-M.; Farmer, D.B.; Jenkins, K.A.; Wu, Y.; Tedesco, J.; Myers-Ward, R.; Eddy, C.; Gaskill, D.; Dimitrakopoulos, C.; Avouris, P. Enhanced Performance in Epitaxial Graphene FETs with Optimized Channel Morphology. Electron. Device Lett. IEEE 2011, 32, 1343–1345. [Google Scholar] [CrossRef]
  2. Wu, Y.Q.; Farmer, D.B.; Valdes-Garcia, A.; Zhu, W.J. Record High RF Performance for Epitaxial Graphene Transistors. In Proceedings of the IEEE International on Electron Devices Meeting (IEDM), Washington, DC, USA, 5–7 December 2011.
  3. Liao, L.; Lin, Y.; Bao, M.; Cheng, R.; Bai, J.; Liu, Y.; Qu, Y.; Wang, K.L.; Huang, Y.; Duan, X.; et al. High-speed graphene transistors with a self-aligned nanowire gate. Nature 2010, 467, 305–308. [Google Scholar] [CrossRef] [PubMed]
  4. Schwierz, F. Graphene Transistors: Status, Prospects, and Problems. In Proceedings of the IEEE, Ilmenau, Germany, 22 May 2013; Volume 101, pp. 1567–1584.
  5. Yang, H.; Heo, J.S.; Park, S.; Song, H.J.; Seo, D.H.; Byun, K.-E.; Kim, P.; Yoo1, K.; Chung, H.-J.; Kim, K. Graphene Barristor, a Triode Device with a Gate-Controlled Schottky Barrier. Science 2012, 336, 1140–1143. [Google Scholar] [CrossRef] [PubMed]
  6. Mehr, W.; Abrowski, J.; Scheytt, C.; Lippert, G.; Xie, Y.-H.; Lemme, M.C.; Ostling, M.; Lupina, G. Vertical graphene base transistor. IEEE Electron Device Lett. 2012, 33, 691–693. [Google Scholar] [CrossRef]
  7. Vaziri, S.; Lupina, G.; Henke, C.; Smith, A.D.; Östling, M.; Dabrowski, J.; Lippert, G.; Mehr, W.; Lemme, M.C. A Graphene-Based Hot Electron Transistor. Nano Lett. 2013, 13, 1435–1439. [Google Scholar] [CrossRef] [PubMed]
  8. Vaziri, S.; Belete, M.; Litta, E.D.; Smith, A.D.; Lupina, G.; Lemme, M.; Östling, M. Bilayer Insulator Tunnel Barriers for Graphene-Based Vertical Hot-electron Transistors. Nanoscale 2015, 7, 13096–13104. [Google Scholar] [CrossRef] [PubMed]
  9. Venica, S.; Driussi, F.; Palestri, P.; Esseni, D.; Vaziri, S.; Selmi, L. Simulation Of DC and RF performance of the graphene base transistor. IEEE Trans. Electron Devices 2014, 61, 2570–2576. [Google Scholar]
  10. Driussi, F.; Palestri, P.; Selmi, L. Modelling, simulation and design of the vertical Graphene Base Transistor. Microelectron. Eng. 2013, 109, 338–341. [Google Scholar] [CrossRef]
  11. Venica, S.; Driussi, F.; Palestri, P.; Selmi, L. Graphene Base Transistors with optimized emitter and dielectrics. In Proceedings of the Microelectronics, Electronics and Electronic Technology Conference, Opatija, Croatia, 26–30 May 2014; pp. 39–44.
  12. Di Lecce, V.; Grassi, R.; Gnudi, A.; Gnani, E.; Reggiani, S.; Baccarani, G. Graphene-base heterojunction transistor: An attractive device for terahertz operation. IEEE Trans. Electron Devices 2013, 60, 4263–4268. [Google Scholar] [CrossRef]
  13. Xu, H.; Zhang, Z.; Peng, L.-M. Measurements and microscopic model of quantum capacitance in graphene. Appl. Phys. Lett. 2011, 98, 1–3. [Google Scholar] [CrossRef]
  14. Vaziri, S.; Belete, M.; Litta, E.D.; Smith, A.D.; Lupina, G.; Lemme, M.C.; Östlinga, M. Bilayer insulator tunnel barriers for graphene-based vertical hot-electron transistors. Nanoscale 2015, 7, 13096–13104. [Google Scholar] [CrossRef] [PubMed]
  15. Ferry, D.K.; Goodnick, S.M. Transport in Nanostructures; Cambridge University Press: Cambridge, UK, 1997. [Google Scholar]
  16. Zeng, C.; Song, E.B.; Wang, M.; Lee, S.; Torres, C.M.; Tang, J.; Weiller, B.H.; Wang, K.L. Vertical graphene-base hot-electron transistor. Nano Lett. 2013, 13, 1435–1439. [Google Scholar] [CrossRef] [PubMed]

Share and Cite

MDPI and ACS Style

Frégonèse, S.; Venica, S.; Driussi, F.; Zimmer, T. Electrical Compact Modeling of Graphene Base Transistors. Electronics 2015, 4, 969-978. https://doi.org/10.3390/electronics4040969

AMA Style

Frégonèse S, Venica S, Driussi F, Zimmer T. Electrical Compact Modeling of Graphene Base Transistors. Electronics. 2015; 4(4):969-978. https://doi.org/10.3390/electronics4040969

Chicago/Turabian Style

Frégonèse, Sébastien, Stefano Venica, Francesco Driussi, and Thomas Zimmer. 2015. "Electrical Compact Modeling of Graphene Base Transistors" Electronics 4, no. 4: 969-978. https://doi.org/10.3390/electronics4040969

Article Metrics

Back to TopTop