- freely available
Electronics 2013, 2(4), 332-367; doi:10.3390/electronics2040332
Published: 30 September 2013
Abstract: Excellent electrical performance and extreme sensitivity to chemical species in semiconducting Single-Walled Carbon NanoTubes (s-SWCNTs) motivated the study of using them to replace silicon as a next generation field effect transistor (FET) for electronic, optoelectronic, and biological applications. In addition, use of SWCNTs in the recently studied flexible electronics appears more promising because of SWCNTs’ inherent flexibility and superior electrical performance over silicon-based materials. All these applications require SWCNT-FETs to have a wafer-scale uniform and reliable performance over time to a level that is at least comparable with the currently used silicon-based nanoscale FETs. Due to similarity in device configuration and its operation, SWCNT-FET inherits most of the variability and reliability concerns of silicon-based FETs, namely the ones originating from line edge roughness, metal work-function variation, oxide defects, etc. Additional challenges arise from the lack of chirality control in as-grown and post-processed SWCNTs and also from the presence of unstable hydroxyl (–OH) groups near the interface of SWCNT and dielectric. In this review article, we discuss these variability and reliability origins in SWCNT-FETs. Proposed solutions for mitigating each of these sources are presented and a future perspective is provided in general, which are required for commercial use of SWCNT-FETs in future nanoelectronic applications.
Single-Walled Carbon NanoTubes (SWCNTs) were first discovered in 1991  and their electronic properties depend on the directions at which two-dimensional graphene stripes are (hypothetically) rolled to make SWCNTs [2,3,4]. When a SWCNT is defined by rolling a graphene layer and by joining any of the solid symbols of Figure 1a with the lattice origin (a1,a2) = (0,0), resultant SWCNT will have metallic properties with no bandgap in the energy vs. density of the state’s relationship (Figure 1b). On the other hand, SWCNTs defined by joining the open symbols of Figure 1a with the lattice origin will have semiconducting properties with bandgaps (Figure 1c,d) that can be expressed as [2,3]:
In Equation (1), d is the diameter of SWCNT and equals √3aC-C/π × √(n2 + nm + m2), (n,m) is the chiral index designating the distance between the open symbols and the lattice origin via chiral vector (Figure 1a), aC-C = 0.142 nm is the C–C bond length, t ~ −3 eV is the C–C bonding energy. SWCNTs with n = m are called armchair nanotubes and always show metallic behavior, whereas SWCNTs with n ≠ m either show metallic behavior for mod (n − m)/3 = 0 or semiconducting behavior for mod (n − m)/3 = 1, 2. SWCNTs with m = 0 are called zigzag nanotubes and the rest with n ≠ m ≠ 0 are called chiral nanotubes.
Semiconducting SWCNTs (s-SWCNTs) are of particular interest for future electronic devices, where s-SWCNTs act as a channel in conventional field effect transistor (FET) configuration. Carrier mobility in such s-SWCNT-FETs can be as high as ~105 cm2/V-s [5,6], which outperforms similar values in current-day FETs. In addition, the ultra-thin s-SWCNT layer that forms the channel of FET offers better electrostatic gate control, hence less short channel effect compared to classical silicon-based FETs . Such ultra-thin layers also offer extreme mechanical flexibility to the resultant electronic device, thereby promoting the best platform for future flexible electronic devices [8,9], which are currently being manufactured using FETs made on thin silicon substrates [10,11]. Use of s-SWCNTs as channels, m-SWCNTs as contacts  and memory elements , SWCNT network [14,15] or single s-SWCNT [16,17] as memory, and CNT fabrics as coaxial cable  may open up the possibility of having “all-CNT” electronics for high performance applications. In addition to electronics, SWCNT-FETs are also considered as chemical-/bio-sensors because of their higher surface-to-volume ratio that reduces response time  and extreme sensitivity [20,21], and their selectivity  to chemical and biological species.
To enable all these applications stated in the last paragraph, SWCNT-FETs and memories not only require superior performance, but also require a controlled level of variability and reliability. Such controllability has to ensure that performance of associated devices does not drop below a certain limit, which can be compensated through circuit design via guard bands [22,23]. Figure 2 schematically explains the extent of guard band that is used in circuit design for handling variability and reliability. Devices have different variability sources that give rise to time-zero variation in device performance around its mean value. In addition, during the operation of the device, its performance degrades over time and such degradation comes with its own statistical variation. Based on this knowledge, circuits are designed with such devices considering that the tail of the performance distribution at the end of intended lifetime will not go beyond a certain limit—thus, the designed circuits are guard-banded against performance variations. As device performance improves via Moore’s law scaling , device design is continuously modified to minimize guard-band such that the devices can be operated at higher performance without compromising the lifetime.
In this review article, we will discuss different aspects of variability and reliability in SWCNT-FETs that will eventually define guard-band in such devices. Section 2 discusses the configurations and performance of SWCNT-FETs that has potential use in future electronics. Section 3 highlights the sources of variability in SWCNT-FETs and the current solutions to control them. Section 4 performs a similar review for the reliability sources. Section 5 summarizes the paper and provides brief guidelines for improving variability and reliability phenomena in SWCNT-FETs based on current understanding of CNT growth conditions and device fabrication challenges.
2. Configurations and Performance of SWCNT-FET
2.1. Device Geometry
For FET applications, SWCNTs are commonly grown in random networks or aligned arrays using metal catalyst placed on SiO2 [9,12,25,26]. Alternately, SWCNTs are drop-casted from solution on SiO2 [27,28,29] or hafnium dioxide (HfO2) [30,31] and assembled in random networks [27,28,29] or parallel arrays [31,32] via coating of self-assembled monolayers on oxides. Bottom-gated FETs with thick SiO2 as gate dielectric and heavily doped silicon as gate are widely used test configurations for SWCNT-FETs. Such bottom-gated structures though are suitable for bio-/chemical-sensing applications [20,21,33], top-gated geometry with thin, high-κ gate dielectric is preferred for high performance electronics [34,35]. (In some novel SWCNT-FETs, local bottom-gating , lateral gating with suspended SWCNTs , and surround-gate geometries  are also used for high performance electronics.) Measurement of SWCNT properties (e.g., conductivity, mobility, contact resistance of individual SWCNTs and their diameter dependence) by applying suitable bias at source, drain, and gate terminals involves fabrication of single SWCNT-FET. Schematic of such a FET in dual-gate (i.e., having top and bottom gate with suitable gate oxides) configuration is shown in Figure 3a. Such single SWCNT-FET, however, cannot provide the amount of current required for different applications, e.g., ~mA per µm of channel width is required for high performance electronics . Current in SWCNT-FETs can be increased either by having a network (Figure 3b) or an aligned array (Figure 3c) of SWCNTs’ bridging sources and drain terminals. Magnitude of current in these configurations depends on the density of SWCNTs (per unit area for network SWCNTs of Figure 3b or per unit width across the length of SWCNTs for aligned SWCNTs of Figure 3c), diameter of SWCNTs, chirality of SWCNTs, and electrostatic coupling on SWCNTs via gate. For network SWCNT-FETs, current additionally depends on the charge transfer efficiency across different SWCNTs in the network [39,40,41].
2.2. Materials for SWCNT-FETs
As mentioned before, SWCNTs are grown on insulating substrates like SiO2, quartz, sapphire, etc. using metal (e.g., Fe, Ni, Co and their alloys) nanoparticles as catalyst. Length, diameter distribution, and chirality of grown SWCNTs vary among the growth methods being used [42,43]. In general, for as-grown SWCNTs, length varies from ~1 µm to several 100 µm, diameter ranges between ~0.7 nm and ~5 nm [26,44,45,46], density is approximately 14–200 per μm2 for network SWCNTs [12,31] and ~2–45 per µm across the length of the SWCNT for aligned SWCNTs [26,31,44,47,48], and chirality varies randomly. Long SWCNTs (>100 µm) are only obtained during chemical vapor deposition (CVD) on stable temperature- (ST-) cut quartz substrates [25,49]. Diameter and chirality of as-grown SWCNTs can be sorted by dissolving SWCNTs in surfactants and then using post-processing techniques like ultra-centrifugation , gel electrophoresis , chromatography . Such solution-processed, sorted SWCNTs can be assembled into a high-density compact film via Langmuir-Blodgett method . However, solution-processing breaks SWCNTs into small segments (~µm or less) and reduces the carrier mobility or conductivity of SWCNTs (down to ~1–20 cm2/V-sec [35,46] with a maximum of ~200–300 cm2/V-sec [28,53]). An alternative approach of maintaining the integrity of SWCNTs in terms of length (up to several hundreds of µm) and carrier mobility (>1000 cm2/V-sec) is to coat horizontally aligned SWCNTs with a molecular film and use thermo-lithography (thermal analogous of photo-lithography) to etch-off m-SWCNTs from the substrate . Remaining s-SWCNTs have a low density; however, there is potential for density improvement via multiple transfers [55,56].
In addition to the requirement of having substrates with high density s-SWCNTs, future electronic devices require appropriate doping in s-SWCNTs to control their conduction. Absence of molecular doping in SWCNTs, however, necessitates the use of metals with lower (higher) work-functions to conduct electrons (holes) through the SWCNTs, hence make n- (p-) type SWCNT-FETs. Palladium (Pd) with work-function of ~5.1 eV is generally used as source/drain contacts for making p-type SWCNT-FETs that allows hole flow from contacts into and out of the SWCNT via Schottky contacts for d < 1 nm SWCNTs and via ohmic contact for d > 1 nm SWCNTs [57,58,59]. Presence of negatively charged hydroxyl (-OH) groups at SWCNTs interface also makes the p-type conduction in SWCNT-FETs easier. N-type or electron conduction in SWCNTs, on the other hand, can be enabled using calcium (Ca) and scandium (Sc) source/drain contacts with work-functions ~3–4 eV [60,61]. In such case, conduction can be further enhanced via electrostatic doping with high-κ oxides [38,62].
2.3. FETs with Single SWCNT
Current-voltage (I-V) characteristics of FETs with single s-SWCNT have reasonably good switching behavior in the measured transfer characteristics (i.e., drain current (Ids) vs. gate voltage (Vg) characteristics, as shown in Figure 4a) and good saturation in output characteristics (i.e., Ids vs. drain to source voltage (Vds) characteristics, as shown in Figure 4b) for any channel length (Lch) down to ~10 nm . These FETs have predominant p-type behavior because of the natural presence of –OH groups at the interface of SWCNTs. On-current (Ion; defined as Ids at a certain high |Vg − Vt|, where Vt is the threshold voltage of a FET) and off-current (Ioff; defined as the minimum of Ids) in these FETs with single s-SWCNT show variation with d and source/drain contact material being used. Contacts with higher work-function (ΦWF) can inject holes into the valence bands of s-SWCNTs more easily and have larger Ion and Ioff (Figure 4c,d); [44,58,59]), especially for larger diameter s-SWCNTs that have smaller band-gap, Eg (see Equation (1)) and hence have negligible hole injection barrier at the metal/s-SWCNT interface. Therefore, contacts play a major role in the conduction of SWCNT-FETs and are considered to have dominant contribution in limiting Ids in the near ballistic limit [28,63], when Lch is much less than the channel mean free path that defines mobility. Sub-threshold slope (SS; defined as ∂Vg/∂(log10Ids) in the region with Vg << Vt) for FETs with single s-SWCNT varies from ~80–95 mV/dec and increases with a decrease in Lch due to ambipolar conduction . (Use of appropriate chemical coating on SWCNT in a dual-gate device configuration can reduce SS to 63 mV/dec , which is close to the theoretical limit of SS = 2.3kBT/q ~ 60 mV/dec at room temperature for a FET ; here, kB is the Boltzmann constant, T is temperature in °K, and q is the electron charge.) Hole effective mobility (μeff,h) of s-SWNTs ranges from ~103–105 cm2/V-sec [5,6,25,63,67] and increases with d . Such μeff,h value depends on CNT growth conditions and is better for CVD-grown CNTs compared to solution-processed CNTs .
In contrary to s-SWNTs, FETs with single metallic (m-) SWCNT-FETs have very small gate modulation and show ambipolar behavior with a smaller n-type tail (Figure 5a). Such gate modulation is often attributed to the presence of Mott-insulating states  and/or strain-induced bandgap  in m-SWCNTs. FETs with s-SWCNTs also show ambipolar behavior, more significantly at higher |VDS| and for larger diameter s-SWCNTs (Figure 5b) due to band-to-band tunneling (BTBT) .
2.4. FETs with Multiple SWCNTs
Multiple SWCNTs in FET’s channel are either arranged randomly as network or aligned parallel to each other bridging source and drain. Network SWCNT-FETs can be made using CVD-grown SWCNTs with mixed chiralities (Figure 6a shows a scanning electron microscope (SEM) image for one such bottom-gated FET near a source/drain contact). These FETs have low on/off ratio, unless the conduction through metallic SWCNTs is turned off via periodic stripping . An alternate way of improving on/off ratio is to use solution-processed, chirality sorted s-SWCNTs for making FETs. However, such FETs show lower conductance compared to CVD-grown SWCNTs because of the presence of structural defects .
Network SWCNTs have impedances at the junctions of different SWCNTs; consequently, they have lower conductance and are suitable only for applications like non-volatile memories [14,15]. Parallel arrangement of aligned SWCNTs resolves the issue with junction impedance and promises applications of SWCNTs in high performance radio frequency (RF) electronics [47,71,72], and transparent electronics [73,74]. Figure 6b shows a SEM image of one such top-gated FET before gate dielectric and gate metal formation. These aligned array SWCNT-FETs are either fabricated by growing SWCNTs via CVD on special types of quartz or sapphire substrates, whose crystal orientations  and/or step-edges [75,76] help parallel alignment (with less than 0.1% imperfection ) of d ~ 0.7~3 nm SWCNTs [26,44,45], or fabricated by aligning solution-processed SWCNTs via dielectrophoresis . CVD-grown SWCNTs are long (with a length of several hundreds of µm ) and have high conductivity [5,25,63,67], however, require the use of post-processing techniques like thermo-lithography  and laser irradiation  for removal of m-SWNTs, or electrical breakdown  for breaking the continuity of m-SWNTs, and hence, cause FETs to use the remaining s-SWNTs.
3. Variability in SWCNT-FETs
3.1. Variability in FETs with Single SWCNT
Performance variation in FETs with single s-SWCNT arises from the variation in d, contact and gate metals’ ΦWF, Lch, Tox (oxide thickness), and interface and oxide defects from one FET to another. For FETs with Lch>µm, variation in d can give rise to several orders of magnitude change in Ids, as shown in Figure 7a for small Vds = −50 mV. One can simulate such transfer characteristics for different d (dashed lines in Figure 7a) by considering the conductance of the FET (Gds) as a series combination of conductances of s-SWCNT (Gss; see Ref.  for appropriate expressions) and contact (Gc = Gc0Tc; where Tc is the transmission probability of carriers near the source/drain contact) with components from both electron (e) and hole (h), i.e.,
Simulated Ion, Gm,max, and Vt distributions (calculated using diameter distribution of Figure 7c and variations of Ion, Gm,max, and Vt vs. d from Figure 7b) suggest good consistency with respective measurements (Figure 7d–f). Similar to the diameter distribution of Figure 7c, Ion distribution fits log-normal statistics, except near the lower tails of the distribution where transport through the contacts’ Schottky barrier with Tc < 1 dominates Ids. Measured Vt − <Vt> distribution (where <Vt> is the average of the distribution) is wider than the simulated one due to the extra contributions from defects [16,83] and gate ΦWF [84,85] variations that is not considered in the simulation. Passivation of SWCNT interface using hydrophobic self-assembled monolayers (SAMs) can tighten the Vt distribution by reducing hydroxyl (–OH) group related interface defects . Figure 8a demonstrates utility of such SAM-based approach for reducing Vt distribution, where Lch << µm s-SWCNT FETs are made using solution-processed SWCNTs and passivated with hexamethyldisilazane (HMDS). As in CVD-grown s-SWCNTs, distribution in Gm (Figure 8b) for such solution-processed s-SWCNT FETs follows that of diameter (Figure 8c). In addition, contact resistance Rc = 1/Gc in such small Lch s-SWCNT FETs plays a dominant role in transport. Distribution of Rc (Figure 8d) arises from variations in Tc with d  and also from variations in the contact’s ΦWF. In contrary, FETs with m-SWCNT and similar Lch have tighter Rc distribution ; however, they still suffer from variations in Ids (Figure 8e) and, hence, Gm (Figure 8f). Since m-SWCNTs are unattractive for high performance electronics applications requiring high Ion/Ioff, parametric variations in m-SWCNT FETs are not well studied.
3.2. Variability in FETs with Multiple SWCNTs
Similar to single SWCNT-FETs, performance variation in FETs with multiple SWCNTs originates from variations in d, ΦWF, Lch, Tox, and defects [87,88,89]. A simple translation of single SWCNT-FET analysis to multiple SWCNT-FET; however, they cannot explain related variations, mostly because of the added complexity coming from variations in the arrangements and types of multiple SWCNTs bridging source/drain contacts. Multiple SWCNT FETs can have random network or aligned SWCNTs with varied density of m- and s-SWCNTs, a wide range of variations in the orientation of SWCNT and its crossings (especially for network SWCNT FET), and a wide distribution in d. This section discusses performance variation in aligned array SWCNT-FETs that have significant promise for high performance device applications. Such FETs have negligible variation in SWCNT’s orientation  and also have negligible SWCNT crossings (Figure 6b). For a discussion on variabilities coming from SWCNT’s orientation and crossings, which are more relevant for network SWCNT-FETs, please refer to Ref. .
Solution-processed SWCNTs that are widely used for fabrication of FETs with network and partially aligned SWCNTs have yet to reach the target of 100% chiral selectivity. Some of the resultant FETs, therefore, have high on/off ratios when SWCNT density within the FET is low [35,46]. On the other hand, high performance electronics demand the availability of CVD-grown SWCNTs that always come with a mixture of m- and s-SWCNTs and require the application of post-processing techniques (e.g., electrical breakdown , gas-phase reaction , thermo-lithography ) for having high on/off ratio in multiple SWCNT FETs. In some cases, application of post-processing techniques like electrical breakdown  and gas-phase reaction  also leads to unwanted removal of s-SWCNTs and, hence, performance degradation or even transistor failure . Considering pm as the probability of a single SWCNT in the FET being metallic, pRs as the probability of s-SWCNT being removed via post-processing, IDC as the index of dispersion in SWCNT count within the FET, one can simulate the failure probability (pF) for FETs with aligned SWCNTs at different SWCNT densities (Figure 9a). Such analysis, however, ignores a well-known aspect of ‘inferential statistics’ , i.e., the distributions of SWCNT density and d in macro-scale (population distributions) is not always same as the distributions in micro-scale (sample distributions). As such, performance variability from diameter variations were expected to diminish for high density multiple SWCNT FETs via statistical averaging [25,41,91], making SWCNT density and m-SWCNT’s presence as the major contributors to performance variations (Figure 9b) .
We performed a comprehensive experimental and theoretical study on FETs with aligned array SWCNTs  and ruled out the presence of statistical averaging in aligned-array SWCNT-FETs. Figure 10a plots distribution of Ion (measured at a Vg − Vt = −1 V) for aligned array-SWCNT FETs having <N> ~ 11 SWCNTs, where <N> = <ρ>W is nominal number of SWCNT within the FET, W is the channel width, and <ρ> is the average SWCNT density on the substrate per µm across the length of the nanotubes. Since variation in Ion follows Poisson statistics , we account for changes in µIon (that arises from variation in sample preparation) from one set of array-SWCNT FET to another by dividing the standard deviation of Ion/<N> (σIon) with √µIon (where µIon is the average of Ion/<N>). Calculated σIon/√µIon, normalized with respect to the same value measured for FETs with single SWCNT, shows a small reduction with the increase in <N> (Figure 10b). If the diameter and density distributions of SWCNT for each array-SWCNT FETs (sample distribution) were the same as the wafer-level distribution (population distribution) of these parameters, as per central limit theorem , the normalized standard deviation should have reduced as 1/√<N> due to statistical averaging. The existence of deviation from 1/√<N>, therefore, suggests significant variations in SWCNTs’ density and diameter across the wafer, as was confirmed via extensive atomic force microscopy (AFM) at different locations over a macroscopic area of ST-cut quartz substrate that had CVD-grown aligned arrays of SWCNTs .
To clarify the differences between measured σIon/√µIon and expected 1/√<N> dependency, measured diameter and density variations across the wafer are used first to calibrate the variations measured at the microscopic level (i.e., electronic properties of single-SWNT-FETs, as discussed in section 3.1). Later, the rules of “inferential statistics”  is used to analyze variations at the macroscopic level (i.e., for array SWCNT FETs). Here, density variation is eliminated by counting the number of SWCNTs (N) for each array-SWNT FET and then using (Ids/N) − Vg characteristics for standard deviation calculation. Even after accounting for density variation, calculated σIon at different <N> (normalized to its value for <N> = 1) shows significant deviation from 1/√<N> scaling (Figure 10c). Such deviation suggests SWCNT density variation as a minor contributor to performance variation, thus contradicting the results of Refs. [25,41,91]. Finally, Ids-Vg characteristics of array-SWCNT FETs are simulated for different <N> by considering experimentally calibrated diameter dependence of single-SWCNT FETs’s Ids-Vg characteristics (Figure 7a) and measured (wafer-scale) density, diameter distributions of SWCNT. Figure 10c,d show normalized standard deviations of Ion (σIon) and Gm,max (σGm), as simulated for different <N> and their comparison to measured quantities. Since the sample sizes in measuring the standard deviations were small (~17–35), simulated standard deviations show a range of magnitudes for similar sample sizes within which the measured data points fits in. (The simulation framework , used for calculating σIon and σGm of array-SWCNT FETs, neglects contributions from m-SWCNTs. However, the procedure is suitable for demonstrating the importance of wafer-level variations in diameter and density).
Recently, use of smaller equivalent oxide thickness (EOT ≡ εSiO2/εHKTox; where εSiO2, εHK are dielectric constants of SiO2 and high-κ dielectrics, respectively) has been shown to reduce the performance variation in FETs with single s-SWCNTs . Decreasing EOT reduces the width of the Schottky barrier near the SWCNT and source/drain junction  and removes the long negative tails in the Ion distribution . Moreover, as Lch approaches the carrier mean-free path of SWCNT, Ids saturates for large diameter SWCNTs and hence diameter dependence of Ids is less pronounced . Both these effects are studied by simulating small-scale array-SWCNT-FETs with EOT ~ 1 nm and Lch = 300nm. (Here, simulated Ids-Vg  is calibrated with measurements of Ref. ). Simulation suggests a decrease in σIon for FETs with <N> = 1 with decreasing EOT (Figure 11a). However, at larger <N>, neither EOT nor Lch scaling could improve the statistics because the effects of variations in density and diameter remain significant (Figure 11b). Therefore, narrowing diameter and density distributions are identified as the main areas for improvement via advanced growth and/or purification techniques to reduce performance variation in multiple-SWCNT FETs.
4. Reliability of SWCNT-FETs
Reliability (i.e., device performance degradation) for any device can be interpreted by understanding its origin. For SWCNT-FETs, degradation arises from defects at the interface of SWCNT/oxide and also from defects within the oxide. Trapping and detrapping of carriers (i.e., electrons and holes) into and out of these defects changes performance parameters like Vt, Ids, Gm, etc. over time [94,95,96] and also causes hysteresis in the measured Ids-Vg characteristics . In addition to these interface and oxide defects, performance of SWCNT-FET is also affected by topological or Stone-Wales defects [97,98]. They affect the transport of carriers through SWCNT; hence, they lower the mobility of associated FETs. On the other hand, controlled introduction of defects via UV/ozone/chemical treatment , doping [20,100], etc. enable the application of SWCNTs as sensors by providing low-energy adsorption sites for introduction of chemical species. These structural defects, however, do not evolve with time during the operation of SWCNT-FET, hence do not affect reliability.
In this section, we discuss the nature of interface (section 4.1) and oxide (section 4.2) defects in SWCNT-FETs and show how these defects raise reliability concerns such as hysteresis (section 4.3), low-frequency noise (section 4.4), radiation damage (section 4.5), and time-dependent performance degradation (section 4.6). These interface and oxide defects though cause reliability concerns at different quantities depending on the orientation and density of SWCNTs within the FET, the qualitative features of reliability remain the same for any orientation and density, as studied in context of hysteresis and performance degradation in Ref. . Therefore, in contrary to Section 3, where variability of FETs with single and multiple SWCNTs is discussed separately, a general discussion of reliability without reference to SWCNTs’ density and orientation within the FET is sufficient for this section.
4.1. Interface Defects in SWCNT-FETs
Hydroxyl group (–OH), commonly present at any oxide surface [101,102], is the source of interface defects in SWCNT-FET [83,103,104]. Physisorbed water molecules and oxygen, present at the SWCNT/oxide in ambient condition, control –OH density  through electrochemical reaction: O2 + 4H+ + 4e− ↔ 2H2O [102,105]. These –OH groups or interface defects surround SWCNTs laying on SiO2 surface (Figure 12a) and can give rise to large hysteresis in measured Ids-Vg characteristics [83,103,104], as well as potential time-dependent degradation in measured current [95,96]. Application of positive Vgs negatively charges –OH groups via electron capture from SWCNT positively shifts Vt and enhances hole conduction in commonly used p-type SWCNT-FET. Application of negative Vg, on the other hand, discharges the –OH group into neutral state, negatively shifts Vt and reduces hole conduction. Marcus-Garischer theory is generally used for modeling charging into or discharging from interface defects in SWCNT-FETs [94,105].
High temperature annealing under vacuum can reduce –OH groups [83,104] by eliminating water molecules at temperatures >190 °C . Annealing at even higher temperature (at >1000 °C ) in vacuum would have completely removed the –OH groups; however, they have never been tested because of the high potential for damage to the SWCNTs and to the characterization system at such high temperatures. In addition to annealing in vacuum, –OH group or interface defects can also be reduced by using poly-methyl methacrylate (PMMA) encapsulation with thermal annealing  or by growing SWCNTs on different types of hydrophobic surfaces like octadecyltrichlorosilanated-SiO2 [103,106], hexamethyldisilazanized-SiO2 , octachlorotrisiloxane-capped organic dielectrics , etc.
4.2. Oxide Defects in SWCNT-FETs
Defects that are present within the gate dielectric, either near the SWCNTs or deep into the dielectric, also affect device performance. These oxide defects are broken bonds (Figure 12b) and pre-exist within the amorphous oxide network at various quantities, depending on the type of oxidation being performed. These pre-existing oxide defects can be annealed, for example, at high temperatures in hydrogen ambient . Oxide defects are also generated near the vicinity of SWCNT during its growth, unless appropriate measures are taken to reduce the defects by running the growth in an inert environment . In addition to the pre-existing ones, oxide defects are also generated during operation of FETs and causes dielectric breakdown [109,110,111]. The nature and origin of these oxide defects have been studied extensively using electron paramagnetic resonance [112,113], stress-induced leakage current , sweep-rate dependent Ids-Vg hysteresis , and optical excitation . Unlike interface defects in SWCNT-FET, oxide defects are ambipolar and can either switch between negative and neutral charged states (i.e., act as electron traps) or switch between positive and neutral charged states (i.e., act as hole traps) —thus, showing a wide range of reliability concerns as discussed below.
4.3. Hysteresis in SWCNT-FETs
Large hysteresis in Ids-Vg characteristics is a common phenomenon in SWCNT-FET and its magnitude depends on the concentration of defects in the FET [83,94], density of SWCNT , and also on the magnitude [94,107,117] and sweep-rate of Vg [83,94] (Figure 12c). Two stable charged and discharged states for the defects and switching between these states by application of appropriate Vg is the origin of hysteresis. Though such hysteresis promises memory applications using SWCNT, it is detrimental for device applications.
As mentioned before, both interface and oxide defects can give rise to hysteresis in SWCNT-FET. According to Marcus-Garischer theory , –OH groups or interface defects in SWCNT have separate, broad energy levels for discharged (neutral) and negatively charged state, as shown in Figure 13a. In FETs where interface defects predominantly controls hysteresis, the separation between these neutral and charged energy levels of –OH (known as reorganization energy) controls the magnitude of hysteresis . Charging and discharging of oxide defects, on the other hand, can be modeled within a Shockley-Read-Hall framework . Density and type of oxide defects depend on the oxide quality on which carbon nanomaterials are grown or placed on . In some harsh growth conditions, oxides near the FET channel are damaged and give rise to large amount of near-interface oxide defects that dominate the trends in measured hysteresis. In other optimized conditions, we only have a small amount of bulk oxide defects that controls the hysteresis trends.
Self-consistent Poisson and drift-diffusion solution , supported by detailed experiments, suggest contrasting sweep rate dependence of hysteresis for different types of defects in SWCNT-FET. Interface defects are characterized by short charge capture and emission times compared to the time used for sweeping Vg to measure hysteresis and, therefore, have sweep rate independent hysteresis. On the other hand, near-interface oxide defect have small capture but comparatively larger emission times, such that hysteresis increases with sweep rate; whereas oxide defects within the bulk of the dielectric have large capture and emission times, such that hysteresis decreases with sweep rate. Measurement of hysteresis at different sweep-rate dependencies, therefore, is used to identify the contributions from different types of defects on hysteresis in SWCNT-FET and modify the fabrication steps appropriately to optimize different defects. Growing SWCNTs in an inert environment reduces the amount of near-interface oxide defects  and enables one to employ different interface defect removal techniques to compare their effectiveness. A comparison of different –OH group reduction methods (e.g., heating FETs in vacuum , coating SWCNT with PMMA  or spin-on-glass ; Figure 14a) suggests high temperature annealing, quality of coatings to block water penetration, and reaction of OH-group with coated molecules as the key for reducing hysteresis originating from –OH group related interface defects. All these –OH removal techniques have shown negligible hysteresis when SWCNT-FET is swept with smaller |Vg,max|. Table 1 summarizes the values of |Vg,max| and corresponding maximum of average oxide electric fields (Eox,max) that has been reported to show negligible hysteresis under various conditions [9,83,94,103,106,107,121,122]. (Eox,max calculation steps for all the references are shown in the caption of Table 1.) Among these conditions, SWCNT-FETs with spin-on-glass/HfO2 gate dielectric shows negligible hysteresis for highest Eox,max ~ 0.45 MV/cm. At higher |Vg,max| or Eox,max, hysteresis reappears [94,107] which suggests incomplete removal of interface and oxide defects using the techniques mentioned above. Use of combinatorial approaches such as placing SWCNT on hydrophobic surfaces, annealing at temperatures above 400 °C in an inert environment, and then coating with hydrophobic gate dielectric may eliminate hysteresis even at higher Eox,max. Hysteresis reduction is critical for SWCNT-FET, because reduced hysteresis is generally accompanied with a narrower distribution in Vt (Figure 8a) and also for the hysteresis itself (Figure 14b) . Removal of –OH group from SWCNT-FETs, therefore, is necessary to improve variability in SWCNT-FET.
4.4. Low-Frequency Noise in SWCNT-FETs
Low-frequency noise measurement is a general way of characterizing deformations or defects in any nanoscale systems [123,124,125,126,127]. It is also a reliability concern for flash memories [128,129], radio-frequency (RF) circuits , and, in general, for many different digital and analog applications employing nanoscale FETs. Among different components of low-frequency noise, the following components are routinely measured: (i) the frequency independent thermal noise component with power spectral density of 4kBTR, which originates from the statistical Brownian motion of carriers at temperature T in a resistive system with resistance R; (ii) the Lorenzian-type noise component with power spectral density ~ 1/[1 + (2πfτ)2], which originates from trapping/detrapping events for a small number of deformations or defects with time constant τ and cut-off frequency fc = 1/τ; and (iii) the flicker noise component with power spectral density ~ 1/f n, which originates from a distribution of trapping/detrapping events.
|Table 1. Values of EOT, SWCNT density (D), capacitance ratio (Ξ) , maximum electric field with parallel plate assumption (i.e., SWCNT is presumed to form a dense film), and maximum of the average oxide electric field (Eox,max) for reported instances [9,83,94,103,106,107,121,122] of negligible hysteresis in SWCNT-FETs. Here, Ξ = 4π × EOT/εSiO2 × λ0[2/εSiO2 × ln[λ0/d × sinh(2π × EOT/λ0)/π] + CQ−1]  (where λ0 = 1000/D is the average distance between each SWCNT, CQ = 4 × 10−12 F/cm is the quantum capacitance ), EP,max = VG,max/EOT, and Eox,max = Ξ × EP,max.|
|Reference||EOT [nm]||D [μm−1]||Ξ||Vg,max [V]||EP,max [MV cm−1]||Eox,max [MV cm−1]||Type of Dielectric|
| Cao et al., Nature ʼ08||8.2||~6||0.01||2||2.44||0.02||HfO2|
| Weitz et al., NL ʼ07||20.3||5.48||0.16||2||0.98||0.16||Octadecyltrichlor osilanated-SiO2|
| Hur et al., JACS ʼ05||6.9||1 (Single CNT)||0.01||1||1.45||0.02||Octachlorotrisilox ane-capped organic dielectric|
| Kim et al., NLʼ03||500||1 (Single CNT)||0.36||10||0.2||0.07||SiO2 with PMMA coating|
| McGill et al., APL ʼ06||100||~3||0.30||2||0.2||0.06||Octadecyltrichlor osilanated-SiO2|
| Hu et al., Phys. E ʼ08||200||~3||0.45||10||0.5||0.23||Aminopropyltrieth oxysilaned-SiO2|
| Kim et al., APL ʼ07||6.5||1 (Single CNT)||0.01||1||1.54||0.02||Al2O3|
| Jin et al., AFM ʼ12||40||~6||0.29||6||1.5||0.45||Spin-on-glass (SOG) + HfO2|
Noise in SWCNT-FETs has been widely studied to understand the origin of deformations or defects in SWCNT lattice and in its surrounding oxides [123,124,125,128,129], and also to explore the effect of radiation damage  and chemical exposure . Measured low-frequency noise in SWCNT is much more pronounced than in silicon electronics [135,136] because of the presence of a few carriers for conduction . In addition to structural defects in the SWCNT lattice , oxide defects contribute significantly to low-frequency noise behaviors in SWCNT-FETs . (A recent discussion on different sources of low-frequency noise in SWCNT materials and devices can be found in Ref. .) Interface defects interact at faster time-scales and hence noise because interface defects are generally overwhelmed by thermal noise at high frequencies. Oxide defects, on the other hand, have comparatively longer and distributed charging and discharging times (either due to distribution in tunneling distance [126,127] or due to distribution in defects’ energetics ) that give rise to 1/f behavior in the power spectral density of measured noise in Ids at low frequencies [134,135], as shown in Figure 15a, which is measured for a single s-SWCNT-FET at different Vg . From Hooge’s number fluctuation theory  noise power spectral density (SI) can be expressed as,
Noise measurements in cryogenic conditions reduce thermal noise and also freeze-off some of the defects that contribute to noise at higher temperatures. Responses from the remaining few oxide defects result in random telegraph noise (RTN) with stochastic variation in Ids and discrete current levels [137,141,142,143]. Figure 16a shows RTN obtained from a SWNT-FET (measured at T = 4.2 °K) suggesting four major switching levels resulting from a slow switching defect (whose fluctuation is digitized in the bottom of Figure 16a) and a fast switching defect . Corresponding power density spectrum for these fluctuations is shown in Figure 16b that suggests two overlapping Lorenzian spectrums with corner frequencies (fc) at 0.2 Hz (for the slow defect) and 5.8 Hz (for the fast defect). At higher temperatures (T = 60 °K), however, responses from these two defects are mixed up (inset of Figure 16b) and noise from new defects (with higher fc) shows up. Similar noise analysis at different Vg (Figure 16c) enables one to extract distributions of capture time τc (defined as the time required for a high to low transition in Ids) and emission time τe (defined as the time required for a low to high transition in Ids). These distributions are used to calculate the averages of capture and emission times (<τc> and <τe>) at different Vg (Figure 16d) and, hence, the location of defect causing RTN from the slope of ln(<τe>/<τc>) vs. Vg plot .
Though RTN analysis has not yet been employed to study the evolution of defects—i.e., reliability in SWCNT-FETs—1/f noise has been used to study the radiation effects in such FETs . An increase in 1/f noise after gamma radiation (Figure 17) suggests generation of defects within the oxide. The next section discusses the radiation effects on SWCNT-FETs in detail.
4.5. Radiation Damage in SWCNT-FETs
Promising performance parameters of SWCNTs have initiated studies to explore their potential in terrestrial and space-based applications [133,144,145,146,147,148,149]. In such niche applications, radiation tolerance is one of the key reliability parameters. In this regard, use of SWCNT as a channel showed significant advantages over its silicon-based predecessors. Small cross-sections of SWCNT make it less susceptible to incident radiation particles, unless radiation dose (termed as displacement damage dose, DDD) exceeds ~ 1013 MeV/g . One can evaluate DDD for different types of particles (e.g., alpha, proton, ionized chemical species) by considering the number of particles striking SWCNTs per unit area (i.e., fluence) and the efficiency of these particles in creating defects within the SWCNT lattice (which is quantified using the term non-ionizing energy loss ). Damage in SWCNT at high radiation dose (with DDD > 1013 MeV/g) can be monitored using Raman spectroscopy as an increase in intensity at the defect (D)-band wavenumber of ~ 1300 cm−1 [133,146,147,148,151] and also using electrical measurement as an increase in resistance [148,151]. Figure 18a,b show Raman spectra for m- and s-SWCNT-FETs measured at different amount of ionized boron irradiation. Radiation gradually introduces defects within the SWCNT lattice, therefore, increasing the ratio of Raman intensities measured for D- and G+-bands or for D- and G'-bands. (G+- Raman signal comes from the atomic vibration of carbon atoms along the axial direction of SWCNT and peaks at a wavenumber of ~1590 cm−1 with no diameter dependence. On the other hand, G'- Raman signal arises from a two-photon, inter-valley, second-order Raman scattering process and peaks at a wavenumber of ~2700 cm−1 with significant diameter dependence. Both G+ and G' have no influence from structural defects in SWCNTs. (Dresselhaus et. al  provide an elaborate review of Raman signal and its origin in different types of SWCNTs.) Ratio of Raman intensities obtained using D- and G'-bands (D/G') are shown to be more sensitive in monitoring the effect of radiation that linearly depends on DDD (Figure 18c), when D/G' at a particular amount of radiation (Φ) is normalized to its value measured before radiation (Φ = 0) . The same linear degradation law also holds for the radiation-induced resistance degradation in SWCNT and graphene.
At radiation doses comparable to aerospace environments (i.e., for DDD<1013 MeV/g), only the dielectric layer of SWCNT-FETs are damaged with no damage to the SWCNT lattice [133,146,154]. Radiation in such condition changes Vt of SWCNT-FETs with negligible change in mobility (Figure 19a), therefore, suggests negligible defect formation within the SWCNT. The behavior is also confirmed via Raman spectroscopy (Figure 19b) that shows negligible change in D-band and the radial breathing mode (RBM) Raman signals. (RBM signal comes from the atomic vibration of carbon atoms along the radial of SWCNT and has peaks at wavenumbers in the range of ~100–400 cm−1 with strong diameter dependence .) A decrease in Vt with increasing radiation for the p-type SWCNT-FET (Figure 19a) suggests creation of oxide defects that act as hole trapping sites. The situation improves significantly when a comparatively thinner (~23 nm) silicon oxynitride dielectric (grown via plasma-enhanced chemical vapor deposition) replaces the regularly used ~100 nm SiO2 in making SWCNT-FETs for radiation testing . Pre- and post-radiation Ids-Vg measurements (Figure 20) suggest negligible change in FET parameters above threshold (i.e., Vt and μeff). Creation of balanced hole and electron trapping sites within the dielectric  and use of thin dielectric that allows the escape of trapped charges  are presumed to be the origin of such radiation hardness in these devices. The sub-threshold behavior, on the other hand, shows degradation when the devices are exposed to a negative gate electric field of −1 MV/cm. The origin of such degradation has been attributed to the formation of electron trapping sites within the oxide or at the interface of SWCNT—which requires detailed future analysis. Overall, SWCNT-FETs with thin dielectric offer great potential for space electronics in the future.
4.6. Performance Degradation in SWCNT-FETs
Performance degradation of transistor parameters over time is a critical reliability concern that dictates the determination of device lifetime. In transistor reliability literature, bias temperature instability  and stress-induced leakage current  are often used to monitor performance degradation and to probe the dynamics of defects in different regions of the FET. Though hysteresis and low-frequency noise has been widely used to study the nature of defects in SWCNT-FET, detailed analysis of performance degradation over longer time scales is still lacking. Studies of degradation up to a few seconds [95,96] though provides critical information about the nature of some of the defects, projection of performance degradation up to an intended lifetime of 5–10 years requires accelerated tests (at voltages much higher than use condition) and for longer times (1000 s or more), which are widely used in conventional CMOS reliability studies .
Some of the recent long-term performance degradation studies in SWCNT-FETs  suggest oxide defect as the key contributor for the instability. SWCNT-FETs with a large amount of near-interface oxide defects show significant Ids degradation (ΔIds; Figure 21a) and have a small time constant τ ~ 7 × 104 sec for the fitted stretched exponential forms according to ΔIds = Ids0[1 − exp(−t/τ)β] (where Ids0 is the magnitude of drain current at t = 0, t is the time at which degradation is measured, and τ, β ~ 0.35 are fitting parameters) . On the other hand, devices with a small amount of bulk oxide defects have lower ΔIds and long τ ~ 2 × 107 s (with β ~ 0.35). Moreover, the nature of trapping into oxide defects remains the same at different accelerated stress conditions, as seen from the measured ΔIds at different gate biases (Figure 21b). All these degradation curves can be fitted with a fixed β and a voltage dependent τ (higher for higher Vg) that suggests more and deeper oxide defects are accessible at higher stress biases. Therefore, by using τ as a voltage dependent parameter, one can project reliability of these SWCNT-FETs at different use conditions. Detailed analysis of such degradation by understanding the trapping dynamics (which may require the use of one or multiple time constants ) is still lacking.
5. Summary and Outlook
We have discussed different sources of variability and reliability that controls the change in time-zero and time-dependent performance parameters in SWCNT-FETs. Variability in SWCNT FETs performance is mainly attributed to the distributions of SWCNTs’ diameter across the wafer and the presence of hydroxyl-group related interface defects in SWCNTs’ surroundings. The removal of m-SWCNTs and the tightening of diameter distribution for s-SWCNTs via chiral-selective growth  or post-processing [50,54], and complete passivation of SWCNTs via removal of hydroxyl groups [83,94] are necessary for controlling variability. Removal of hydroxyl groups from SWCNTs’ surfaces will also be the key to having a reliable SWCNT FET that will operate with reduced performance degradation over its lifetime. In addition, oxide defects keep playing a dominant role in controlling reliability parameters, like low-frequency noise, radiation damage, and long-term performance degradation. Therefore, solutions in terms of having reliable gate dielectrics with less defects [111,160] will not only help current CMOS scaling, but will also assist with the introduction of beyond CMOS devices with SWCNT-based FET.
The author acknowledges contributions from John Rogers (University of Illinois) for introducing the presented area of research and also from Sunghun Jin, Frank Du (University of Illinois) for related experiments and discussion. Discussions with Muhammad A. Alam (Purdue University), Cory D. Cress (Naval Research Laboratory), Benji Maruyama (Air Force Research Laboratory), and funding from Air Force Office of Scientific Research (contract number: FA 8650-09-D-5037), Materials Structures and Devices Focus Center (Task ID: 2051.003.4) of Semiconductor Research Corporation are acknowledged for preparation of this review article.
Conflicts of Interest
The authors declare no conflict of interest.
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