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Electronics 2013, 2(1), 57-79; doi:10.3390/electronics2010057
Article

Design of a Parallel Sampling Encoder for Analog to Information (A2I) Converters: Theory, Architecture and CMOS Implementation

,
 and
*
Electrical and Computer Engineering Department, The Johns Hopkins University, Baltimore, MD 21218, USA
* Author to whom correspondence should be addressed.
Received: 19 December 2012 / Revised: 9 February 2013 / Accepted: 21 February 2013 / Published: 5 March 2013
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Abstract

We discuss the architecture and design of parallel sampling front ends for analog to information (A2I) converters. As a way of example, we detail the design of a custom 0.5 µm CMOS implementation of a mixed signal parallel sampling encoder architecture. The system consists of configurable parallel analog processing channels, whose output is sampled by traditional analog-to-digital converters (ADCs). The analog front-end modulates the signal of interest with a high-speed digital chipping sequence and integrates the result prior to sampling at a low rate. An FPGA is employed to generate the chipping sequences and process the digitized samples.
Keywords: analog to information converter; sub-Nyquist sampling; compressive sensing; parallel ADCs analog to information converter; sub-Nyquist sampling; compressive sensing; parallel ADCs
This is an open access article distributed under the Creative Commons Attribution License (CC BY 3.0).

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Murray, T.S.; Pouliquen, P.O.; Andreou, A.G. Design of a Parallel Sampling Encoder for Analog to Information (A2I) Converters: Theory, Architecture and CMOS Implementation. Electronics 2013, 2, 57-79.

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