Next Article in Journal
A Bond Graph Approach for the Modeling and Simulation of a Buck Converter
Next Article in Special Issue
Design of a Programmable Passive SoC for Biomedical Applications Using RFID ISO 15693/NFC5 Interface
Previous Article in Journal / Special Issue
A Low-Power CMOS Piezoelectric Transducer Based Energy Harvesting Circuit for Wearable Sensors for Medical Applications
Article Menu

Export Article

Open AccessArticle
J. Low Power Electron. Appl. 2018, 8(1), 1; https://doi.org/10.3390/jlpea8010001

SoC-Based Edge Computing Gateway in the Context of the Internet of Multimedia Things: Experimental Platform

ISEN Yncrea Ouest, VISION Team, 20 rue Cuirassée Bretagne, 29200 Brest, France
*
Author to whom correspondence should be addressed.
Received: 4 October 2017 / Revised: 9 January 2018 / Accepted: 10 January 2018 / Published: 12 January 2018
(This article belongs to the Special Issue Low-Power Electronic Circuits for Monolithic Smart Wireless Sensors)
View Full-Text   |   Download PDF [6270 KB, uploaded 12 January 2018]   |  

Abstract

This paper presents an algorithm/architecture and Hardware/Software co-designs for implementing a digital edge computing layer on a Zynq platform in the context of the Internet of Multimedia Things (IoMT). Traditional cloud computing is no longer suitable for applications that require image processing due to cloud latency and privacy concerns. With edge computing, data are processed, analyzed, and encrypted very close to the device, which enable the ability to secure data and act rapidly on connected things. The proposed edge computing system is composed of a reconfigurable module to simultaneously compress and encrypt multiple images, along with wireless image transmission and display functionalities. A lightweight implementation of the proposed design is obtained by approximate computing of the discrete cosine transform (DCT) and by using a simple chaotic generator which greatly enhances the encryption efficiency. The deployed solution includes four configurations based on HW/SW partitioning in order to handle the compromise between execution time, area, and energy consumption. It was found with the experimental setup that by moving more components to hardware execution, a timing speedup of more than nine times could be achieved with a negligible amount of energy consumption. The power efficiency was then enhanced by a ratio of 7.7 times. View Full-Text
Keywords: Internet of Multimedia Things; power efficiency; adaptive signal processing; approximate computing; FPGA design Internet of Multimedia Things; power efficiency; adaptive signal processing; approximate computing; FPGA design
Figures

Figure 1

This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. (CC BY 4.0).
SciFeed

Share & Cite This Article

MDPI and ACS Style

Jridi, M.; Chapel, T.; Dorez, V.; Le Bougeant, G.; Le Botlan, A. SoC-Based Edge Computing Gateway in the Context of the Internet of Multimedia Things: Experimental Platform. J. Low Power Electron. Appl. 2018, 8, 1.

Show more citation formats Show less citations formats

Note that from the first issue of 2016, MDPI journals use article numbers instead of page numbers. See further details here.

Article Metrics

Article Access Statistics

1

Comments

[Return to top]
J. Low Power Electron. Appl. EISSN 2079-9268 Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert
Back to Top