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J. Low Power Electron. Appl. 2016, 6(3), 13; doi:10.3390/jlpea6030013

Scaling Floating-Gate Devices Predicting Behavior for Programmable and Configurable Circuits and Systems

Electrical and Computer Engineering (ECE), Georgia Institute of Technology, Atlanta, GA 30332-250, USA
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Academic Editor: Tony Tae-Hyoung Kim
Received: 4 March 2016 / Revised: 18 July 2016 / Accepted: 19 July 2016 / Published: 27 July 2016
(This article belongs to the Special Issue Ultra-Low Power VLSI Design for Emerging Applications)
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Abstract

This paper presents scaling of Floating-Gate (FG) devices, and the resulting implication to large-scale Field Programmable Analog Arrays (FPAA) systems. The properties of FG circuits and systems in one technology (e.g., 350 nm CMOS) are experimentally shown to roughly translate to FG circuits in scaled down processes in a way predictable through MOSFET physics concepts. Scaling FG devices results in higher frequency response, (e.g., FPAA fabric) as well as lower parasitic capacitance and lower power consumption. FPAA architectures, limited to 50–100 MHz frequency ranges could be envisioned to operate at 500 MHz–1 GHz for 130 nm line widths, and operate around 4 GHz for 40 nm line widths. View Full-Text
Keywords: floating-gate devices; FPAA; hot-electron injection; electron tunneling; scaling FPAA architectures floating-gate devices; FPAA; hot-electron injection; electron tunneling; scaling FPAA architectures
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. (CC BY 4.0).

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MDPI and ACS Style

Hasler, J.; Kim, S.; Adil, F. Scaling Floating-Gate Devices Predicting Behavior for Programmable and Configurable Circuits and Systems. J. Low Power Electron. Appl. 2016, 6, 13.

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J. Low Power Electron. Appl. EISSN 2079-9268 Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert
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