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J. Low Power Electron. Appl. 2016, 6(2), 9; doi:10.3390/jlpea6020009

Mastering the Art of High Mobility Material Integration on Si: A Path towards Power-Efficient CMOS and Functional Scaling

Imec, Kapeldreef 75, 3001 Heverlee, Belgium
Academic Editor: Alexander Fish
Received: 31 March 2016 / Revised: 16 May 2016 / Accepted: 6 June 2016 / Published: 14 June 2016
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2015)
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Abstract

In this work, we will review the current progress in integration and device design of high mobility devices. With main focus on (Si)Ge for PMOS and In(Ga)As for NMOS, the benefits and challenges of integrating these materials on a Si platform will be discussed for both density scaling (“more Moore”) and functional scaling to enhance on-chip functionality (“more than Moore”). View Full-Text
Keywords: high mobility materials; III-V; (Si)Ge; CMOS high mobility materials; III-V; (Si)Ge; CMOS
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. (CC BY 4.0).

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Collaert, N. Mastering the Art of High Mobility Material Integration on Si: A Path towards Power-Efficient CMOS and Functional Scaling. J. Low Power Electron. Appl. 2016, 6, 9.

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J. Low Power Electron. Appl. EISSN 2079-9268 Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert
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