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J. Low Power Electron. Appl. 2016, 6(2), 5; doi:10.3390/jlpea6020005

A Survey of Cache Bypassing Techniques

Oak Ridge National Laboratory, Oak Ridge, TN 37831, USA
Academic Editor: Swaroop Ghosh
Received: 8 March 2016 / Revised: 18 April 2016 / Accepted: 25 April 2016 / Published: 28 April 2016
Download PDF [517 KB, uploaded 28 April 2016]

Abstract

With increasing core-count, the cache demand of modern processors has also increased. However, due to strict area/power budgets and presence of poor data-locality workloads, blindly scaling cache capacity is both infeasible and ineffective. Cache bypassing is a promising technique to increase effective cache capacity without incurring power/area costs of a larger sized cache. However, injudicious use of cache bypassing can lead to bandwidth congestion and increased miss-rate and hence, intelligent techniques are required to harness its full potential. This paper presents a survey of cache bypassing techniques for CPUs, GPUs and CPU-GPU heterogeneous systems, and for caches designed with SRAM, non-volatile memory (NVM) and die-stacked DRAM. By classifying the techniques based on key parameters, it underscores their differences and similarities. We hope that this paper will provide insights into cache bypassing techniques and associated tradeoffs and will be useful for computer architects, system designers and other researchers.
Keywords: review; classification; cache bypassing; selective caching; dead block prediction; non-volatile memory; CPU; GPU; CPU-GPU heterogeneous system review; classification; cache bypassing; selective caching; dead block prediction; non-volatile memory; CPU; GPU; CPU-GPU heterogeneous system
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. (CC BY 4.0).

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Mittal, S. A Survey of Cache Bypassing Techniques. J. Low Power Electron. Appl. 2016, 6, 5.

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