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J. Low Power Electron. Appl., Volume 4, Issue 3 (September 2014), Pages 168-267

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Research

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Open AccessArticle SOTB Implementation of a Field Programmable Gate Array with Fine-Grained Vt Programmability
J. Low Power Electron. Appl. 2014, 4(3), 188-200; doi:10.3390/jlpea4030188
Received: 28 February 2014 / Revised: 28 May 2014 / Accepted: 25 June 2014 / Published: 15 July 2014
Cited by 6 | PDF Full-text (1620 KB) | HTML Full-text | XML Full-text
Abstract
Field programmable gate arrays (FPGAs) are one of the most widespread reconfigurable devices in which various functions can be implemented by storing circuit connection information and logic values into configuration memories. One of the most important issues in the modern FPGA is the
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Field programmable gate arrays (FPGAs) are one of the most widespread reconfigurable devices in which various functions can be implemented by storing circuit connection information and logic values into configuration memories. One of the most important issues in the modern FPGA is the reduction of its static leakage power consumption. Flex Power FPGA, which has been proposed to overcome this problem, uses a body biasing technique to implement the fine-grained threshold voltage (Vt) programmability in the FPGA. A low-Vt state can be assigned only to the component circuits along the critical path of the application design mapped on the FPGA, so that the static leakage power consumption can be reduced drastically. Flex Power FPGA is an important application target for the SOTB (silicon on thin buried oxide) device, which features a wide-range body biasing ability and the high sensitivity of Vt variation by body biasing, resulting in a drastic subthreshold leakage current reduction caused by static leakage power. In this paper, the Flex Power FPGA test chip is fabricated in SOTB technology, and the functional test and performance evaluation of a mapped 32-bit binary counter circuit are performed successfully. As a result, a three orders of magnitude static leakage reduction with a bias range of 2.1 V demonstrates the excellent Vt controllability of the SOTB transistors, and the 1.2 V bias difference achieves a 50× leakage reduction without degrading speed. Full article
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2013)
Open AccessArticle Assessment of Global Variability in UTBB MOSFETs in Subthreshold Regime
J. Low Power Electron. Appl. 2014, 4(3), 201-213; doi:10.3390/jlpea4030201
Received: 28 February 2014 / Revised: 27 June 2014 / Accepted: 8 July 2014 / Published: 16 July 2014
Cited by 2 | PDF Full-text (897 KB) | HTML Full-text | XML Full-text
Abstract
The global variability of ultra-thin body and buried oxide (UTBB) MOSFETs in subthreshold and off regimes of operation is analyzed. The variability of the off-state drain current, subthreshold slope, drain-induced barrier lowering (DIBL), gate leakage current, threshold voltage and their correlations are considered.
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The global variability of ultra-thin body and buried oxide (UTBB) MOSFETs in subthreshold and off regimes of operation is analyzed. The variability of the off-state drain current, subthreshold slope, drain-induced barrier lowering (DIBL), gate leakage current, threshold voltage and their correlations are considered. Two threshold voltage extraction techniques were used. It is shown that the transconductance over drain current (gm/Id) method is preferable for variability studies. It is demonstrated that the subthreshold drain current variability in short channel devices cannot be described by threshold voltage variability. It is suggested to include the effective body factor incorporating short channel effects in order to properly model the subthreshold drain current variability. Full article
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2013)
Open AccessArticle Embedded Memory Hierarchy Exploration Based on Magnetic Random Access Memory
J. Low Power Electron. Appl. 2014, 4(3), 214-230; doi:10.3390/jlpea4030214
Received: 18 October 2013 / Revised: 9 March 2014 / Accepted: 20 March 2014 / Published: 28 August 2014
Cited by 1 | PDF Full-text (2961 KB) | HTML Full-text | XML Full-text
Abstract
Static random access memory (SRAM) is the most commonly employed semiconductor in the design of on-chip processor memory. However, it is unlikely that the SRAM technology will have a cell size that will continue to scale below 45 nm, due to the leakage
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Static random access memory (SRAM) is the most commonly employed semiconductor in the design of on-chip processor memory. However, it is unlikely that the SRAM technology will have a cell size that will continue to scale below 45 nm, due to the leakage current that is caused by the quantum tunneling effect. Magnetic random access memory (MRAM) is a candidate technology to replace SRAM, assuming appropriate dimensioning given an operating threshold voltage. The write current of spin transfer torque (STT)-MRAM is a known limitation; however, this has been recently mitigated by leveraging perpendicular magnetic tunneling junctions. In this article, we present a comprehensive comparison of spin transfer torque-MRAM (STT-MRAM) and SRAM cache set banks. The non-volatility of STT-MRAM allows the definition of new instant on/off policies and leakage current optimizations. Through our experiments, we demonstrate that STT-MRAM is a candidate for the memory hierarchy of embedded systems, due to the higher densities and reduced leakage of MRAM.We demonstrate that adopting STT-MRAM in L1 and L2 caches mitigates the impact of higher write latencies and increased current draw due to the use of MRAM. With the correct system-on-chip (SoC) design, we believe that STT-MRAM is a viable alternative to SRAM, which minimizes leakage current and the total power consumed by the SoC. Full article
(This article belongs to the Special Issue Selected Papers from FTFC 2013 Conference)
Open AccessArticle The Impact of Process Scaling on Scratchpad Memory Energy Savings
J. Low Power Electron. Appl. 2014, 4(3), 231-251; doi:10.3390/jlpea4030231
Received: 11 June 2014 / Revised: 22 August 2014 / Accepted: 1 September 2014 / Published: 9 September 2014
PDF Full-text (630 KB) | HTML Full-text | XML Full-text
Abstract
Scratchpad memories have been shown to reduce power consumption, but the different characteristics of nanometer scale processes, such as increased leakage power, motivate an examination of how the benefits of these memories change with process scaling. Process and application characteristics affect the amount
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Scratchpad memories have been shown to reduce power consumption, but the different characteristics of nanometer scale processes, such as increased leakage power, motivate an examination of how the benefits of these memories change with process scaling. Process and application characteristics affect the amount of energy saved by a scratchpad memory. Increases in leakage as a percentage of total power particularly impact applications that rarely access memory. This study examines how the benefits of scratchpad memories have changed in newer processes, based on the measured performance of the WIMS (Wireless Integrated MicroSystems) microcontroller implemented in 180- and 65-nm processes and upon simulations of this microcontroller implemented in a 32-nm process. The results demonstrate that scratchpad memories will continue to improve the power dissipation of many applications, given the leakage anticipated in the foreseeable future. Full article
Figures

Open AccessArticle 39 fJ/bit On-Chip Identification ofWireless Sensors Based on Manufacturing Variation
J. Low Power Electron. Appl. 2014, 4(3), 252-267; doi:10.3390/jlpea4030252
Received: 8 July 2014 / Revised: 18 August 2014 / Accepted: 4 September 2014 / Published: 12 September 2014
Cited by 1 | PDF Full-text (425 KB) | HTML Full-text | XML Full-text
Abstract
A 39 fJ/bit IC identification system based on FET mismatch is presented and implemented in a 130 nm CMOS process. ID bits are generated based on the ΔVT between identically drawn NMOS devices due to manufacturing variation, and the ID cell structure allows
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A 39 fJ/bit IC identification system based on FET mismatch is presented and implemented in a 130 nm CMOS process. ID bits are generated based on the ΔVT between identically drawn NMOS devices due to manufacturing variation, and the ID cell structure allows for the characterization of ID bit reliability by characterizing ΔVT . An addressing scheme is also presented that allows for reliable on-chip identification of ICs in the presence of unreliable ID bits. An example implementation is presented that can address 1000 unique ICs, composed of 31 ID bits and having an error rate less than 10-6, with up to 21 unreliable bits. Full article
(This article belongs to the Special Issue Low Power Wireless Sensing and Internet of Things)

Review

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Open AccessReview Study of Back Biasing Schemes for ULV Logic from the Gate Level to the IP Level
J. Low Power Electron. Appl. 2014, 4(3), 168-187; doi:10.3390/jlpea4030168
Received: 14 March 2014 / Revised: 20 June 2014 / Accepted: 27 June 2014 / Published: 7 July 2014
Cited by 1 | PDF Full-text (1151 KB) | HTML Full-text | XML Full-text
Abstract
Minimum energy per operation is typically achieved in the subthreshold region where low speed and low robustness are two challenging problems. This paper studies the impact of back biasing (BB) schemes on these features for 28 nm FDSOI technology at three levels of
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Minimum energy per operation is typically achieved in the subthreshold region where low speed and low robustness are two challenging problems. This paper studies the impact of back biasing (BB) schemes on these features for 28 nm FDSOI technology at three levels of abstraction: gate, library and IP. We show that forward BB (FBB) can help cover a wider design space in terms of the optimal frequency of operation while keeping minimum energy. Asymmetric BB between NMOS and PMOS can mitigate the effect of systematic mismatch on the minimum energy point (MEP) and robustness. With optimal asymmetric BB, we achieve either a MEP reduction up to 18% or a 36× speedup at the MEP. At the IP level, we confirm the MEP configurability with BB with synthesis results of microcontrollers at 0.35 V.We show that the use of a mix of overdrive FBB voltages further improves the energy efficiency. Compared to bulk 65 nm CMOS, we were able 28 nm FDSOI to reduce the energy per cycle by 64% or to increase the frequency of operation by 7×, while maintaining energy per operation below 3 µW/MHz over a wide frequency range. Full article
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2013)

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