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J. Low Power Electron. Appl. 2014, 4(2), 110-118; doi:10.3390/jlpea4020110
Published: 23 May 2014
Abstract: A threshold voltage (Vth) controllable multigate FinFET on a 10-nm-thick ultrathin BOX (UTB) SOI substrate have been investigated. It is revealed that the Vth of the FinFET on the UTB SOI substrate is effectively modulated thanks to the improved coupling between the Si channel and the back gate. We have also carried out analysis of the Vth controllability in terms of the size dependence such as the gate length (LG) and the fin width (TFin).
Recently, complementary metal oxide semiconductor (CMOS) device technology has faced several difficulties. Short channel effects (SCEs) such as threshold voltage roll-off and sub-threshold slope (s-slope) degradation caused by the reduced drivability of the gate electrode cause significant increase in power consumption and become a limiting factor in MOS devices [1,2]. In addition, variability of the CMOS device increases and reduces the yield of the CMOS circuit . Fortunately, fin-type MOS field effect transistors (FinFETs) provide a potential solution for the nano-scale CMOS technology thanks to their high drive current while maintaining a low sub-threshold (s-) slope [4,5]. However, for FinFETs, adjustment of the threshold voltage (Vth) is still a tough issue. One way of controlling the Vth of the MG MOSFET is to tune the work function of the gate electrode . However, selection of the metal with the appropriate work function is difficult. A doped silicon channel is effective for Vth tuning; however, it cause severe variability due to the random dopant fluctuation [7,8].
The other way of controlling the Vth of the FinFET is by using the substrate back bias using the SOI substrate [9,10]. In fact, Vth control by the substrate back bias has been investigated for the planar devices [11,12,13,14]. However, effectiveness of the back gate bias on the Vth of the FinFET is different due to the narrow channel. Recently, we have demonstrated a flexible Vth tuning for the FinFET by controlling the back bias using a 10-nm-thick ultra-thin (UT) buried oxide (BOX) silicon on insulator (SOI) substrate to demonstrate effectiveness of UTBOX for the vth control of the FinFET [15,16]. Moreover, we have flexibly controlled the Vth by adding the second gate of the independent-double-gate FinFET . In this study, we have extended the analysis of Vth flexibility in terms of the LG and the TFin dependence of the Vth controllability using the 10 nm-thick UTBOX SOI substrate.
2.1. MOS Capacitor
Prior to the device fabrication, we have evaluated the quality of the UTBOX by comparing the characteristics with thermal SiO2. The test structure used in this study is illustrated in Figure 1. The thermal SiO2 grown at 850 °C is covered with the chemical-vapor-deposited 50-nm-thick poly-Si. Ion implantation was carried out into the top Si layer to fabricate the gate electrode. The thermally grown SiO2 with the polycrystalline-Si electrode is used as a reference sample.
2.2. Device Fabrication
In this study, we have used 200-mm UTBOX SOI wafers as an initial material and have fabricated the FinFET devices on a UTBOX SOI substrate. The ellipsometrically measured thickness of the UTBOX was 10 nm. We have also fabricated the FinFET on the 120-nm-thick BOX for comparison. The fabrication process flow is summarized in Figure 2. A 50-nm-thick non-doped silicate glass (NSG) layer and the electron beam (EB) resist masks were formed to make hard masks on the wafer. To fabricate vertical Si-fins, the SOI layer was etched by a conventional reactive ion etching (RIE) using a Cl2 inductively coupled plasma (ICP) as schematically shown in Figure 2. After the Si-fin etching, a 2.5-nm-thick gate-oxide was formed at 850 °C followed by the TiN and n+ polycrystalline-Si (poly-Si) gate formation using EB lithography and the RIE. After the gate electrode was formed, a shallow implantation into the extension of the source/drain (S/D) was performed. To distribute impurity atoms uniformly into the vertical channel, 60-degree tilted implantation was carried out at an acceleration energy of 5 keV and a dose of 2 × 1014 cm−2 in each side . S/D implantation was performed at an acceleration energy of 10 keV and a dose of 1.5 × 1015 cm−2 after a 50-nm-thick gate-sidewall was formed by using CVD grown SiO2. The acceleration energy was set to 10 keV to preserve the seed-crystal layer for the recrystalline annealing. Figure 3 shows the cross sectional transmission electron microscope (TEM) image of the fabricated FinFET and the plane scanning electron microscope (SEM) image of the SRAM cell. The FinFET on the UTBOX SOI is successfully fabricated. The fin height was measured as 30 nm.
3. Results and Discussion
Figure 4 compares capacitance-voltage (C-V) characteristics of the UTBOX layer and the thermal SiO2. It is found that the C-V characteristics of the UTBOX layer are similar to that of the thermal SiO2. The capacitance equivalent thickness (CET) of the UTBOX is measured as 11.5 nm and the uniformity of the UTBOX thickness is as good as that of the thermal SiO2. Figure 5 compares the current-voltage (I-V) characteristics of the MOS capacitor using the UTBOX and the thermal SiO2. The I-V characteristics of the MOS capacitor with the same dielectric thickness are also the same. Figure 6 shows the gate voltage of the MOS capacitor where the leakage current exceeds 10−7 A/cm2 as a function of the oxide thickness. The gate voltage of the UTBOX completely follows the trend of the thermal SiO2. These results strongly indicate that quality of the UTBOX and its interface is as good as that of the thermal SiO2.
Figure 7 shows the ID-VG characteristics of the FinFET with the UTBOX SOI and the conventional thick BOX SOI. We revealed that the ID-VG characteristics the FinFET on the UTBOX SOI could be flexibly modified by applying the substrate bias voltage. We also found that the FinFET with the thick TFin was effective for the Vth modulation. Figure 8 shows the Vth as a function of the Vsub. The Vth is taken by the constant current method. The ID-VG characteristics are fixed and thus the Vth is fixed with the conventional thick BOX substrate. Also, the effectiveness of the thick TFin for the Vth modulation is clearly shown. This is caused by the increased coupling between the Si body and the back gate.
Figure 9 summarizes the size dependence of the body factor γ determined by the ΔVth/ΔVsub. The γ is increased by increasing the TFin supporting the effectiveness of the thick TFin for the Vth modulation. In contrast to the TFin dependence, the opposite trend with the LG is shown and the γ is increased by reducing the LG. Moreover, the γ exceeded more than 0.1 with the 70-nm-thick fin thanks to the 10-nm-thick UTB SOI. To understand this LG dependence, the short channel effect represented by the Vth roll-off is evaluated as shown in Figure 10. We found that the Vth roll-off is more sever for the FinFET with the positive Vsub, small LG, and the thick TFin. Thus, the γ becomes higher for the FinFET with the small LG and the thick TFin due to the Vth roll-off. This result is consistent with the previous report on the nanowire FET with the 20-nm-thick BOX SOI .
Figure 11 shows the s-slope of the FinFET as a function of the LG. The increase of the s-slope by reducing the LG due to the short channel effect is clearly shown. It is noteworthy that the s-slope of the FinFET with the negative Vsub is smaller than that of the positive Vsub. Thus, the body bias is also effective for suppressing the short channel effects.
The Vth controllable FinFETs using the 10-nm-thick UTB SOI substrate have been successfully fabricated and controllability of the Vth is analyzed in terms of the size dependence. It is shown that the body factor is increased by increasing the TFin and reducing the LG and it exceeded above 0.1 thanks to the 10-nm-thick UTBOX SOI. The back gate bias is also effective for the reduction of the s-slope. Thus, the UTBOX SOI is promising for the modulation of the Vth and improvement of the short channel effects for the scaled FinFET.
Kazuhiko Endo fabricated the devices and coordinated the overall research. Shinji Migita fabricated the MOS capacitor and investigated quality of the BOX layer. Yuki Ishikawa, Takashi Matsukawa, Shin-ichi O’uchi, Junji Tsukada fabricated the devices. Hitomi Yamauchi observed TEM images. Wataru Mizubayashi, Yukinori Morita, Hiroyuki Ota, and Meishoku Masahara designed the fabrication process and discussed the results.
Conflicts of Interest
The authors declare no conflict of interest.
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