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Multi-Threshold Dual-Spacer Dual-Rail Delay-Insensitive Logic (MTD3L): A Low Overhead Secure IC Design Methodology
J. Low Power Electron. Appl. 2014, 4(1), 44-62; doi:10.3390/jlpea4010044

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Article Published27 February 2014 14:14 CET
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article files uploaded.27 February 2014 14:16 CET
article files uploaded.27 February 2014 14:16 CET
article files uploaded.27 February 2014 14:16 CET
article files uploaded.27 February 2014 14:16 CET
article files uploaded.27 February 2014 14:16 CET
article files uploaded.27 February 2014 14:16 CET
article files uploaded.27 February 2014 14:16 CET
article files uploaded.27 February 2014 14:16 CET
article files uploaded.27 February 2014 14:16 CET
article files uploaded.27 February 2014 14:16 CET
article files uploaded.27 February 2014 14:16 CET
article files uploaded.27 February 2014 14:16 CET
J. Low Power Electron. Appl. EISSN 2079-9268 Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert