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This paper presents a model of inductor based DC-DC converters that can be used to study the impact of power management techniques such as dynamic voltage and frequency scaling (DVFS). System level power models of low power systems on chip (SoCs) and power management strategies cannot be correctly established without accounting for the associated overhead related to the DC-DC converters that provide regulated power to the system. The proposed model accurately predicts the efficiency of inductor based DC-DC converters with varying topologies and control schemes across a range of output voltage and current loads. It also accounts for the energy and timing overhead associated with the change in the operating condition of the regulator. Since modern SoCs employ power management techniques that vary the voltage and current loads seen by the converter, accurate modeling of the impact on the converter efficiency becomes critical. We use this model to compute the overall cost of two power distribution strategies for a SoC with multiple voltage islands. The proposed model helps us to obtain the energy benefits of a power management technique and can also be used as a basis for comparison between power management techniques or as a tool for design space exploration early in a SoC design cycle.

This paper presents a model for inductor based DC-DC converters and its application to quantify the benefits of power management techniques for ultra low power (ULP) SoCs. Various power management techniques, such as dynamic voltage and frequency scaling (DVFS), clock gating, and power gating are now commonly employed in many SoCs. However, the power benefits of these techniques cannot be quantified accurately without assessing their impact on the DC-DC converter that delivers power. For example, DVFS uses a high voltage to support higher performance and lower voltage to save power. However, changing the output voltage of a DC-DC converter incorporates significant power overhead, and the efficiency can vary widely across voltage and current loads. These overheads may offset the benefits from DVFS. There is a need to characterize the benefits of power management techniques like DVFS in conjunction with their impact on the DC-DC converter. This is particularly important for ultra-low energy near- or sub-threshold systems that operate in a very dynamic power environment, and whose power constraints are stringent. This paper presents a model [

Structure of the proposed model. (

_{L}

The energy savings for a power management technique are typically reported at the load circuit operating voltage and load level in literature [_{L} is discharged to a lower voltage by dissipating its stored energy. The actual benefits can be obtained by taking these losses and overhead into account. _{PAR}), and capacitor (C_{ESR}) cause the conduction loss, which is determined by the load current and output voltage. These losses are all a function of the operating condition. The proposed model accurately predicts the trends in behavior of DC-DC converters across topologies implementing both pulse width modulation (PWM) and pulse frequency modulation (PFM) control schemes.

Loss mechanisms inside a typical switching DC-DC converter.

In order to model DC-DC converter trends and to capture the impact of DC-DC converters on power management strategies, it is essential to account for the converter efficiency, which is the power delivered to the load divided by the total power drawn by the converter. This efficiency of the DC-DC converter is a function of its output load, output voltage (

Voltage and frequency are varied in DVFS to trade off power consumption with speed. This changes the load current and output voltage of the DC-DC converter, which changes its efficiency. In this section, we define a model that captures the change in efficiency that results from changing load conditions. One prior work [_{L}_{L}_{LO}

Instead, we propose a model that accurately captures the trends in the efficiency of the DC-DC converter in terms of the peak and minimum efficiency values of the converter, which can be either predicted, specified as targets, or pulled from prior work. To derive this simplified model, we begin by following previous work [_{2} is the peak efficiency occurring at load _{1} is the minimum efficiency at a given load. For the verification of the model proposed in Equation (2), let us consider the following cases.

For a light load condition in Equation (1),

So the power loss given by Equation (1) in the buck converter takes the form of

The efficiency of the converter will be given by power delivered (_{L}

Expanding Equation (3) using Taylor’s series we get:

It is clear from Equation (3) that the efficiency decreases as load current decreases for the cases of light load conditions on the converter. The proposed equation in the model is given by:

This expression also decreases for the light load condition, capturing the correct behavior of DC-DC converter efficiency trend. We know from Taylor’s series that:

Since,

So the efficiency equation in Equation (2) can be rewritten as:

The proposed model in Equation (2) for the DC-DC converter reduces to Equation (6) under light load, which follows the behavior of DC-DC converter reported in literature [_{2} in Equation (2) can be obtained by equating the constants in Equations (4) and (2),

Equations (2) and (6) are not bounded for the cases when I_{L} becomes very small, but it can predict the behavior for light load condition in a PWM control switching scheme based DC-DC converter with less than 5% error.

Now consider the case when load is very high compared to the point of peak efficiency. The constant _{DSAT}_{DSAT}_{L}^{2}R loss increases, because of the increase in current and because of the increase in resistance caused by that increase in current. For a high load we know that:

so the power loss in the buck converter using equation (1) of [

The equation for efficiency can be written as:

This expression shows that efficiency decreases as the load current increases. Using Taylor series expansion, this expression can be written as,

In the proposed equation in this paper, Equation (2), the efficiency also decreases for the higher load. Expanding (2) using Taylor’s series,

Equations (10) and (11) follow closely, with constants _{2}, _{1}, _{1}, _{L}

While Equations (1), (4) or (10) can be more analytical versions of the DC-DC converter efficiency formulation, they are not very useful for early design space exploration or for studying system level power management techniques because of the unknown constants. In contrast, the compact model in Equation (2) can be expressed in terms of peak efficiency and minimum efficiency, making it easy to use.

In the PFM control scheme with a constant peak inductor current, the switching and conduction loss scale with frequency, and the efficiency remains flat for higher loads. The power loss is given by

where

Using _{Out}_{L}

Equation (14) shows that the efficiency increases and becomes constant as load increases. This happens because power loss in PFM schemes scales with the load. At light load condition, the static loss dominates reduces the efficiency.

The equations we have provided accurately model the trends for PWM, PFM, and combinations of those control schemes.

Efficiency Variation with load current in (_{2} = 0.9, _{1} = 0.68 and _{L}_{2} = 0.88 and a = 5 × 10^{−5}.

_{2} as the peak efficiency reported in the corresponding paper and _{O}_{1} is obtained experimentally based on [_{1} = 10 for all the papers ([

We also compared the model with reported works that employ the PFM switching scheme. _{2} as the peak efficiency reported in the corresponding paper. The constant

Comparison of the load equation with measured work in literature. (

To further illustrate the usefulness of the model, we also compared it with the schemes where both PFM and PWM schemes are employed. This is often done to increase the range of load a converter can support. _{O}

The proposed model is accurate in predicting the efficiency trend with respect to the load if the control scheme is PWM or PFM. Also, an approximate peak efficiency of a DC-DC converter can be obtained very early in the design cycle as it is dependent on the technology, size of the inductor, and ripple on rails. Therefore, the model can be employed for analyzing the DC-DC converter overheads early in design while implementing power management techniques.

The peak efficiency of an inductor based DC-DC converter decreases with a decreasing output voltage. For a given load current, the switching loss and conduction loss of the converter remain the same. The decreased output power level at lower voltages results in a decreased efficiency. The efficiency as a function of voltage can be modeled as:

_{O}

Dynamic efficiency variation with current and voltage.

The settling time of a converter is the time it takes to reach the desired supply voltage. A typical converter has a large inductor and a large filter capacitor that makes the settling time very large (few µs to ms [_{O}

when output voltage is charged to

The change in the output voltage of a converter results in a change of the stored energy on the capacitance of the supply voltage rail of the load blocks. Some of this stored energy is dissipated if the new voltage is lower than the previous voltage, whereas energy is consumed from the source supply, _{in}_{1} and _{2} are the new and previous voltages of the converter. If _{1} is greater than _{2}, work is to be done by the supply _{in}_{1} is less than _{2}, no work is done by _{in}

In some cases, the voltage on the capacitor is not immediately discharged to lower voltage. VDD slowly discharges from _{2} to _{1} while running workloads. In such cases _{C}

In summary, this section has derived models for inductor based DC-DC converter efficiency for both PWM and PFM control schemes at a fixed load and provided equations for modeling the overheads that arise when the loads change. In the next section, we examine an example of how to apply these models in the evaluation of power management schemes like DVS.

The DC-DC converter model can be used for assessing a variety of block level power management techniques. Since the model captures both the efficiency of the converter for fixed loads and the cost of making dynamic changes to the converter output voltage and load, we can use it to model system level implementations of varying complexity. In the most basic case, the model can provide additional insight into the system level cost of reducing the voltage delivered to a block or to a chip.

For example,

Energy consumption for a microcontroller across voltage with and without consideration of the DC-DC converter efficiency.

Further, the DC-DC model can help designers to choose the optimal specification for a converter to use for a given block or chip. This is especially important for embedded converters serving extremely low power systems like the one in [

(

In addition to supporting the co-design of embedded DC-DC converters, our model can enable higher level comparisons of power management techniques that apply to multiple blocks. The next example illustrates the application of our model to two different power management strategies.

DVFS is commonly used to save power in a SoC by changing the supply voltage at the full chip level. Even larger energy savings can be realized by implementing block level DVFS, so that each block can use a voltage that is best matched to its own workload.

Dedicated DC DC converter per block.

In this section, we establish the framework for computing the system level energy consumption of a multiple block DVFS system, where individual DC-DC converters are modeled using the equations from

Operating condition for dedicated DC DC.

_{op}

Each block is modeled as a chain of inverters with different depths. The delay of the block is calculated as its time of operation. The power supply level changes for 100 iterations. The rate at which the voltage changes to a new value is varied from 10 ns to 1 ms. The energy dissipation in each case is compared with a single VDD (always 1.2 V) block. _{OP} greater than 1µs with a maximum benefit of more than 150% achievable at slower rates of VDD transitions. This implies that, for these assumptions, the 5 VDD system would save energy relative to the single VDD system when transitioning VDD to adapt to changes in the workload that are slower than ~1 µs.

This section applies the DVFS modeling approach to a different DVS implementation.

Energy Savings with rate of Voltage Scaling.

Panoptic dynamic voltage scaling (PDVS): Block level voltage scaling technique.

We reproduce the operating condition of a block from _{1} < 0.8 V) for T1 time, PDVS accomplishes it by connecting the block to 0.4 V for _{11} and 0.8 V for _{12}, such that _{11} + _{12} = _{1} of _{11} and _{12} are such that the performance of the block does not change. A final operating condition is given by

PDVS operating condition evaluation. (

The load on each supply will change depending on the blocks that are connected to it and results in a continuous time varying load on each supply. We include time to obtain the energy. Each supply has larger load variation which will have an impact on the overall efficiency. The total energy is given by,

We keep the same system set-up as was used for the dedicated DC-DC converter case. It should be noted that there will be an insignificant overhead of settling time in this case. We assume a capacitive load of 20 pF on each block, since the local block virtual VDD rail switches instead of the total chip-wide VDD rail (with all of its decoupling capacitance).

Energy Benefits of PDVS and Dedicated DVFS.

Energy Benefits of PDVS for different values of the virtual VDD capacitance of the block.

A model that can accurately capture the behavior of inductor based DC-DC converters in a dynamic environment has been presented. The converter model has been validated and compared with measured results from a variety of DC-DC converter topologies in existing literature. We use this model to study block level power management techniques for a SoC by incorporating it into a higher level model of the multiple block system. The system model predicts that there is a break-even time before the benefit of voltage scaling becomes positive, and our proposed modeling framework provides a quantitative means for comparing multiple power management techniques in a given use case scenario.

This work was supported in part by the NSF NERC ASSIST Center (EEC-1160483) and by DARPA through a subcontract with Camgian Microsystems.