The minimum energy point (MEP) denotes the operating point where the energy per operation is minimized. The energy per operation is composed of switching and leakage energy. Theoretically, the MEP for static CMOS logic depends on the technology [5]. For a given technology, the absolute MEP is tied to a certain threshold voltage. For newer technologies, there is typically a choice of devices with different threshold voltages (e.g., high threshold voltage, HVT, or low threshold voltage, LVT). These devices have their own respective MEPs which may differ from the absolute MEP. When the threshold voltage is fixed, the MEP is mainly dependent upon the technology and activity factor. For example, a 90 nm CMOS process has a MEP that ranges from 250 mV to 400 mV depending on the architecture and activity factor [3,5].

The MEP is situated in the subthreshold region for technologies down to 45 nm [5]. Figure 1 shows the MEP for a 65 nm process. A ring oscillator, with an activity factor (α) of 0.1, was used to generate the MEP curves. Different process corners change the leakage energy and, thus, change the MEP.

As shown in Figure 1, the MEP of 65 nm CMOS lies in the subthreshold region. The functional boolean design of static CMOS gates for the subthreshold region is comparable to a design for the strong inversion region with a few exceptions, which are mainly due to logic level deterioration due to leakage. However, in the subthreshold region, I_ds has exponential dependencies [3]:

where I_O is the drain current when V_gs = V_t, V_t is the threshold voltage, n is the subthreshold slope factor, and V_th is the thermal voltage. As can be seen from Equation (1), PVTA variations cause exponential changes in the subthreshold current (e.g., a change in V_t due to process variations).

To show the impact of the exponential effects of Equation (1), different process corners and temperatures were simulated on an inverter chain. As shown in Figure 2(a), at 1.2 V, the SS and FF corners are, respectively, 1.26 and 0.78 times the delay at the TT corner. At 0.3 V, the SS and FF corners are, respectively, 2.56 and 0.39 times the delay at the TT corner. Low temperatures further exacerbate the variation impact. For example, the delay is 60 times larger at a voltage of 0.3 V, a temperature of −40 °C, and the SS corner, than at the TT corner. Figure 2(b) shows the coefficient of variation (σ/µ) for the local variance at 0.3 V and 1.2 V. The σ/µ at 0.3 V is 10 times larger than at 1.2 V. A 1000-point Monte-Carlo is used to generate both Figure 2(a) and (b).

Several subthreshold processors have been presented previously. In a recent study by Kwong et al. a 16-bit processor that is based on the MSP430 microcontroller and built in 65 nm is presented [9]. The processor achieves a frequency of 434 kHz and consumes 27.2 pJ/cycle at a V_dd of 0.5 V. In another study, Zhai et al. present an 8-bit custom ISA processor fabricated in 130 nm [10]. The processor achieves a frequency of 833 kHz and consumes 2.6 pJ/instruction at a V_dd of 360 mV.

Typically, the functionality of processors during variations in temperature is not analyzed in modern low voltage processors. Recently, Bol et al. addressed the issue of global PVT variation by utilizing a compensation system [11]. However, both the study by Kwong et al. [9] and the one by Zhai et al. [10] show frequency measurements over temperature but do not comment on the functionality of the circuit during variations in temperature. Prior studies also rarely focus on active variance robustness methods are also slightly commented. In a study by Hanson et al. [12], body bias is used to achieve variance robustness in 130 nm technology. However, the effect of body bias decreases with smaller process nodes [2].

Timing-error detection (TED) has been shown to remove PVTA variation-incurred safety margins [6,7,13], which would conventionally guarantee operation across all corners with a sufficient yield. The lower safety margins can then either be turned into power savings (i.e., lower V_dd [13]) or a higher yield [6]. The TED methodology is based on having the system operate at a voltage and frequency point in which the timing of critical paths fails intermittently. The failed timing occurrences are detected and corrected, for example, with an instruction replay system. If the error rate is low enough (e.g., 0.04% in a study by Blaauw et al. [13]), then an energy consumption benefit is achieved as a result of operating at a lower V_dd. If the error rate is too high, the instruction replay portion of the TED system begins to consume too much energy.

The key component of a TED system is an error-detection sequential (EDS) circuit. EDS circuits generate error signals when the path setup timing fails. This is also known as late signal detection, and it is a well-known synchronization concept. With a TED system, the EDS circuits are placed at critical logic paths where timing errors can occur. When using an EDS circuit, a timing error is flagged when a transition of D occurs in the TED window, as shown in Figure 3(a). The TED window for the EDS circuits can be tied to the clock signal [13], or it can be independently generated [6].

There are two main types of EDS architectures: a dynamic node [13,14,15] and a delayed shadow latch [7,8]. Of these architectures, the dynamic node can achieve a lower power and lower clock node capacitance. The dynamic node implementation typically uses an inverter delay chain and a logic gate (e.g., XOR) to produce a signal pulse. The signal pulse, or PULSE, as shown in Figure 3(a), is used to change the state of a dynamic node and generate a timing error signal. The inverters and logic gates used to produce the PULSE signal require a high level of precision across all PVTA variations, especially at low voltage levels. In addition to being robust, the size of the PULSE should be minimized since it limits the speed of the entire TED system as is further explained in Section 3.3.

Figure 3(b) shows a high-level block diagram of a TED system using EDS circuits rather than normal FFs. The EDS circuits, called TEDsc, are explained in more detail in Section 3.3. Since the TED window is reserved for detecting timing errors in the previous clock cycle, no signals from the current clock cycle can arrive within the TED window. A signal that propagates too quickly through the combinational logic leads to a false error being flagged. Thus, the minimum delay for the combinational logic is the TED window. To prevent these false errors from being generated because of fast transitions, additional buffers are required as is described in more detail in Section 3.4.

In practice, the minimum and maximum delay are both limited by the design uncertainties rather than by the logical operation. More specifically, the design of the EDS circuit defines two uncertainty regions, during which an error is captured with a finite probability (Figure 4). Local variation in an EDS circuit results in an uncertainty region at the microprocessor’s clock signal (CLK) positive and negative edges, as shown in Figure 4. Near the CLK edges, the probability that N EDS circuits in a system would generate a timing error may not be 100% at some positions of the CLK (i.e., uncertainty regions A₂ an A₄). In Figure 4, t_edge2 and t_edge4 are defined as the position before the positive CLK edge at which the probability of a timing error is 100% and the position before the falling CLK edge at which the probability of detecting a timing error is 0%, respectively.

Thus, the uncertainty region can be defined as the location within a CLK cycle (T_CLK) in which the probability of a timing error for N EDS circuits (EDS₀ to EDS_N) is between 0 and 100%:

A study by Bull et al. refers to a similar concept at the positive CLK edge as setup pessimism [6]. For new processes or applications with weak to moderate inversion voltage levels, it is essential to understand the size and location of the uncertainty region. Since the uncertainty region is largely determined by the EDS circuit, it needs to be considered at the same time as the EDS design.

The architecture of the general purpose processor is an accumulator-based style in which the second operand is always the accumulator register. The processor core is pipelined into three stages: “Fetch”, “Execution”, and “Write”. The instruction memory, which has a size of 256 bytes, resides in a separate block; the size of the block is 256 bytes. Due to design-time resource constraints, we do not consider here the memory design associated with the processor. The memory is designed for functionality and is not optimized in any way.

As explained in Section 2, the EDS-cells are inserted on the critical paths. The three-stage pipeline is configured so that the first stage, “Fetch,” and the last stage, “Write,” are shorter than the “Execute”. Thus, the “Fetch” or the “Write” stages never fail before the “Execute” stage, and only the paths on the “Execute” stage had to be considered as potential candidates for critical paths. This design choice limits both the length of the clock cycle and the number of EDS circuits, and it facilitates the placement of the EDS latches by limiting the critical paths to one pipeline stage of the core. Since the error signals from the EDS circuits are combined using a logical OR tree, this design choice keeps the OR tree shallow. This simplifies the error control, keeps the control delay short, and reduces the control overhead. The study by Bull et al. solves this control delay by adding two stages to the pipeline [6]; in this study the clock cycle remains unchanged, but the clock cycles per instruction may increase. In the solution presented in this paper, the length of the clock cycle may be limited depending on how balanced the logic is between the pipeline stages of the core.

Figure 5 shows the block diagram of the core. The paths that can generate timing errors are highlighted in red. The core contains a total of 20 EDS circuits; 8 of them are in the accumulator register, 8 of them in the register file write buffer, and 4 of them are used for the arithmetic and logic unit (ALU) flags. The error signal paths are highlighted in blue.

The design requires more circuit modifications than a conventional design. For example, we inserted buffers on the fastest paths during the place and route stage to ensure that the hold time requirement for the TED error detection window was met. During the "Decode" stage, there are significant modifications to allow for error recovery.

Both the architecture of the core and the timing constraints set during the synthesis ensure that timing errors can only occur during the “Execution” stage. A timing error occurs when a data signal on a critical path arrives too late to the subsequent EDS data storage element (i.e., the latch). At this point, incorrect values can be written to the accumulator and register file. In addition, the Program Counter (PC) and the stack might be incorrectly updated due to incorrect ALU flags.

After a timing error, the core needs to be able to restore the previous state using the following methods. First, when a timing error is detected, the system operation is halted by disabling the clocking. Next, the data stored during the previous cycle is restored (i.e., the previous values of the PC, the accumulator, and the last stack push/pop are stored in the data FFs). Thus, the system stage becomes the previous stage. Finally, the failed instruction is re-executed using two clock cycles instead of one to guarantee an error-free operation. After the two clock cycle execution, the normal operation frequency is restored.

The error signals are not distinguished from each other, but are, instead, combined with one another. Thus, the system does not know which path generated an error. This arrangement is simple and it enables fast operation. With regards to functionality, it is not necessary to know on which path an error occurred.

Correct TED operation requires that signals do not arrive too early or late with respect to a TED window (TED_win,N), since these signals are not accounted for in real time at the system level or within the EDS. A signal that arrives too early has an insufficient delay time and, thus, it incorrectly arrives in the previous TED detection window (TED_win,N−1). In other words, a timing error is incorrectly generated (false positive). False positives are avoided by constructing correctly sized delay buffers. When a signal arrives too late (i.e., at TED_win,N+1), it means that the delay is too large and that an error has not been correctly detected. To avoid these false negatives, timing constraints within the design are implemented to ensure that a signal cannot be delayed too greatly.

TEDsc is an EDS circuit [Figure 6 (a)] that uses subthreshold source-coupled logic (STSCL) to detect timing errors [15]. Depending on the logic depth, the leakage current, the activity factor, and the operation frequency of a system, STSCL can have several advantages over static CMOS (e.g., tunability, reduced power consumption, and a decreased sensitivity to supply noise [16,17]). STSCL has been shown to be advantageous for ultra-low-power (ULP) systems.

An STSCL gate is composed of a network of differential NMOS pairs, an adjustable PMOS load (M₃,M₄) with output resistance R_P, and an adjustable tail current I_SS [Figure 7(a)]. The NMOS pairs are used to construct logic gates. The voltage swing is defined as V_SW = R_P·I_SS, and it is maintained by dynamically adjusting the size of R_P and the magnitude of I_SS. Since I_SS can be reduced to the pA range, R_P needs to be in the GΩ range to achieve a proper V_SW (i.e., V_SW > 150 mV). By connecting the bulk of the PMOS load devices to the drain, a large R_P is achieved without excessively large transistor lengths [16,17].

The size of R_P and the magnitude of I_SS are both adjusted by the voltage swing control (VSC) block as shown in Figure 7(b). The VSC decreases the dependence on global variations (e.g., supply noise, temperature fluctuations, and ageing). The VSC ensures a voltage swing greater than 150 mV across all global variations. The VSC for TEDsc uses a two-stage, miller-compensated opamp for ASW. The opamp is able to maintain an open loop gain of 40 dB for all the global process corners. The bias voltage (V_P) from one VSC can be used for a large number of TEDsc gates [16].

Since TEDsc uses STSCL, it has the unique ability to adjust its D-to-timing error delay (D-ERRf delay); this results in an adjustable TED window. This ability to adjust the D-ERRf delay can be explained by first understanding that during a D transition, TEDsc requires a minimum amount of charge (Q_emin) to move from the dynamic output node in order to induce a differential timing error [15]. Reaching Q_emin is dependent on I_TEDsc and the β-delay that is extended under the CLK high (i.e., t_βCLK). For example, when I_TEDsc is increased, the TED window is widened at both of the CLK’s edges since the required t_βCLK is decreased to meet Q_emin.

The starting point of the TED window (t_a2 + t_edge2 from Figure 4) has two important implications. First, at the positive CLK edge, an excessively early starting point of the TED window (i.e., (t_a2 + t_edge2)/T_CLK is too large) does not allow for the maximum clock frequency to be reached and, thus, the energy consumption is increased. Second, for a flip-flop based pipeline, an overly delayed TED window starting point (i.e., due to a low I_TEDsc) does not correctly report all setup time failures as timing errors, which results in a non-functional design. In the presence of large global variation susceptibility, as found in subthreshold, the tunable TED window enables fine tuning on the system level.

Fine tuning of the TED window is achieved by adjusting I_TEDsc within TEDsc. To understand how the I_TEDsc affects the TED window, three TEDsc circuits were measured on the same die. TEDsc and VSC used the following settings: V_dd,scl = 400 mV, V_L = 200 mV, and V_dd = 300 mV. A total of 500 positions of D were applied as input to TEDsc. There were 16,384 transitions of D at each of the 500 positions. The duty cycle of the CLK was at 50%. The TED window for TEDsc in Figure 8 is located between (Position of D Transition) 250 and 500. Figure 8 shows the error probability of the three TEDsc circuits as a function of the D transition. For this measurement, the frequency of the CLK was 10.37 kHz.

As shown in Figure 8, by adjusting I_TEDsc, TEDsc can adjust its D-ERRf delay. This subsequently makes fine tuning of the TED window (and the uncertainty region) possible. For example, to reduce the D-ERRf delay, I_TEDsc was increased from 300 pA to 1.56 nA (Figure 8). In previous designs [14,15], the uncertainty region and TED window have been fully defined at design time, which is not favorable for weak inversion TED design. Simulations showed an uncertainty region (i.e., A₂, A₄) of approximately the same size as found in measurement [15].

As the microprocessor’s performance is altered by local and global variations, it is essential that the EDS circuit operate correctly and accurately. Through simulations, TEDsc was shown to be robust to both local and global variations. Local variations were accounted for by applying Monte-Carlo simulations at each process corner (i.e., TT, FF, SS, SF, and FS). This simulation also showed a robustness to global process corners due to the VSC. Additionally, TEDsc showed a correct functionality from −40 °C to 90 °C as a result of the VSC. Using STSCL also reduces the sensitivity of TEDsc to changes in the supply voltage [17]. In addition, the probability of a fast change in the supply voltage at the exact same time that D transitions is low. To verify this, we applied a sawtooth-wave ripple voltage from 0 to 40 mV and a frequency from 10 MHz to 100 MHz to TEDsc; the correct functionality was shown under these ripple conditions.

The effects of local variations on TEDsc are minimized by proper sizing techniques developed by Wang, Calhoun and Chandrakasan [3] and Alioto and Leblebici [18]. The effects of global variations on TEDsc are minimized due the STSCL design choice. As mentioned in Section 3.3, STSCL uses the VSC to maintain proper operation during the application of both static and dynamic global variations [17]. As mentioned in Section 2.2, larger local variations increase the size of t_a2 and t_edge2. This fundamentally limits the speed of the entire TED system since if (t_a2 + t_edge2)/T_CLK is too large, there is not ample time to detect errors.

To compare the benefits of TED, we designed a TED-enabled core (Core 1) and a non-TED core (Core 2). The designs of both cores were fabricated in 65 nm CMOS. The supply voltage range of both designs is from 300 mV to 500 mV, which is at the edge or below the strong inversion region for the process and all the digital cells. However, we optimized TEDsc to work deep into subthreshold; the analysis below will only include 300 mV and 400 mV operation points.

To simplify the design process of Core 1, two power domains were used in the design. The instruction memory and the error propagation path are located within one power domain, while the rest of the design is in a second power domain. The size of the instruction memory is 256 instructions and the size of the register file is 68 bytes. The area of the TED core (without instruction memory) is approximately 50,000 μm². The length of the CLK period is approximately 160 times the FO4 delay. The clock period is limited by the “Execute” stage and EDS design.

The foundries did not provide digital EDA tool library information for subthreshold operation. To acquire the library’s timing and power information for the EDA tools, we re-characterized the standard cells for subthreshold operation by using the Synopsys library characterization workflow. During the re-characterization process, we used the standard libraries as templates, considered all the timing arcs, and acquired the new timing and power information via analog simulation. The re-characterization process was repeated for the typical, best, and worst corners. The acquired library information was used by the EDA tools in the automated design flow. Due to their sensitivity variation in subthreshold, the smallest gates were removed from the libraries.

It was not possible to characterize the EDS element and include it to the digital library due to the asynchronous nature of the element’s error signal. Furthermore, the VSC block that generates bias voltages for the TEDsc blocks is inherently analog. Therefore, a digital simulation of the full system was not possible. An analog simulation of the system would have been excessively long. Thus, we performed a mixed-mode simulation on the system. The VCS and TEDsc blocks were simulated using Spice transistor level models. All of the digital blocks were simulated using the post-layout netlist (including parasitics). Mentor Graphics Questa ADMS was used to perform the mix-mode simulation.

The die microphotograph of Core 1 (TED) and Core 2 without instruction memory is shown in Figure 9. Both Cores include all the logic, delays, and buffers. The VSC block and the EDS circuits are also shown in Core 1 (TED).

Table 1 shows a comparison of Core 1 and Core 2. The area of Core 2 is approximately 18,000 µm², which is approximately 64% smaller than that of the TED version. For the comparison, the chip I/O compatibility level-shifters present in the subthreshold version are excluded, which gives the total area for the TED version as approximately 50,000 µm². The VSC block occupies an area of approximately 1750 µm² in the subthreshold design. It should be noted that in a larger design, the VSC area gets proportionally smaller. The areas of the different blocks were measured so that only the active area occupied by the blocks was taken into account.

The data in Table 1 shows that both the clock delay cells and the buffer cells occupy a substantially larger area than in the nominal voltage design. The number and the area of the logic ports are comparable. The area of the data storage elements is approximately two times larger in the subthreshold design, which can be explained by the fact that the EDS cells in general are larger in area than their conventional style counterparts. This applies especially to the EDS circuits designed for subthreshold operation due to their variation immunity requirements as explained in Section 3.3. The area in the table that is unaccounted for is occupied by the decap and antenna protection elements, and in Core 1 by the VSC block. It should be noted that the Core 1 (TED) design has not been optimized area-wise. Also, the I/O port functionality has been excluded from the Core 1 design. This makes the comparison somewhat less favorable for the Core 1 design in terms of the area. Also, the error recovery mechanism modification adds to the logic size slightly. The last columns of the table show the percentage of the area of the Core 1 design compared to the area of the nominal voltage design (Core 2).