In addition to continued reduction in transistor dimensions along the scaling, also the transistor configuration (or “transistor layout”), as used by standard cells become more and more complex. At this section, we will discuss some of the transistor leakage dependency to the layout “style”. Although the number of the different functions supported almost did not change during the years, the number of different cell types has increased in ~×1.2 at every technology node (Figure 4). The gate density is increased by factor of ×2 as required by basic scaling. More cell types and with more demanding design rules increase the challenge to reduce the leakage dependence on layout.

Another aspect for analysis of the complex topography, is the OPC (Optical-Proximity-Correction) implemented by the semiconductor foundry after the design is completed and prior to mask making. Basically, during OPC, small corrections are made to the design by attaching (or removing) small polygons. This OPC procedure takes place for the active area (AA), poly, all the metal layers and in the advanced platforms (≤90 nm), also for contacts and vias.

Figure 5 shows a snapshot from a standard cell library used in mass production, and the “on-silicon” shapes, based on modeling that takes into consideration the OPC and the manufacturing photolithography illumination conditions.

About 20 TDR (Topological Design Rules) are needed, for drawing the cells shown above. Among them, several rules have a direct relation with the transistor leakage, and therefore, should be optimized for low-power design. The analysis below covers some of these layout rules that are listed in Table 2.

GC.D.1 and transistor configuration: Several papers already discussed the effect of the distance between the poly (over STI) to related AA. If the poly is too close and rounded, it may affect the transistor gate length [12], and because of that, it is always recommended (if possible) to have larger distance. In terms of process and leakage interaction, the distance GC.D.1, also affects the exact corner location of the spacer/AA (Figure 6). In case the spacer corner is located too close to the AA/STI boundary, the damage to the silicon substrate during the spacer etch-back can cause junction leakage. The example below (Figure 6), shows the N+/WP junction leakage, as function of GC.D.1, using a dedicated test structure consisting of diffusion comb interdigitated with the poly over STI comb. As can be seen, if the distance is large enough, the leakage is low and almost similar to that of junction w/o poly-near-by. However, for a too short distance, the leakage and the leakage spread both increase. Figure 6 also shows the dependence of the leakage value on the number of diffusion corners. Naturally, the higher the number of corners, the higher the junction leakage (for the same value of GC.D.1). Therefore, for low-power design relaxing GC.D.1 and avoiding using complex transistors with a large amount of AA corners is recommended.

The transistor leakage also depends on the complex AA/Poly configuration. For analysis, a study methodology was developed [13,14] consisting of systematic Edge-Contour-Extraction (ECE) from transistors, taken along the manufacturing line. In general, the SEM (Scanning Electron Microscopy) ECE algorithm is based on CAD (GDS) to SEM pattern recognition, followed by initial and final 2D edge extraction. About ~3000 transistors were measured for the analysis. Device modeling (based on SPICE simulation) was then used, to predict the nominal values as well as the device performance variability of I_on and I_sub. The SEM analysis was done with measurement steps of 2 nm, so for every transistor gate, the min/max, average and standard deviation of the width and length were measured and calculated. I_on was calculated based on W_avg and L_avg—average width and length of every transistor, respectively. I_sub was calculated based on L_min, σ_L and W_avg were L_min and σ_L are the minimum gate length and the related standard deviation of every transistor. More details on this calculation method are given in [15]. The I_on/I_sub characteristic was used, in order to compare the performance of different transistor configurations. Generally, shorter gate length resulted in higher drive current and higher leakage current. The I_on/I_sub chart (Figure 7), gives the possibility to characterize configurations that yield lower leakage current for the same drive current. This is the main advantage of using the I_on/I_sub chart instead of looking on I_on or I_sub separately for variability analysis.

Analysis of the different clusters at the I_on/I_sub chart using Calibre DFM (Design-for-Manufacturing) property (Mentor Graphic) showed that each cluster is related to a different transistor configuration. The most frequent configurations (Figure 8) were configuration 4 (37%), configuration 1 (32%), configuration 8 (11%) and configuration 10 (8%). In the other 12% of transistors, 18 different configurations were defined.

Configuration 1 consists of a U-shape AA, with isolated poly gate. This configuration is known to have higher AA width variability [15,16]. The transistor under detection at configuration 4 does not have any AA or poly corners close the gate area, and can be referred to as “semi-dense” poly. Configuration 8 and 10, are very similar: both have poly bent at minimum design rule distance to the gate area, and the poly gate can be referred to as isolated. The only difference between these two configurations is the local area that is very similar but not identical. The electrical performances of each one of the configurations are shown in Figure 9. Configuration 4 shows the lowest I_sub, with about 20% lower leakage compared to configuration 8 or 10. This “better performances” can be attributed to the lack of AA and poly corners near the transistor gate, as well as to the semi-dense poly line. On the other hand, configurations 8 and 10 show the “worse performances” due to the isolated poly line, L_min was narrow and yield high leakage current. In addition, the poly bent and the related OPC, may affect the transistor width (as well as the transistor minimum length), as proposed at the SEM micrograph (Figure 8). It is clear from the I_on/I_sub chart, that these two configurations, had the highest (the worse) ratio and therefore, are less recommended to be used for low power or low leakage applications. Configuration 1, also shows bad I_on/I_sub ratio, correlated with the AA width spread as well as the isolated poly gate as can be clearly seen at the SEM micrograph (Figure 8).

Configurations 8 and 10 were also studied in [14]. A large array of standard cells was OPC treated followed by “silicon simulation”, to simulate the optical and etch manufacturing conditions. After the physical parameters were extracted from the “on-silicon” structures, device simulation was performed. Some correlation was found between the I_on and I_sub values and the ratio of J/L (Figure 10) where J is the length of the parallel poly to the AA and L is the length of the poly line. The parameters L and J determine how close the poly corners are to each other. Close corners will cause the OPC corrections to interfere with each other, causing channel length profile to undershoot in the jog side of the channel. This poly line-width undershoot increases I_sub because it is a function of L_min.

CS.D.1/2: Contacts too close to transistor gate, may have higher electrical field between the gate and the drain and as a result, may lead to higher I_sub (Figure 11). This is the reason that at some cases, CS.D.2 for thick oxide MOSFETs that use V_dd of 3.3 V and have larger electrical field between the contact and the gate, use larger distances compared to thin oxides (CS.D.1). In addition, contacts too close to the gate increase the overall gate capacitance, and degrade the transistor switching speed. Process improvement for this rule for leakage reduction result mostly from contact etches profile optimization and some selective OPC. A special test chip was proposed for monitoring CS.D.1 leakage levels [17].

Comparison among several vendors of standard cells using “ranking methodology” was presented in [18]. The ranking rule was based on fab manufacturing information data regarding the physical and electrical sensitivity of the structure to the design rule type and value. The overall design score was calculated using the ranking rule and its “weight”. Table 3 below (taken from [18]), shows the results for 4 different Std Cells libraries from 3 different vendors. Vendor C yielded the highest score for both GC.D.1 and CS.D.1. Vendor B2 received the lowest score for these two parameters.

High LER (Line-Edge-Roughness) and higher LWR (Line-Width-Roughness), also degrade the transistor leakage current. If we assume that the poly is composed of N segments in series, having a length l_i, so the overall I_sub of the transistor at V_gs close to 0 V will be [19]:

(3)

where l is constant. The first term at the summation will be L_min (the minimum gate length at the specific transistor). This segment will have much higher leakage than the other terms because of the exponential dependence. This can also explain the decision to use (L_min + σ_L) for the I_sub calculation [15]. The natural conclusion from this is that higher transistor variability means also higher power consumption. Kim et al. [20], found that for poly gates having widths of 80 nm~90 nm, increasing LWR from <7.1 nm to 14~21 nm, increased I_sub by 1.5~2 orders of magnitude.

LER is a strong function of the image conditions. At poly layer photolithography, the poly is “dark” and the poly space is “clear” or “bright”. In order to improve image fidelity and reduce variability, the transition from bright-to-dark needs to be steep. For reducing LWR, it is recommended to have a fixed (and optimal) space between poly the gates: to the near transistor or to dummy transistor. The size of this optimal space is set by the image conditions used by the technology—the wavelength, the numerical aperture, the illumination conditions as well as the photo-resist conditions like thickness and viscosity. Standard cells libraries used the minimum poly width of the technology for almost all gates. However, the position of the different transistors over the AA can not be fixed due to contact located in between for some cases. In addition, if the library supports multi-V_t, so the distance between different types of transistors should be maintained. This “fix space” is the base for using regular and gridded design with restrictive design rules (RDR) that introduced in 45 nm and below platforms.

Ban and Pan [21] proposed an algorithm for LER-aware poly optimization in order to minimize the leakage related LER, by setting an optimal space. The procedure placed poly gates at the best locations and introduced dummy poly to eliminate boundary conditions. As an example, 6 cells simulated with 32 nm technology conditions, showed leakage reduction by up to 47% (average 40%). In another work [22], Ban at al., presented a layout optimization based on comprehensive sensitivity metric which seamlessly incorporate proximity effects and process variations. Based on that information, standard cell layout optimization (poly gate and AA layout adjustments) is taking place, to minimize the delay at nominal and corner conditions. Using 45 nm Std Cell library, they demonstrated a leakage reduction of 7~91% at that corner.

Threshold voltage reduction is the simplest way to overdrive the transistors, and reduce propagation delay. However, V_t reduction means an exponential increase of I_sub. (Figure 12). By using a very high V_t values for non-critical paths, the leakage can be reduced by 2~3 orders of magnitude. Figure 13 shows the V_t scaling from 0.25 μm platform down to 65 nm for Standard (or regular) V_t. As can be seen, V_t values were no longer reduced beyond 90 nm. For Low Power, V_t higher by 100 mV~200 mV was used.

Basically, V_t change can be done by doping adjustments (of the channel and/or the SDE—Source-Drain-Extensions), adjustment of the gate oxide effective thickness and/or the work-function difference of the gate electrode (in the case of metal-gates) or by body biasing. In multiple-V_t, also known as “Multiple Threshold Voltage CMOS” (MTCMOS, or dual-V_t CMOS or DVTCMOS), two (or more) types of transistors are fabricated: Standard (SVt) or Regular-V_t and high-V_t (HVt). In most cases, this is done by an additional two V_t implant masks or two SDE implant masks. In high-density standard cells, this technique can be limited for “mixing” standard cell libraries, due to the layout design-rules related to the other layers. For SRAMs, the mask data preparation done by the foundry assign the relevant HVt implant masks also to the SRAM array. In case the design is without HVt, the dedicated VNS (Vt implant for nMOS SRAM) mask described above (or another VPS mask) are used. Another way to adjust the V_t is by the V_t roll-off behavior. However, modern CMOS devices use high doping levels of halo implants, in order to reduce the V_t roll-offs. In addition, in case a larger L is used, the gate capacitance will also be increased.

“Mixed” technology refers to the case of having simultaneously the Standard Logic transistors and the Low-Power transistors, having a different gate oxide thickness. In the example of the 65 nm platform described in Table 1, the two technologies can be used separately or “mixed” together [1,2]. These combinations have a triple-gate oxide and it is not manufacturing friendly due to an additional mask penalty, between +1 mask for the gate oxide process only, and up to +8 masks for the case V_t and SDE implants also need to be separated. In addition, the complexity of having an oxide-strip at a very small window, the additional thermal budget, and the fact that there are two different gates with a close thickness target are problematic due to the oxidation kinetics [25]. However, it was successfully developed for 28 nm technology, having gate oxides thickness of 16A for Low Power Standby (1.1 V) and 13.5 A for Low Power (0.8 V) [26]. In summary, this combination is one of the ways to reduce the overall circuit leakage, but it introduces many process challenges and has a high cost penalty.

It is known that the back bias (body bias, or reverse body biasing - RBB) can modify the transistor V_t. However, higher body bias increases GIDL, degrades V_t variability, and in multi-V_t transistors induces different body-biasing sensitivity that depends on V_t [1]. In this case, closely located transistors can not share the same N or P wells and because of that, triple wells are needed. Such wells have high area penalty due to additional layout design rules. It is important to note that, while the reverse bias increases V_t, it also increases the junction current and decreases the junction capacitance. In [27], a novel technique to minimize the standby leakage was proposed. In order to overcome the performance’s degradation using RBB due to increase in GIDL, DIBL and BTBT currents, H-J Jeon at al. [27], proposed a standby leakage power reduction technique, based on optimal body bias voltage. This voltage was determined by the ratio of I_sub and the band-to-band tunneling current (I_BTBT). For circuit implementation, they proposed a control system that includes monitoring circuit, current comparator and charge pump. The leakage monitoring circuit input both I_sub and I_BTBT into the current comparator that increase or decrease the body voltage applied to the chip core by the charge pump. Implementation of this technique to 32 nm MOSFET technology ISCAS85 benchmark circuits yield 400~1500× leakage reduction. Yasuda et al. [28] succeeded in reducing the sensitivity of the body-biasing to threshold voltage by careful channel and gate engineering—they increased the channel contour doping (by adjustment of the punch through implant dose and energy) and shifted the channel from the surface (buried channel). Taking advantage of the V_t shift by the work-function modulation of the Hf-based gate dielectric, the peak concentration of the channel impurity profile was positioned in a deeper channel region, away from the surface, and without lowering the V_t.

The main drawback of reducing the leakage by increasing the channel doping for V_t, is the reduction in the transistors currents due to a lower overdrive, which leads to degradation in delay time, that for an inverter is given by:

(4)

where ν is a fitting constant (that is correlated to the velocity saturation index), μ, ε_ox, W_eff and L_eff are the channel mobility, the gate oxide dielectric constant, the effective width and length of the transistors, respectively.

The 90 nm technology was the first node in which performance enhancement was done using stressors [29]. These stressors can be STI [30], Stress Memorization layers [31], nitride located under D1 that was also used as Contact Etch-Stop Layer (cSEL) [32] and eSiGe (elevated SiGe) [33]. Stress induced by the salicided Source-Drain active area can also improve performance [34]. Basically, stress induced into the channel can improve or degraded the carrier’s mobility, and as a result change the transistors currents. The level of improvement (or degradation) depends on the level of the stress induced, the type (tensile or compressive) as well as on the direction of the strain induced into the silicon. For example, compressive stress induced by STI along the x-axis (along the channel length), will improve the drive current for pMOS transistors. However, the compressive stress at the y-axis (along the channel width) will degrade the drive current for the same pMOS transistor, and because of that, higher tensile stress resulting from AA salicidation at the y-axis will improve the current. In the work reported in [35], all stress techniques listed above were used in a 90 nm platform. The overall currents improvement was up to 15%. It consisted of improvement due to cSEL (~7%), from STI (~7%) and from salicidation (~5%). Naturally, the improvement of all stress components is not “cumulative”.

The main advantage of the different mobility enhancement techniques is the increase in drive current without leakage degradation (Figure 14). Based on that, by a careful layout modification, the leakage current can be improved by keeping other parameters in place. As a basic example, assume a transistor with a specific gate length that yields drive current and leakage based on the I_on/I_sub charts. Increase of the gate length, will reduce the leakage and the drive current. However, by using stressors, we can re-set the drive current back to place, while still having this low leakage levels. In the example of Figure 14, the leakage for the nMOS can be reduced by ~60% while keeping the same drive current. In addition to this example, the I_sub reduction is observed to taper off quickly with longer gate length. It is important to note, that stress can also increase the leakages related to junctions. Wang et al. [36] studied the effect of mechanical uni-axial stress on junctions fabricated in 65 nm technology. They found, that for junction in nMOS, where the BTBT is the major component of the junction leakage, the dependence on stress (generated by tensile cSEL) is weak, and even using high-stress layers (thicker, as for 45 nm technology), the junction leakage degradation was <7%. For nMOS, higher tensile stress reduced the leakage. However, for junction in the pMOS, where the stress was generated by both compressive cSEL and eSiGe elevated S/D, due to the fact that the leakage mechanism was based on both BTBT and generation current, high stress would degrade the leakage by up to 25%. These facts should be taken into consideration for future technologies. Examples for stress affecting layout modification are:

The first research work to tackle timing closure for standard cell by layout modifications using active area depended mobility of strained silicon was made by [38]. In there work, GC.S.1 was adjusted, to modify the stress induced by eSiGe stressor. Later, Joshi et al. [39], developed a methodology for stress-aware layout optimization, with a constraint that the cell area will not change, have similar switching delays or less, and lower leakage. Because dual-V_t (HVt, LVt) was available, the algorithm also “assigned” the optimal V_t type per case, together with the layout optimization. This approach was used successfully for the 65 nm technology design having the following parameters: V_dd = 1 V, nMOS_HVt = 334 mV, pMOS_HVt = −391 mV, nMOS_LVt = 243 mV, pMOS_LVt = −280 mV. The I_on and I_sub ratio for LVt/HVt was ×1.24/×16 for the nMOS and ×1.32/×29 for the pMOS. The stress-aware layout modification included changes in GC.X.1, CS.D.1 and CS pitch, and setting of the location of tensile/compressive nitride cSEL layer located over STI (Figure 17). Comparison was also made between using dual-V_t with single thin-oxide thickness only, and using dual-V_t with stress-aware layout modification. Analysis showed that for the same delay time, up to 34% reduction of leakage was obtained. For the same leakage values, up 10% delay time reduction was achieved using this methodology.

The results of Table 4 [39] clearly show, that the combined approach improved significantly the leakage power while keeping the same delay time. Improvement in critical delay time for iso-leakage was also seen while comparing to dual-V_t only approach. Maximum leakage improvement was 38.5% and with average value of 23.8%.