^{*}

This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution license (http://creativecommons.org/licenses/by/3.0/).

Energy consumption is one of the main barriers to current high-performance designs. Moreover, the increased variability experienced in advanced process technologies implies further timing yield concerns and therefore intensifies this obstacle. Thus, proper techniques to achieve robust designs are a critical requirement for integrated circuit success. In this paper, the influence of intra-die random process variations is analyzed considering the particular case of the design of energy aware adder circuits. Five well known adder circuits were designed exploiting an industrial 45 nm static complementary metal-oxide semiconductor (CMOS) standard cell library. The designed adders were comparatively evaluated under different energy constraints. As a main result, the performed analysis demonstrates that, for a given energy budget, simpler circuits (which are conventionally identified as low-energy slow architectures) operating at higher power supply voltages can achieve a timing yield significantly better than more complex faster adders when used in low-power design with supply voltages lower than nominal.

The rapid scaling of silicon technology has enabled designers to integrate millions and even billions of transistors into a single chip. This ability, to achieve very high integration density, has contributed to the success of integrated circuit (IC) design during the past few decades. Unfortunately, technology scaling is leading to a significant increase in process variability due to random doping effects, imperfections in lithographic patterning of small devices, and related effects [

PVs can be compensated by using appropriate circuit techniques like Adaptive Body Bias (ABB) and Adaptive Supply Voltage (ASV) [_{max}) and maximum power consumption (P_{max}), and thus, to improve the parametric yield.

Another well known method for performing PV compensation is the ASV approach which consists in opportunely tuning the power supply voltage (VDD). This technique was originally proposed to trade performance with power [

Whereas the above mentioned design methodologies are effective for compensating inter-die PVs they are less useful to mitigate intra-die PVs, since it is not physically possible to measure the variations for each single transistor on the chip and generate and apply the appropriate body/VDD source voltage to it.

The most well-known technique for reducing device-to-device (

In this paper, the influence of intra-die random PVs is analyzed considering the particular case of the adder circuits, which are a very important class of digital circuits since they are frequently used in the critical path of the control unit and the data-path of microprocessors and digital signal processors (DSPs) [

As a first step of our analysis, the speed uncertainty due to PVs is evaluated for different power supply voltages. It is shown that the impact of intra-die PVs on delay strongly depend on the considered VDD. Moreover the delay sensitivity worsens at the lower supply voltages. This information is particular important, especially for low power applications where the supply voltage may be reasonably low. In fact, if the delay variation becomes too large, timing yield fallout may occur. As a subsequent step of this work, the sensitivity to process variations was comparatively analyzed for low-energy slow and high-energy fast adder architectures. As a fundamental result, our study demonstrates that, for an equal energy budget, low-complexity circuits operating at higher VDDs can be significantly faster and less delay sensitive to random PVs than high-complexity adders operating at lower power supply voltages. This suggests some criteria for opportunely choosing optimum VDD and logic architecture to design energy aware high yield adders. We believe that this result can be very useful as it provides effective suggestions to manage intra-die process variability impact on Deep-Submicron (DSM) multi-VDD digital systems.

This paper is organized as follows: in Section 2, the analyzed adder topologies are briefly reviewed and their main characteristics are discussed; Section 3 deals with the impact of intra-die process variability on the analyzed adders; timing yield issues and important design guidelines for energy-aware adder circuits are discussed in Section 4; finally, conclusions are drawn in Section 5.

Addition of binary numbers is implemented in a bitwise approach. At each bit position, the sum value can be determined based upon the corresponding bit values of the operands and the incoming carry value from the previous position. Since, in the worst case, the incoming carry value should be propagated from the least significant bit position to the most significant, the delay of an addition operation is dependent on the operand word length (

Five 16-bit adder architectures have been considered as the case study in this work. They were synthesized by Synopsys Module Compiler (MC) [

The fast carry look-ahead (_{2} _{2}

When a digital circuit is designed using the semi-custom standard cells based approach, the available degrees of freedom for a designer to satisfy given energy consumption and performance specs are essentially represented by logic architecture and supply voltage choosing. Among these, tuning the VDD value is a straightforward technique to meet the given delay (energy) constraint. In fact, by increasing the power supply voltage, the device drive currents are improved thus leading to better circuit performances, but this also degrades both dynamic and leakage power which are quadratically and exponentially dependent on VDD, respectively. Conversely, by reducing the power supply voltage, dynamic and leakage power are improved but the performance is degraded.

In order to characterize the sensitivity of the considered adder architectures to different VDDs, the circuits were simulated in the Cadence environment for VDD ranging from 0.8 V up to 1.2 V. Simulations were performed placing input buffers between ideal voltage sources and operand inputs to provide realistic input signals. Moreover, each output signal was loaded with a 0.8 fF capacitance (which corresponds to the input capacitance of a D-type Flip-Flop in the referred technology). This choice allows realistic running conditions to be examined.

The energy dissipation evaluated under different supply voltages is plotted in _{op}), evaluated over 200 input patterns. The latter were randomly provided at a running frequency of 166 MHz. From

For the sake of completeness, the leakage current evaluated in the considered VDD range is plotted in

The analyzed adder topologies can be thoroughly and fairly compared by combining results of

As highlighted in

The performed analysis suggests that considering power supply voltage as a tuning parameter, different architecture choices can be performed on the basis of the available energy budget. In the following, we analyze how the possible choices are impacted by random intra-die PVs.

The impact of intra-die PVs was evaluated through Monte Carlo simulations performed on 1000 samples. In this case, driving circuits of the simulation setup are not influenced by random process variations in order to isolate process variability effects on circuits under test.

The ratio between the maximum spread 3σ and the mean value μ (

The 3-sigma delay value (defined as μ + 3σ) was evaluated for different VDD and is plotted in

It is worth noting that the 3-sigma delay value provides very practical information to evaluate the achievable post fabrication timing yield. In fact, considering the 3-sigma delay value as a timing constraint, it is statistically assured that about 99.87% of the fabricated circuits satisfy the target speed [

Results shown in

The previous discussed analysis provides important suggestions to design robust circuits under energy constraints. This is highlighted in the next section.

Under process variations, the delay of a given circuit can be modeled by a normal distribution with a probability density function (PDF) characterized by the mean and the standard deviation values [

The delay distributions for the

The above discussed results clearly demonstrate that, for a given energy constraint, properly power supplied low-complexity adder architectures can achieve better timing characteristics and reduced delay sensitivity to random PVs with respect to complex adders operating at lower power supply voltages.

In this paper, the influence of intra-die random PVs was analyzed considering five well known adder circuits, designed exploiting the ST 45 nm static CMOS standard cells library. As a first step of our analysis, the speed uncertainty due to PVs was evaluated for different power supply voltages. It was shown that the impact of intra-die PVs on timing yield strongly depends on the considered logic architecture and chosen power supply voltage. For a given VDD, slower adder circuits present reduced delay variability due to the averaging effect of longer critical paths. In the second part of this work, the sensitivity to process variations was comparatively analyzed for low-energy slow and high-energy fast adder architectures. As the main result it was demonstrated that, for an equal energy budget, low-complexity circuits, operating at higher VDDs can be significantly faster and less delay sensitive to random PVs than high-complexity adders, operating at lower power supply voltages. This suggests some criteria for opportunely choosing optimum VDD and logic architecture to design energy aware high yield adders: for a given energy constraint it is preferable to use lower complexity adders power supplied at an appropriately high VDD.

Delay characteristics.

Energy characteristics.

Leakage current.

Energy-Delay characteristics.

Energy-Delay characteristics in the 350–800 fJ energy range.

Delay variability.

3σ Delay characteristics.

Energy-3σ Delay characteristics.

Energy-3σ Delay characteristics in the 350–800 fJ energy range.

Energy-3s Delay characteristics in the 550–1650 fJ energy range.

Delay Probability Density Function (PDF) for _{op} = 500 fJ.

Delay Probability Density Function (PDF) for _{op} = 1000 fJ.

Delay Probability Density Function (PDF) for _{op} = 1500 fJ.

Asymptotic time and area requirements of

ripple carry adder | O( |
O( | |

fast carry look-ahead adder | O(_{2} |
O(log_{2} | |

carry look-ahead adder | O( |
O(log_{2} | |

carry select adder | O( |
O(√ | |

carry look-ahead/select adder | Variable |
Variable |