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In this paper, we present a hardware friendly binary decision tree (DT) classifier for gas identification. The DT classifier is based on an axis-parallel decision tree implemented as threshold networks—one layer of threshold logic units (TLUs) followed by a programmable binary tree implemented using combinational logic circuits. The proposed DT classifier circuit removes the need for multiplication operation enabling up to 80% savings in terms of silicon area and power compared to oblique based-DT while achieving 91.36% classification accuracy without throughput degradation. The circuit was designed in 0.18

The last decade has witnessed an increasing interest in gas identification based on gas sensor arrays and pattern analysis for machine olfaction applications [

The paper is organized as follows. Section 2 introduces binary decision tree classifiers and examines prior hardware implementations. Section 3 describes the proposed axis-parallel DT architecture and silicon implementation. Experimental results and performance evaluation are discussed in Section 4. Finally, a conclusion is given in Section 5.

Decision tree is a classification model where the target function is represented by a sequence of queries based on the attributes of input test patterns. The sequence of queries is reflected in a tree structure with finite depth. The classification of a particular pattern begins at the root decision node and terminates in the leaf node where a single class label is specified as the classification result. Each decision node contains different tests involving one or more attributes of the test patterns. Depending on the output of the decision node, only one branch of the decision node is selected and the child (descendent) node is visited. This process is repeated until a leaf is reached.

_{1}, _{2}, _{3},…,_{n}_{i}_{i}_{i}_{i}_{i}_{n}_{+1} is the threshold value of the function

While quadratic polynomial nonlinear DTs correspond to the function
_{i}_{j}

_{1} and _{2} of test patterns. The decision boundaries of different decision tree methods have their own properties. For axis-parallel DTs, partition lines are parallel with the attribute axes. For oblique DTs, partition lines are oblique straight lines and the decision boundaries are curves for nonlinear DTs.

The three aforementioned DT classifiers are actually intimately related. For example, _{i}_{j}

Nonlinear DTs are more complex than the other two types of DTs. Oblique DTs are normally much smaller than axis-parallel DTs due to their flexibility at each decision node. However, finding the best oblique DT is an NP-complete problem [

A second approach [

In this paper, we propose to explore axis-parallel DT based classifiers, to remove the need for multiplication operations and enable a low cost compact implementation with a classification accuracy comparable to prior works [

The proposed DT classifier illustrated in

There are 9 processing elements in the TLU layer and 3 programmable logic blocks using the tree structure. Each processing element is here a pipelined digital comparator (subtracter). Each programmable logic is configured for a given gas identification task. To minimize the area cost and avoid input and output port limitation, we chose a bit-serial architecture to process elements. The digital weight precision is important for classification performance. Research works in [

For an oblique DT architecture, each node requires to realize the function given by _{n}_{+1} to make the decision on the node. With the increase of the number of attributes

In the proposed axis-parallel DT architecture (

However due to the same classification problem, the built tree's node number and tree's depth are typically much larger than that of the oblique DT structure.

In prior works [

As shown in

The comparator used in our proposed circuit is illustrated in _{s}_{1} and _{s}_{2} are included to avoid hysteresis or delayed response in the resetting phase. The operational principle is as follows. When the clock is high, the comparator is operated in the resetting mode and both outputs (_{b}

_{2}

Principal component analysis (PCA) is often used to pre-process the initial data and decrease the dimensions of the feature vector [_{1} and _{2}. In this section, we compare the performance of the proposed binary decision tree classifier with and without PCA pre-processing. 12 gas sensors are selected to build the sensor test vector. The dimensions of test vectors are reduced to 2, 3 and 4 by using PCA program implemented in MATLAB. Both original and PCA pre-processed data were fed into the OC1 software tool to build the axis-parallel decision tree and the oblique decision tree for gas classification.

According to our simulation results, both decision tree based classifiers benefit from the PCA algorithm. In particular, oblique decision tree hardware complexity can be significantly decreased by reducing the number of attributes in the test vector by using the PCA. However, PCA requires more hardware resources such as matrix multiplications. For example, if we want to select

The proposed classifier was designed using Charter 0.18

In this paper, a low-power single-chip binary decision tree based classifier is proposed for gas identification applications. The classifier circuit uses an axis-parallel architecture to remove the need for multiplication operations and enables a low cost compact implementation with a classification accuracy comparable to prior art. Without PCA pre-processing, the proposed classifier can still achieve 91.36% classification accuracy without throughput degradation while saving up to 80% silicon area and power consumption. The performance of the circuit can easily be enhanced by using Boosting or Bagging techniques [

(

Reported DT hardware implementations with: (

Two layer neural network architecture to implement the axis-parallel DT classifier. The first layer is the TLU layer to implement the decision node function. The second layer is the PLU layer to implement the logic function for each class.

The processing element of the axis-parallel decision tree. The processing element includes 10-bit register to store the coefficients, 3 1-bit registers for pipelining, one 1-bit adder with an invertor for the substraction operation and one tri-state buffer for controlling the output data. _{in}_{out}

Overview of the proposed tree-based programmable logic circuit.

The stacked transistor tree circuit. The FF line represents a line of registers to control the _{0}, _{1}, _{2}, _{3} values and determine the differential outputs (

The dynamic comparator circuit with no static current consumption. Two operation phases: (i) the reset phase; (ii) the comparison phase.

Timing diagram of the proposed programmable circuit with the four control signals

Experiment setup for gas identification.

Example of response of the gas sensor array.

PCA pre-processing of the gas sensor array multivariate response.

Layout of the classifier and interface circuits. Note that the PLUs are full-custom designs whereas the TLUs are designed using standard cells.

Hardware cost and classification accuracy comparison for 3 gases (_{2} and

2 | axis-parallel | 88.33% | 13 | 12 | 0 | 12 | 12 |

2 | oblique | 89.24% | 9 | 8 | 16 | 16 | 24 |

| |||||||

3 | axis-parallel | 92.73% | 10 | 9 | 0 | 9 | 9 |

3 | oblique | 90.30% | 5 | 4 | 12 | 12 | 16 |

| |||||||

4 | axis-parallel | 99.55% | 7 | 6 | 0 | 6 | 6 |

4 | oblique | 94.55% | 3 | 2 | 8 | 8 | 10 |

| |||||||

no PCA | axis-parallel | 91.36% | 10 | 9 | |||

no PCA | oblique | 92.58% | 6 | 5 | 60 | 60 | 65 |

Performance of Front-end TLU blocks using Design Compiler(DC).

^{3} ^{2}) | ||||||
---|---|---|---|---|---|---|

Reference [ |
oblique | 0.18 |
5 | 1.61 | 25 | 100 |

This work | axis-parallel | 0.18 |
5 |

Gas classification performance comparison.

Sensor type | 2×2_{2} array |
2×2_{2} array |
4×4_{2} array |
4 × 4_{2} array |

| ||||

Target gas species | _{4},_{2},_{4},_{2} |
_{4},_{2},_{4},_{2} |
_{2} |
_{2} |

| ||||

Detection rate | 92% | 94% | 92.58% | 91.36% |

| ||||

FPGA Implementation | ||||

No. of Slice FF | N/A | 12146 | 1176 | |

No. of 4-LUT | N/A | 20115 | 1269 | |

| ||||

ASIC Implementation | ||||

process | 0.25 |
N/A | 0.18 |
0.18 |

Area | 1.69 ^{2} |
N/A | 0.1 ^{2} |
^{2} |

Power | N/A | 500 |
25 |

This work was supported by a Research Grant from Hong Kong University of Science and Technology (Research Project Competition grant reference: RPC 10EG20).