Gate Tunable Transport in Graphene/MoS₂/(Cr/Au) Vertical Field-Effect Transistors

Abstract

Two-dimensional materials based vertical field-effect transistors have been widely studied due to their useful applications in industry. In the present study, we fabricate graphene/MoS₂/(Cr/Au) vertical transistor based on the mechanical exfoliation and dry transfer method. Since the bottom electrode was made of monolayer graphene (Gr), the electrical transport in our Gr/MoS₂/(Cr/Au) vertical transistors can be significantly modified by using back-gate voltage. Schottky barrier height at the interface between Gr and MoS₂ can be modified by back-gate voltage and the current bias. Vertical resistance (R_vert) of a Gr/MoS₂/(Cr/Au) transistor is compared with planar resistance (R_planar) of a conventional lateral MoS₂ field-effect transistor. We have also studied electrical properties for various thicknesses of MoS₂ channels in both vertical and lateral transistors. As the thickness of MoS₂ increases, R_vert increases, but R_planar decreases. The increase of R_vert in the thicker MoS₂ film is attributed to the interlayer resistance in the vertical direction. However, R_planar shows a lower value for a thicker MoS₂ film because of an excess of charge carriers available in upper layers connected directly to source/drain contacts that limits the conduction through layers closed to source/drain electrodes. Hence, interlayer resistance associated with these layers contributes to planer resistance in contrast to vertical devices in which all layers contribute interlayer resistance.

1. Introduction

Heterostructures [1,2,3] composed of graphene and other two-dimensional (2D) crystals, such as transition metal dichalcogenides (TMDs), are of a great interest due to their fundamental and applied aspects. Extensive research has been carried out in both lateral [4,5,6] and vertical [3,7,8,9,10,11] hetero-stacks of graphene with other two-dimensional materials. The vertical devices of two-dimensional materials open particularly promising new horizons in material research. For example, graphene vertical field-effect transistors (G-VFETs) are charming candidates for future research, as they have ultimately thin bodies of a few atomic layers, which provide ultrafast transport nearly in a few femtoseconds [12] and higher switching (on/off) ratio as compared to their lateral counterparts.

Thus far, several vertical heterostructures of graphene with other 2D materials have been proposed. For example, Britnell et al. introduced a VFET heterostructure [13] composed of two graphene electrodes and a thin hexagonal boron nitride (h-BN) layer sandwiched between them showing the on/off ratio ~50. When h-BN was replaced by MoS₂, on/off ratio was enhanced to ~10⁴ due to the low bandgap of MoS₂ as compared to h-BN. It was reported that tunneling transport was dominant in off-state, whereas thermionic transport played a major role in on-state in other previous studies on Gr/TMDs/Gr vertical devices [3]. Another configuration of VFETs has been investigated in which one side of TMDs was contacted with a graphene electrode, while the other was contacted with a metal electrode [7,14,15,16,17,18,19,20,21]. In this kind of devices (Gr/TMDs/Metal), Schottky barriers at the interface between graphene and TMDs play an important role in the electrical transport. Electric field from the back-gate can modify the Schottky barrier height. These devices are superior to tunneling devices due to a large current density through the semiconducting TMDs channel [22,23,24]. Gr/TMDs/Metal devices showed a high on/off ratio and low driving voltage; therefore, they are good to use in low power consumption applications.

In previous reports, most VFETs were studied by employing the two-probe measurement configuration, which included contact electrodes as a part of the devices. This configuration always possesses contact resistance due to which intrinsic characteristics of the device were impossible to achieve. In the present paper, we have fabricated Gr/MoS₂/(Cr/Au) VFET with various MoS₂ thickness. However, we use four-probe cross-bar geometry in this experiment to exclude contribution of electrode to the measurement. Monolayer Gr used as a bottom electrode allows back-gate electric field to tune the energy states of MoS₂ in VFET. Therefore, we could investigate the gate-dependent electrical transport in our MoS₂ VFET. Moreover, graphene contacts [25,26,27,28] can effectively decrease contact resistance because of small work function mismatch between graphene and MoS₂. We have also measured planar transport properties of lateral MoS₂ field-effect transistors for comparison. Electronic transports in the vertical and lateral direction were discussed by analyzing the resistance components.

2. Experimental Section

2.1. Device Fabrication

Our Gr/MoS₂/(Cr/Au) VFETs were fabricated on SiO₂/P⁺-Si substrate. The thickness of dielectric (SiO₂) was 300 nm, whereas P⁺-Si was used to apply back-gate voltage. In the first process, chemical vapor deposition (CVD) grown graphene was transferred on SiO₂/Si substrate using wet transfer method [29], and a graphene Hall bar pattern was defined by using photo-lithography. Then oxygen plasma (power ~50 W) was used for several minutes to etch extraneous graphene. The Raman spectrum for Gr is shown in Supplementary Materials Figure S1 (see Supplementary Materials). In Raman spectrum, 2D to G peak intensity ratio is larger than 3:1, indicating monolayer characteristics of Gr [30]. We used the scotch-tape method for mechanical exfoliation of MoS₂ [17,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45]. The suitable MoS₂ flake was selected under an optical microscope and then transferred on graphene Hall bar by using micromanipulator. Subsequently, 15-nm-thick HfO₂ films was grown by atomic layer deposition on the e-beam lithography defined area. In the last process, e-beam lithography was done to define the top electrode of Cr/Au (8/120 nm).

2.2. Measurements

Electrical measurements were performed by using Keithley 2400 source meter, Keithley 6485K picoammeter, and Keithley 2182A nanovoltmeter. All measurements were performed in vacuum at room temperature. Structural investigation and material identification were performed using Raman spectroscopy and atomic force microscopy (AFM). In Raman spectroscopy, laser wavelength of 514 nm with power below 1 mW was selected to avoid structural degradation caused by the heating effects of the laser. The nominal diameter of laser spot was 0.7 µm.

3. Results and Discussion

3.1. Gr/MoS₂/(Cr/Au) Vertical Field-Effect Transistor

A schematic representation of Gr/MoS₂/(Cr/Au) VFET is shown in Figure 1a, where the back-gate voltage is applied to control the vertical transport in MoS₂ channel. The optical micrograph of device is shown in Figure 1b. Graphene is represented by the purple color, MoS₂ by the sky blue, and HfO₂ (~15 nm thick) window by the dark blue color. We choose CVD-grown monolayer graphene despite multilayer graphene. We believe that, in case of multilayer graphene, the gate effect would be small as compared to monolayer graphene due to back-gate electric field screening, and modulation in Schottky barrier height will be more difficult as compared to monolayer graphene.

The alphabetic and numeric symbols indicate different contacts used for the planar and vertical transport measurement. Figure 1c shows AFM of MoS₂ film, which reveals uniform surface morphology. Height profile taken by AFM shows the thickness of MoS₂ to be ~44 nm in Figure 1d.

Raman spectroscopy of MoS₂ on monolayer Gr was studied in comparison with MoS₂ on Si/SiO₂ substrate shown in Supplementary Materials Figure S2. Raman spectrum for MoS₂ on Si/SiO₂ substrate was represented by the black color, whereas the red color shows Raman spectrum of MoS₂ on Gr. Two prominent peaks of MoS₂ appeared in the wavenumber range from 380 to 420 cm⁻¹. These two Raman peaks belongs to in-plane (${\mathrm{E}}_{2\mathrm{g}}^1$) and out of plane (A_1g) vibrations of “Mo” and “S” atoms [46]. The difference between ${\mathrm{E}}_{2\mathrm{g}}^1$ and A_1g Raman peaks for MoS₂ on Si/SiO₂ substrate amounted to Δ ≈ 24 cm⁻¹, indicating a multilayer nature [22]. There was a slight change in peak positions of MoS₂ when stacked on Gr. This slight change was due to the relaxation of atoms on different substrate.

We assume that vertical resistance (R_vert) is a cumulative effect of all the resistances including contact resistance and MoS₂ channel resistance. We made a cross-junction geometry to investigate the vertical transport in Gr/MoS₂/(Cr/Au). The measurements consisted of four-probe technique where two contacts were used as source and drain, while the other two for voltage measurement across VFET. Figure 1b shows the measurement configuration (I⁺, I⁻, V⁺, V⁻) for the vertical resistance R_vert. We also measured planar resistance R_planar of the same MoS₂ film using Cr/Au contacts as illustrated by numeric symbols 1, 2, 3, 4 in Figure 1b.

3.2. Vertical Resistance of Gr/MoS₂/(Cr/Au) VFET

Figure 2a shows a schematic diagram of Gr/MoS₂/(Cr/Au) VFET, where R_int and R_c represent interlayer resistance between stacked layer of MoS₂ and contact resistance, respectively. Figure 2b represents vertical resistance (R_vert) of Gr/MoS₂/(Cr/Au) VFET as a function of the back-gate voltage (V_bg). In this experiment, the current flows from Gr to the top Cr/Au contact through semiconducting MoS₂ channel. The electrical characteristics are strongly modified by V_bg. To understand the physics of the transport mechanism, there are lot of factors that should be keep in mind e.g., Schottky barrier height, barrier width etc. It is a well-known concept that electrical transport in TMD’s based field effect transistors (FET) is governed by either tunneling or thermionic emission. Tunneling is due to passing of carriers through barrier height and is a temperature-independent quantity. However, thermionic emission is highly reliant on temperature. Tunneling current depends upon barrier width, and if the barrier width is too large, we cannot observe tunneling current. Here, our average MoS₂ thickness is 50 nm (barrier width ~50 nm). Usually, to observe tunneling mechanism, the barrier width should be ≤5 nm [47]. So, we can firmly say that in our experiment, electrical transport is not caused by tunneling. However, the low value of current observed at V_bg < 0 in our Gr/MoS₂ heterostructure’s transport property (shown in Supplementary Materials Figure S3c) is due to gate leakage current and not by the tunneling that is a very well-known phenomenon in Si-based field effect transistors. The Gr/MoS₂ junction is completely in off state at low V_bg due to the presence of large Schottky barrier height (SBH), which is why we observed large resistance at that point.

On the other hand, Deshun Qu et al. reported that “S” vacancies in MoS₂ play an important role in r_int [48]. The importance of “S” atoms was further elaborated for the vertical carrier transport by orbital overlapping between “S” atoms in adjacent layers [49,50].

3.3. Resistance Analysis of Gr/MoS₂/(Cr/Au) VFET

R_vert in the measurement configuration of Figure 2a can be considered as the sum of interface resistance between Gr and MoS₂ (${\mathrm{R}}_{\mathrm{Gr}/{\mathrm{MoS}}_2}$), total channel resistance of individual layers of MoS₂ (R_TCR-V), interlayer resistance (R_int) of MoS₂, and interface resistance (R_SBH) between Cr/Au electrode and MoS₂. So, the vertical resistance (R_vert) is given by Equation (1).

R_vert = R_TCR-V + R_int + R_GR/MoS2 + R_SBH

(1)

where total interlayer resistance (R_int) is given by ${\mathrm{R}}_{\mathrm{int}}{=\mathrm{Nr}}_{\mathrm{int}}$, where N is the total number of layers in MoS₂ and r_int is the interlayer resistance between two consecutive layers of MoS₂. As the thickness of MoS₂ increases, R_int increases, and then R_vert increases as well. In the vertical transport, r_int is a non-negligible quantity in the thick MoS₂ channel. Another important factor that should be elaborated here is the channel resistance itself. In the vertical transport, R_TCR-V increases with an increase of the thickness of MoS₂ channel. Since both R_int and R_TCR-V increase with increasing MoS₂ thickness, R_vert shows the dependence of MoS₂ thickness. However, the resistance of planar or vertical device depends on cross-sectional area, so it is better to examine resistivity instead of resistance. Figure 2d shows ${\mathsf{\rho }}_{\mathrm{planar}}$ and ${\mathsf{\rho }}_{\mathrm{vert}}$ as a function of MoS₂ thickness.

As another important component of R_vert, we discuss ${\mathrm{R}}_{\mathrm{Gr}/{\mathrm{MoS}}_2}$ which is the interface resistance between Gr and MoS₂. We analyze ${\mathrm{R}}_{\mathrm{Gr}/{\mathrm{MoS}}_2}$ within 2D thermionic emission theory, where the Schottky barrier height is given by Equation (2).

$${\mathsf{\Phi }}_{\mathrm{B}}=\frac{{\mathrm{k}}_{\mathrm{B}}\mathrm{T}}{\mathrm{e}}\ln (\frac{{\mathrm{A}}^{*}{\mathrm{T}}^2}{{\mathrm{J}}_{\mathrm{rev}}})$$

(2)

where ${\mathrm{k}}_{\mathrm{B}}$ is the Boltzmann’s constant, A* is effective Richardson constant and we choose A* = 54 Acm⁻² K⁻² for MoS₂ [51]. We extracted Schottky barrier height at T = 300 K from I_ds-V_ds curves shown in Supplementary Materials Figure S3. J_rev (=I_ds/A_junc) is the reverse saturation current density at V_ds = −0.5 V, where we see a beginning of saturation of I_ds. A_junc (=200 μm²) is the junction area of Gr/MoS₂. Barrier height decreases with an increase of V_ds or V_bg (see Figure 3a,b). ${\mathsf{\Phi }}_{\mathrm{B}}$ ranges from 1.10 to 0.78 eV for the interface between monolayer Gr and 53-nm-thick ML-MoS₂.

Moreover, planar resistance (R_planar) of the MoS₂ channel was measured by using the electrodes labelled as numeric letters in Figure 1b. While current was applied between 1 and 2, voltage was measured between 3 and 4. Figure 2c shows R_planar as a function of V_bg. As V_bg increases from −30 to 40 V, R_planar rapidly decreases, indicating MoS₂ is a n-type semiconductor. The MoS₂ channel thickness dependence of R_planar at V_bg = −10 V is shown in Figure 2d. As MoS₂ flake thickness increases, R_planar decreases in contrast to R_vert. We can analyze R_planar as R_TCR-P in 4-probe measurement configuration. Here, R_TCR-P represents the in-plane resistance of MoS₂. As the thickness of MoS₂ channel increases, more layers can contribute to the planar electrical transport, so that total planer channel resistance, R_TCR-P decreases. To have an estimate of contact resistivity, we employed transmission line method (TLM) on 51 nm-thick MoS₂ flake and extracted contact resistivity to be 0.14 MΩ μm at V_bg = −10 V as shown in Supplementary Materials Figure S4b. The contact resistivity is smaller than the planar resistivity of MoS₂ channel itself. So, it is obvious that there are other factors contributing to the total in-plane resistance other than contacts. The back-gate voltage-dependent contact resistivity was also estimated using TLM method as shown in Supplementary Materials Figure S4d. The contact resistivity decreases with V_bg and has a low value in the positive region of V_bg due to the increasing carrier channels.

In lateral devices, the source and drain contacts are directly attached to top surface of MoS₂. Therefore, the charge carriers will flow from source to drain mainly through a few top layers of MoS₂ due to the interlayer resistance [52,53]. Moreover, since the thickness of MoS₂ flake in the lateral device is ~50 nm (about 76 layers), the back-gate electric field will not affect much on the charge carrier transport. This could be the reason of a low R_planer for thick MoS₂ channel in the lateral devices.

3.4. Vertical Transport of (Cr/Au)/Mos₂/(Cr/Au) Vertical Field-Effect Transistor

We have studied vertical transport in (Cr/Au)/MoS₂/(Cr/Au) VFET, the schematic representation of which is shown in Figure 4a, and inset of Figure 4b shows the scanning electron microscope image. The thickness of MoS₂ is about 48 nm. While current bias is applied between 4 and 3, voltage is measured between 2 and 1. Figure 4b shows R_vert as a function of V_bg at room temperature. It shows similar characteristics as Gr/MoS₂/(Cr/Au) VFET, but with a low R_vert, which may be due to the low interface resistance between Cr/Au and MoS₂. The strong screening of electric field by the bottom Cr/Au electrode creates a weaker dependence on V_bg. The I-V characteristics show almost ohmic behavior at different back-gate voltages (see Figure 4c).

Although R_vert of (Cr/Au)/MoS₂/(Cr/Au) VFET in Figure 4b decreases as V_bg is increased, the relative change of R_vert is rather small. To compare the relative change of R_vert we obtain R_vert/R₀ as a function of V_bg, where R₀ at V_bg = −10 V is taken as a reference resistance. Figure 5a shows R_vert/R₀ as a function of V_bg for Gr/MoS₂/(Cr/Au) and (Cr/Au)/MoS₂/(Cr/Au) VFETs. The thickness of MoS₂ is 50 nm and 48 nm for Gr/MoS₂/(Cr/Au) and (Cr/Au)/MoS₂/(Cr/Au) VFETs, respectively. Of note, V_bg does not significantly affect transport characteristics in (Cr/Au)/MoS₂/(Cr/Au) VFET, because the bottom Cr/Au electrode effectively screens the electric field from the V_bg application. However, R_vert/R₀ has a strong dependence on V_bg in Gr/MoS₂/(Cr/Au) devices, due to the weak screening of the electric field by bottom monolayer Gr. For comparison, we also present R_planar/R₀ as a function of V_bg in Figure 5b. A rapid increase of R_planar/R₀ below V_bg = −30 V indicates the threshold voltage of n-type MoS₂ channel in our devices. The dependence of R_planar/R₀ on V_bg is much larger than VFETs, asMoS₂ channel is directly affected by V_bg application in ordinary planar geometry.

In the positive region of V_bg, both resistances in planar (in-plane) and vertical configuration show a similar dependence of V_bg. However, at negative V_bg, we find different dependences of V_bg as seen in Figure 5a,b. In Figure 5a R_vert/R₀ shows an exponential dependence of V_bg for Gr/MoS₂/(Cr/Au) VFET with 50 nm-thick MoS₂ flake. This might be due to the gate-voltage dependent density of states in graphene, which affects the interface resistance between graphene and MoS₂. In case of (Cr/Au)/MoS₂/(Cr/Au) VFET with 50 nm-thick MoS₂, there exists large screening effect by the bottom Cr/Au electrode that does not allow the back-gate electric field to influence on the electronic transport. On the other hand, in case of planar 48 nm-thick MoS₂ FET of Figure 5b, we have source/drain (Cr/Au) electrodes directly on the lateral channel of MoS₂. At a particular negative V_bg, the channel transport is in off-state, so resistance increases rapidly at V_bg below the threshold voltage.

4. Conclusions

In the present study, we performed four probe measurements using cross-junction geometry of Gr/MoS₂/(Cr/Au) VFETs. We were able to achieve gate-tunable transport characteristics in VFETs. Since the bottom Gr allows the electric field to reach MoS₂ channel, the vertical resistance (R_vert) of Gr/MoS₂/(Cr/Au) VFET can be effectively modified by V_bg. The vertical transport characteristics are examined as compared to those of the ordinary lateral MoS₂ field-effect transistor. R_vert increases as the thickness of MoS₂ increases, whereas R_planar decreases. The increase of R_vert in the thicker MoS₂ film can be attributed to the interlayer resistance in the vertical direction. However, R_planar shows a lower value for a thicker MoS₂ film because of excess of charge carriers available in upper layers connected directly to source/drain contacts and cumulative contribution of low R_int from the lower layers. In planer geometry only, layers attached near to channel layer (on which source/drain electrodes are constructed) are the main source of the conduction mechanism. Schottky barrier height at Gr/MoS₂ interface can be analyzed from the I_ds-V_ds curve. The Schottky barrier height decreases as V_bg or V_ds increases. V_bg does not affect transport characteristics much in (Cr/Au)/MoS₂/(Cr/Au) VFET, because the bottom Cr/Au electrode effectively screens the electric field from the V_bg application. However, a strong dependence on V_bg in Gr/MoS₂/(Cr/Au) devices was observed due to the weak screening of electric field by bottom Gr. We believe that gate tunable VFET will serve as one of important components for future 2D materials electronics.