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Appl. Sci. 2017, 7(3), 246; doi:10.3390/app7030246

Metal-Insulator-Metal Single Electron Transistors with Tunnel Barriers Prepared by Atomic Layer Deposition

1
Department of Electrical Engineering, University of Notre Dame, Notre Dame, IN 46556, USA
2
Lashkaryov Institute of Semiconductor Physics, 03028 Kyiv, Ukraine
3
Present address: Electrical Engineering and Computer Sciences, University of California, Berkeley, Berkeley, CA 94720-1770, USA
4
Present address: Intel Corp, 2501 NW 229th Ave., Hillsboro, OR 97124, USA
5
Present address: Cypress Semiconductor Corp, 2401 East 86th St., Bloomington, MN 55425, USA
*
Author to whom correspondence should be addressed.
Academic Editor: Antonio Ficarella
Received: 16 January 2017 / Accepted: 27 February 2017 / Published: 3 March 2017
(This article belongs to the Special Issue Applied Single-Electron Transistors)
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Abstract

Single electron transistors are nanoscale electron devices that require thin, high-quality tunnel barriers to operate and have potential applications in sensing, metrology and beyond-CMOS computing schemes. Given that atomic layer deposition is used to form CMOS gate stacks with low trap densities and excellent thickness control, it is well-suited as a technique to form a variety of tunnel barriers. This work is a review of our recent research on atomic layer deposition and post-fabrication treatments to fabricate metallic single electron transistors with a variety of metals and dielectrics. View Full-Text
Keywords: single electron transistor; atomic layer deposition; tunnel barrier single electron transistor; atomic layer deposition; tunnel barrier
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MDPI and ACS Style

Karbasian, G.; McConnell, M.S.; George, H.; Schneider, L.C.; Filmer, M.J.; Orlov, A.O.; Nazarov, A.N.; Snider, G.L. Metal-Insulator-Metal Single Electron Transistors with Tunnel Barriers Prepared by Atomic Layer Deposition. Appl. Sci. 2017, 7, 246.

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