High-Resolution Digital-to-Time Converter Implemented in an FPGA Chip
AbstractThis paper presents the design and implementation of a new digital-to-time converter (DTC). The obtained resolution is 1.02 ps, and the dynamic range is about 590 ns. The experimental results indicate that the measured differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.17~+0.13 LSB and −0.35~+0.62 LSB, respectively. This DTC builds coarse and fine Vernier delay lines constructed by programmable delay lines (PDLs) to ensure high performance delay. Benefited by the close-loop feedback mechanism of the PDLs’ control module, the presented DTC has excellent voltage and temperature stability. What is more, the proposed DTC can be implemented in a single field programmable gate array (FPGA) chip. View Full-Text
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Wang, H.; Zhang, M.; Liu, Y. High-Resolution Digital-to-Time Converter Implemented in an FPGA Chip. Appl. Sci. 2017, 7, 52.
Wang H, Zhang M, Liu Y. High-Resolution Digital-to-Time Converter Implemented in an FPGA Chip. Applied Sciences. 2017; 7(1):52.Chicago/Turabian Style
Wang, Hai; Zhang, Min; Liu, Yan. 2017. "High-Resolution Digital-to-Time Converter Implemented in an FPGA Chip." Appl. Sci. 7, no. 1: 52.
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