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Appl. Sci. 2017, 7(1), 52; doi:10.3390/app7010052

High-Resolution Digital-to-Time Converter Implemented in an FPGA Chip

Key Laboratory of Electronic Equipment Structure Design, Ministry of Education, School of Electro-Mechanical Engineering, Xidian University, Xi’an 710071, China
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Academic Editor: Hung-Yu Wang
Received: 9 November 2016 / Revised: 24 December 2016 / Accepted: 27 December 2016 / Published: 4 January 2017
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Abstract

This paper presents the design and implementation of a new digital-to-time converter (DTC). The obtained resolution is 1.02 ps, and the dynamic range is about 590 ns. The experimental results indicate that the measured differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.17~+0.13 LSB and −0.35~+0.62 LSB, respectively. This DTC builds coarse and fine Vernier delay lines constructed by programmable delay lines (PDLs) to ensure high performance delay. Benefited by the close-loop feedback mechanism of the PDLs’ control module, the presented DTC has excellent voltage and temperature stability. What is more, the proposed DTC can be implemented in a single field programmable gate array (FPGA) chip. View Full-Text
Keywords: digital-to-time converter; FPGA; programmable delay lines; time and frequency analysis digital-to-time converter; FPGA; programmable delay lines; time and frequency analysis
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This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. (CC BY 4.0).

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Wang, H.; Zhang, M.; Liu, Y. High-Resolution Digital-to-Time Converter Implemented in an FPGA Chip. Appl. Sci. 2017, 7, 52.

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