Digital Controller Design Based on Active Damping Method of Capacitor Current Feedback for Auxiliary Resonant Snubber Inverter with LC Filter

Abstract

In some high-performance applications, an LC filter must be added to the auxiliary resonant snubber inverter (ARSI) to reduce the output current ripple. However, resonance occurs due to the additional LC filter, which makes the traditional closed-loop control not suitable to be used directly. Therefore, this paper presents a double-loop digital control based on the active damping method of capacitor current feedback to stabilize the system. Most of the studies on active damping methods are focused on the grid in consideration of zero resistance. However, the load resistance should not be neglected in the drive system. Therefore, the load resistance and digital control delays are considered in this paper. Moreover, an improved loading method is proposed to improve the duty ratio range. In order to verify the effectiveness of the controller, a prototype was developed. The simulation and experimental results demonstrate that soft-switching can be realized for the entire load range. The maximum duty ratio is improved by 0.01 by using the proposed loading method. The resonance can be eliminated by using the proposed control method.

1. Introduction

In power electronic converters, high switching frequency is a highly desirable feature, which can not only reduce the volume and power density of converters, but also increase the dynamic response. However, high switching frequency brings about the problems of high switching loss and severe electromagnetic interference (EMI) [1,2]. The soft switching technique is one of the best options to address the problems above. To date, a variety of soft-switching DC-AC topologies have been proposed. Among them, the zero-voltage-transition (ZVT) pulse-width-modulation (PWM) inverter is a typical soft-switching inverter [3,4,5,6,7,8,9,10,11]. An auxiliary circuit connected parallel to the main power path is employed in the ZVT PWM inverter, which only operates for a short interval before and after the commutation period of the main switches. This makes the ZVT inverter closest to the PWM converter counterpart. Compared with other soft-switching inverters, the voltage and current stresses and conduction losses are much lower [3,4]. Contributing to these advantages, the ZVT PWM inverter is well accepted.

Several topologies of the ZVT PWM inverter have been proposed. The auxiliary resonant commutated pole inverter (ARCPI) has been proposed with two auxiliary switches per phase [5,6]. The ARCPI can meet the demand for high efficiency and low voltage and current stresses. However, the major drawback is the existence of the split capacitors, which cause the problems of capacitor charge unbalance. The auxiliary resonant snubber inverter (ARSI) has been proposed to eliminate the split capacitors, but the three-phase topology cannot utilize the conventional space-vector-pulse-width modulation (SVPWM) [7,8]. Thus, they are more suitable for permanent magnet brushless DC motors instead of all types of motors. The single-phase topology is very attractive with only two auxiliary switches and well fit to the conventional PWM. Meanwhile, the ZVT inverter using coupled magnetics has been proposed to eliminate the split capacitors [9,10,11]. However, these topologies need coupled inductors and a large number of auxiliary switches, which increases the cost and difficulty of the circuit realization. The ZVT PWM converter has been synthesized and summarized in [3,4].

In high-precision motor drive applications, an LC filter must be added in the ARSI to reduce the output current ripple. Moreover, the additional LC filter can solve problems of poor insulation that result from the overvoltage [12]. However, since the additional LC filter together with the inductor of the motor forms the LCL filter, a resonance peak occurs in the system, which makes the system unstable. Recently, the passive damping method has been used to stabilize the system [13,14]. The passive components of resistors, capacitors, and inductors are parallel or series-connected to the filter capacitor to damp out the resonance. The method is easy to implement; however, it reduces the efficiency of the system. The active damping method can be used to damp out the resonance at no expense of efficiency. The state variable feedback, such as filter capacitor voltage [15,16] or filter capacitor current [17,18], is introduced to provide virtual resistance. Among them, the capacitor current feedback is a typical and widely used method.

Most studies of the active damping method have focused on the grid with consideration of zero resistance. However, in the drive system, the load resistance should not be neglected. Until now, only a few researchers have studied the active damping in the motor drive system; however, they have not taken into consideration the digital control delays. In addition, previous studies on ARSI have focused on the circuit design and auxiliary current control but there has been a lack of research about the design of the closed-loop control. Thus, a step-by-step closed-loop controller design of the ARSI with LC filter is proposed in this paper, including the auxiliary current controller and the output current controller. A double-loop control based on active damping method of capacitor current feedback and PI regulator is introduced. The load resistance and digital control delays are considered. Moreover, an improved loading scheme of digital PWM (DPWM) is proposed to improve the duty ratio range of the ARSI. Finally, simulations and experiments are carried out to verify the effectiveness of the proposed method.

2. Control of the ARSI

Figure 1 depicts the single-phase ARSI topology analyzed in this paper, which consists of a standard H-bridge inverter, an auxiliary circuit, and an LC filter. The proper operation of the auxiliary switches S_r1 and S_r2 can create zero-voltage-switching (ZVS) conditions for the main switches S₁–S₄. Meanwhile, the auxiliary switches can realize zero-current switching (ZCS).

Figure 2 shows a control diagram of the ARSI. The ARSI controller consists of an output current controller and an auxiliary current controller. In the output current controller, the driving signals of the main switches are generated according to the output current. In order to dampen the resonance caused by the LC filter, a filter capacitor current feedback is introduced. The auxiliary current controller aims to control the auxiliary current to achieve ZVS of the main switches. Due to the large amount of calculations and the need for logic sequential control in the auxiliary current controller, a digital controller is required.

The auxiliary current control involves two methods, fixed-timing control [19] and variable-timing control [20]. Owing to the advantages of lower conduction losses and achieving soft-switching for a wide load range, variable-time control methods are more widely used. By using the variable-timing control, the auxiliary current follows the magnitude of the load current adaptively. The auxiliary current controller in Figure 2 is realized based on the variable-timing control. The auxiliary controller is influenced by the output current controller, whereas the output current controller is independent of the auxiliary current controller.

3. The Load Adaptive Auxiliary Current Control

3.1. Principle

Essentially, the ZVS realization of the main switches is to obtain a proper initial resonant current I_r, in order to discharge the resonant capacitors to zero voltage before the main switches are turned on. Figure 3 shows the key waveforms to realize ZVS of S₁ and S₄, where v_ds is the drain-source voltage of a MOSFET, i_d is the drain current of a MOSFET, v_g is the gate signal, i_Lf is the filter inductor current, i_{Lf_l} is the lower envelope of i_Lf, i_{Lf_u} is the upper envelope of i_Lf, and i_Lr is the auxiliary current. When i_{Lf_l} < −I_{r_min}, i_{Lf_l} can create natural ZVS (NZVS) conditions for S₁ and S₄ without the operation of auxiliary switches. When i_{Lf_l} > −I_{r_min}, S_r1 is turned on before S₂ and S₃ are turned off. The resonant inductor L_r is charged, resulting in the linear increase of the auxiliary current. Therefore, a proper I_r can be obtained with the operation of S_r1. The auxiliary ZVS (AZVS) of S₁ and S₄ is realized. In order to fully discharge the resonant capacitors, the minimum initial resonant current must meet the following requirement:

$$I_{r\_\min }\ge \frac{2C_r{V}_s}{t_{dead}}.$$

(1)

The principle of ARSI without LC filter was introduced in [21]. The initial resonant current is the difference between the auxiliary current and the output current. Namely, the required auxiliary current is the sum of the output current and initial resonant current. As for the ARSI with LC filter, the auxiliary current is the sum of the filter inductor envelope current and the initial resonant current, which is different from that of the ARSI without LC filter.

The filter current ripple can be calculated as follows:

$$\Delta i_{Lf}=\frac{V_s-v_o}{L_f}D{T}_s=\frac{(2-2D)D{V}_s{T}_s}{L_f},$$

(2)

where v_o is the output voltage, D is the duty ratio, and T_s is the switching period.

The upper and lower envelopes of the filter inductor current can be calculated as follows:

$$i_{Lf\_u}=i_o+\frac{1}{2}\Delta i_{Lf}=i_o+\frac{(1-D)D{V}_s{T}_s}{L_f}$$

(3)

$$i_{Lf\_l}=i_o-\frac{1}{2}\Delta i_{Lf}=i_o-\frac{(1-D)D{V}_s{T}_s}{L_f}.$$

(4)

The ZVS realization of S₁ and S₄ is related to the lower envelope of the filter inductor current i_{Lf_l} shown in Figure 3. Similarly, the ZVS realization of S₂ and S₃ is related to the upper envelope of the filter inductor current i_{Lf_u}.

Table 1. Zero-voltage switching (ZVS) types of switches under different output currents.

Switch	iLf_l < −Ir_min	iLf_l > −Ir_min	Switch	iLf_u < Ir_min	iLf_u > Ir_min
S1 & S4	NZVS	AZVS (Sr1)	S2 & S3	AZVS (Sr2)	NZVS

shows the ZVS types under different load conditions.

The output current can be obtained through the current sensor. Therefore, the required auxiliary current can be calculated as follows:

$$I_{Lrm}=\{\begin{array}{ll}{I}_r+i_{Lf\_l}& for{S}_{r1}\\ I_r-i_{Lf\_u}& for{S}_{r2}\end{array}.$$

(5)

The charging rate and the discharging rate of the resonant inductor are the same because of the same voltage V_s. Therefore, the charging time of the resonant inductor t_ch and the on-time of the auxiliary switch t_A can be calculated as follows:

$$t_{ch}=\frac{L_r{I}_{Lrm}}{V_s}$$

(6)

$$t_A=2t_{ch}+t_{dead}.$$

(7)

After generating the driving signals of the main switches, the gate signal of the auxiliary switches can be generated from Equations (6) and (7).

3.2. Limitation of the Duty Ratio

In the ARSI, to guarantee the ZVS of one set of switches, the auxiliary circuit must be turned on before the opposite set of switches is turned off. Subsequently, the resonant inductor can be charged to the required current. Therefore, the minimum on-time of the opposite set of switches must be longer than the maximum charging time of the resonant inductor. This requirement limits the maximum duty ratio D_max.

Figure 4 shows the DPWM diagram of the ARSI. The triangle carrier is adopted due to its lower harmonic compared to the sawtooth carrier [22]. Moreover, the current is synchronously sampled at twice the PWM carrier interval, which can eliminate the switching current ripple from the current samples without needing low-pass filtering or complex ripple elimination filters [23]. Then the calculated reference voltage v_c is loaded into a modulator at the point of upper limit and lower limit of the reference voltage V_upperlimit and V_lowerlimit, instead of the conventional loading point V_cmax and V_cmin. The proposed loading method can improve the maximum duty ratio. The reason is given as follows:

In order to achieve ZVS from zero load to full load, the minimum on-time of the main switches must be longer than the maximum charging time of the resonant inductor:

$$t_{on\_\min }\ge t_{ch\_\max }.$$

(8)

The maximum charging time occurs when the output current reaches its maximum value I_{o_max}. The minimum on-time of the main switches occurs when the duty ratio reaches D_max. Figure 5 shows the DPWM diagram at the condition of I_{o_max} and D_max. Figure 5a shows the conventional loading scheme, namely loading at V_cmax and V_cmin. The Kth current is sampled at the point V_cmin. Then the data are loaded at the next V_cmax after calculation. Subsequently, S_r1 can be turned on to charge the resonant inductor. Therefore, the following requirement must be met based on Equation (8):

$$\frac{T_s}{2(V_{c\max }-V_{c\min })}(V_{c\max }-V_{upperlimit})\ge t_{ch\_\max }.$$

(9)

The upper limit of the reference voltage can be obtained from Equation (9):

$$V_{upperlimit}\le V_{c\max }-\frac{2(V_{c\max }-V_{c\min })t_{ch\_\max }}{T_s}.$$

(10)

The maximum duty ratio D_max occurs when t_{on_min} equals t_{ch_max}. However, Figure 5a shows that t_{on_min} is still longer than t_{ch_max} in this case. Only after the Kth data are loaded at V_cmax, S_r1 can be controlled. In this case, a short time cannot be utilized.

In order to improve D_max, an improved loading scheme is adopted in which the data are loaded at V_upperlimit and V_lowerlimit. In this case, S_r1 can be turned on in advance. Furthermore, this loading scheme will not influence the gate signal generation of the main switches because the reference voltage v_c is limited between V_upperlimit and V_lowerlimit. Figure 5b shows that t_{on_min} equals t_{ch_max} by using the improved loading scheme, which improves D_max.

In the improved loading scheme, the following requirement must be satisfied based on Equation (8):

$$\frac{T_s}{2(V_{c\max }-V_{c\min })}·2(V_{c\max }-V_{upper\lim it})-t_{dead}\ge t_{ch\_\max }.$$

(11)

The upper limit of the reference voltage can be obtained from Equation (11):

$$V_{upperlimit}\le V_{c\max }-\frac{(V_{c\max }-V_{c\min })(t_{ch\_\max }+t_{dead})}{T_s}.$$

(12)

From Equations (10) and (12), the limit of the reference voltage v_c can be improved by adopting the improved loading scheme, resulting in larger D_max.

4. Output Current Control

4.1. The Model of the ARSI

Figure 6 shows the digital control model of the output current controller, where G_c(z) is the proportional integral (PI) regulator, G_dc(z) is the calculation and transport delay, the sampling switch stands for analog digital converter, K_pwm is the gain of the ARSI, K_cf is the filter capacitor current feedback coefficient, and G₁(s) and G₂(s) are the output impedance. In the digital controller, all the calculations and operations are discrete. Therefore, the digital controller is modeled on the z-domain.

4.2. PI Controller Design

Commonly, the sample period is short and the time constant of the controlled plant is much larger than the sample period. Therefore, the digital PI controller can be designed in the s-domain. Figure 7 shows the output current controller model in the s-domain.

The PI regulator G_c(s) can be written as follows:

$$G_c(s)=K_p+\frac{K_i}{s}.$$

(13)

After the current is sampled, a sampling period delay T_sp exists, which is shown in Figure 4. Therefore, the calculation and transport delay can be written as follows:

$$G_{dc}(s)=e^{-T_{sp}s},$$

(14)

where the sampling period T_sp = T_s/2.

In the s-domain, the sampling switch can be modeled as 1/T_sp [24]. The modulator can be modeled by zero-order holder (ZOH) [25], which can be expressed as:

$$H(s)=\frac{1-e^{-T_{sp}s}}{s}\approx T_{sp}{e}^{-0.5T_{sp}s}.$$

(15)

Commonly, the cutoff frequency of the LC filter is larger than the bandwidth frequency of the ARSI. Therefore, the filter inductance is much lower than the load inductance, namely L_f << L_o. The output impedance can be written as follows:

$$G_1(s)=\frac{i_{cf}(s)}{v_o(s)}=\frac{s^2{L}_o{C}_f+s{R}_o{C}_f}{s^3{L}_f{C}_f{L}_o+s^2{L}_f{C}_f{R}_o+s(L_o+L_f)+R_o}\approx \frac{s{C}_f}{s^2{L}_f{C}_f+1}$$

(16)

$$G_2(s)=\frac{i_o(s)}{i_{cf}(s)}=\frac{1}{s^2{L}_o{C}_f+s{R}_o{C}_f}.$$

(17)

The system open-loop transfer function can be calculated as follows:

$$G(s)=\frac{i_o(s)}{i_o^{*}(s)-i_o(s)}=(K_p+\frac{K_i}{s})·\frac{K_{pwm}{e}^{-1.5T_{sp}s}}{(s^2{L}_f{C}_f+1)(s{L}_o+R_o)+s{K}_{pwm}{K}_{cf}{e}^{-1.5T_{sp}s}{C}_f(s{L}_o+R_o)}.$$

(18)

The closed-loop transfer function can be written as follows:

$$T(s)=\frac{i_o(s)}{i_o^{*}(s)}=\frac{G_{dc}(s)G_c(s)G_P(s)}{1+K_{cf}{G}_{dc}(s)G_T(s)+G_{dc}(s)G_c(s)G_P(s)}.$$

(19)

In order not to reduce the bandwidth of the ARSI, the cutoff frequency of the LC filter is designed to be two times larger than the system bandwidth f_c. Therefore, the influence of the filter capacitor can be ignored when calculating the magnitude of the loop gain at f_c and frequencies lower than f_c. The low-frequency controller characteristics will still be dominated by the series filter inductance. Thus, the transfer Equation (18) can be approximated as follows:

$$G(s)\approx (K_p+\frac{K_i}{s})·\frac{K_{pwm}{e}^{-1.5T_{sp}s}}{s{L}_o+R_o}.$$

(20)

Figure 8 shows the Bode plots of the approximation model (20) and the precise model (18). It demonstrates that the cutoff frequency of the system will not be influenced by using the approximation model.

When the crossover frequency and phase margin are specified as ω_c and φ_m respectively, the parameters of the PI controller can be obtained:

$$\{\begin{array}{l}{K}_p=\frac{\sqrt{{(L_o{\omega }_c)}^2+R_o^2}}{K_{pwm}\sqrt{1+\frac{1}{{\tan }^2(-\frac{\pi }{2}+1.5{\omega }_c{T}_{sp}+{\varphi }_m+\arctan \frac{{\omega }_c{L}_o}{R_o})}}}\hfill \\ K_i=\frac{{\omega }_c{K}_p}{\tan (-\frac{\pi }{2}+1.5{\omega }_c{T}_{sp}+{\varphi }_m+\arctan \frac{{\omega }_c{L}_o}{R_o})}\hfill \end{array}.$$

(21)

If K_p >> K_i/ω_c, Equation (21) can be approximated as:

$$\{\begin{array}{l}{K}_p=\frac{\sqrt{{(L_o{\omega }_c)}^2+R_o^2}}{K_{pwm}}\hfill \\ K_i=\frac{{\omega }_c{K}_p}{\tan (-\frac{\pi }{2}+1.5{\omega }_c{T}_{sp}+{\varphi }_m+\arctan \frac{{\omega }_c{L}_o}{R_o})}\hfill \end{array}.$$

(22)

Figure 9 shows the Bode plot of the ARSI with different PI parameters. The circuit parameters are listed in

Table 2. Parameters of the circuit.

Parameter	Value
DC voltage Vs	80 V
Switching frequency fs	200 kHz
Dead time tdead	0.2 μs
Load	3.7 Ω, 4.87 mH
Resonant inductor Lr	2.2 μH
Resonant capacitor Cr	2.7 nF
Filter inductor Lf	22 μH
Filter capacitor Cf	1 μF
Maximum output current Io_max	8 A

. When K_p >> K_i/ω_c, the crossover frequency ω_c is determined by K_p. The larger K_p, the larger ω_c and the faster the dynamic response. Regarding K_i, it will influence the low-frequency gain, which can influence the stable precision of the system. The larger K_i, the larger the low-frequency gain and the higher the stable precision. K_i has almost no influence on the frequency characteristic around ω_c when K_p >> K_i/ω_c. However, when K_i/ω_c is close to K_p, K_i will influence the phase margin. The larger K_i, the smaller the phase margin.

4.3. Capacitor Current Feedback Design

In Section 4.2, the influence of filter capacitor is neglected when the PI parameters are designed. However, the LC filter together with the load inductance forms the LCL filter, which leads to resonance. To analyze the stability of the ARSI, the influence of filter capacitor cannot be ignored. The filter capacitor current feedback is introduced to damp the resonance.

Because of the delay caused by the computation, the system is no longer a minimum phase system. To design the inner capacitor current loop, a discrete model must be built instead of a continuous model. Figure 10 shows the model of the inverter, which is obtained from Figure 6.

The closed-loop and open-loop transfer functions can be obtained as follows. (The detailed proof is presented in Appendix A.)

$$T(z)=\frac{i_o(z)}{i_o^{*}(z)}=\frac{G_{dc}(z)G_c(z)G_P(z)}{1+K_{cf}{G}_{dc}(z)G_T(z)+G_{dc}(z)G_c(z)G_P(z)}$$

(23)

$$G(z)=\frac{i_o(z)}{i_o^{*}(z)-i_o(z)}=\frac{G_{dc}(z)G_c(z)G_P(z)}{1+K_{cf}{G}_{dc}(z)G_T(z)},$$

(24)

where

$$G_c(z)=K_p+\frac{K_i}{1-z^{-1}}$$

$$G_{dc}(z)=z^{-1}$$

$$G_T(z)=K_{pwm}\sqrt{\frac{C_f}{L_f}}\frac{(z-1)\sin \phi }{z^2-2z\cos \phi +1}$$

$$G_P(z)=K_{pwm}\frac{-z(R_{o}F\cos \phi +L_o{\omega }_{res}F\sin \phi -R_{o}F)+R_{o}F-R_{o}F\cos \phi +L_o{\omega }_{res}F\sin \phi }{z^2-2z\cos \phi +1}$$

$$F=\frac{L_f{C}_f}{L_o^2+L_f{C}_f{R}_o^2}$$

$$\phi ={\omega }_{res}{T}_{sp}$$

$${\omega }_{res}=\frac{1}{\sqrt{L_f{C}_f}}.$$

In the z-domain, the root locus is used to analyze the stability of the system. The relevant expressions can be developed from Equation (23) as follows:

$$1+K_{cf}{G}_{dc}(z)G_T(z)+G_{dc}(z)G_c(z)G_P(z)=0.$$

(25)

Equation (19) can be transformed as follows:

$$1+K_{cf}\frac{G_{dc}(z)G_c(z)}{1+G_{dc}(z)G_c(z)G_P(z)}=0.$$

(26)

From Equation (26), the root locus related to K_cf can be plotted in Figure 11. When the capacitor current feedback is not used, namely K_cf = 0, the closed-loop poles are outside the unit circle, which demonstrates that the system is unstable. As K_cf increases, the system becomes stable. However, if K_cf is too large, the system becomes unstable again.

Figure 12 shows the Bode plot with different K_cf which is obtained from Equation (24). In the magnitude-frequency characteristic, K_cf hardly influences the low-frequency characteristic. As K_cf increases, the open-loop gain decreases slightly around the crossover frequency ω_c. Besides, the resonance peak is damped. In the phase-frequency characteristic, the phase margin decreases with the increase of K_cf. When K_cf is large enough, the phase-frequency curve crosses −180° after it drops to −180°. This makes the system unstable according to the stability criterion.

In order to stabilize the system, the active damping gain K_cf must meet the requirements as follows. (The detailed proof is presented in Appendix B.)

$$K_{cf\min 1}<K_{cf}<K_{cf\max 1}\mathrm{and}{K}_{cf\min 2}<K_{cf}<K_{cf\max 2},$$

(27)

where

$$K_{cf\min 1}=\frac{-1-\cos \phi +K_{pwm}{L}_o{\omega }_{res}F\sin \phi }{K_{pwm}\sqrt{\frac{C_f}{L_f}}\sin \phi }$$

$$K_{cf\max 1}=\frac{1+\cos \phi -K_p{K}_{pwm}F(R_o\cos \phi -R_o-2L_o{\omega }_{res}\sin \phi )}{2K_{pwm}\sqrt{\frac{C_f}{L_f}}\sin \phi }$$

$$K_{cf\min 2}=-\frac{\frac{1-2\cos \phi }{2}-K_p{K}_{pwm}F(R_o-R_o\cos \phi +L_o{\omega }_{res}\sin \phi )+\sqrt{\frac{{(1-2\cos \phi )}^2}{4}+K_p{K}_{pwm}(2R_{o}F\cos \phi -2R_{o}F)}}{K_{pwm}\sqrt{\frac{C_f}{L_f}}\sin \phi }$$

$$K_{cf\max 2}=-\frac{\frac{1-2\cos \phi }{2}-K_p{K}_{pwm}F(R_o-R_o\cos \phi +L_o{\omega }_{res}\sin \phi )-\sqrt{\frac{{(1-2\cos \phi )}^2}{4}+K_p{K}_{pwm}(2R_{o}F\cos \phi -2R_{o}F)}}{K_{pwm}\sqrt{\frac{C_f}{L_f}}\sin \phi }.$$

5. Design Example

The circuit parameters are listed in Table 2. The specifications are given as the crossover frequency f_c ≈ 10 kHz and the phase margin φ_m > 45°.

(1) Determination of the initial resonant current I_r:

According to Equation (1), the minimum initial resonant current is given as I_{r_min} > 2.16 A. The minimum initial resonant current and the initial resonant current for AZVS are selected as I_{r_min} = 2.5 A and I_{r_A} = 5 A, respectively. Therefore, when i_{Lf_l} < −2.5 A, S_r1 is not operated, achieving NZVS of S₁ and S₄ according to Table 1. Otherwise, S_r1 would be turned on properly to realize AZVS of S₁ and S₄. Regarding S₂ and S₃, when i_{Lf_u} < 2.5 A, S_r2 must be turned on to create AZVS conditions. When i_{Lf_u} > 2.5 A, S₂ and S₃ can achieve NZVS.

(2) Determination of the upper limit and lower limit of the DPWM (V_upperlimit and V_lowerlimit)

The frequency of the DPWM clock is 120 MHz. Thus, the carriers are specified as V_cmax = 300 and V_cmin = 0 to achieve 200 kHz switching frequency. To simplify the calculation, the filter inductor current ripple is neglected. Therefore, the maximum required auxiliary current can be obtained from Equation (5) as I_{Lrm_max} = I_{r_A} + I_{o_max} = 13 A. The maximum charging time t_{ch_max} can be calculated from Equation (6) as t_{ch_max} = 357.5 ns. The upper limit can be calculated from Equation (12) as V_upperlimit ≈ 266 by using the improved loading scheme. Thus, the lower limit V_lowerlimit and maximum duty ratio D_max are 34 and 0.867, respectively. Regarding the conventional loading scheme, the upper limit, lower limit, and maximum duty ratio are 257, 43, and 0.857, respectively.

Table 3. Comparison of the parameters between the conventional and improved loading scheme.

Parameter	Conventional Loading Scheme	Improved Loading Scheme
Maximum Duty Ratio Dmax	0.857	0.867
Minimum Duty Ratio Dmin	0.143	0.133
Upper Limit Vupperlimit	257	266
Lower Limit Vlowerlimit	43	34

shows a comparison of the parameters between the conventional and improved loading scheme. The range of the duty ratio is improved by utilizing the improved loading scheme.

(3) Determination of the PI regulator parameters and active damping gain K_cf

The active damping gain K_cf will influence the stability of the system and the phase margin will decrease due to the increase of K_cf according to the analysis in Section 4.3. However, the influence of the filter capacitor is neglected to simplify the design of the PI regulator in Section 4.2. Therefore, in order to meet the requirement φ_m > 45°, the phase margin is specified as 60° due to the capacitor current feedback. Thus, the parameters of the PI regulator can be calculated from Equation (21). The results are that K_p = 3.6522 and K_i = 70,999. To ensure the system’s stability, the capacitor current feedback gain K_cf must meet the requirement of 0.0158 < K_cf < 0.119 according to Equation (27). The feedback gain is selected as K_cf = 0.05.

Based on the above parameters, the Bode plots of the single loop and double loop can be obtained from Figure 13. The crossover frequency of the single loop is −62,900 rad/s and the phase margin is 60°. This is in agreement with the design specifications. However, the LC filter leads to resonance, which makes the phase–frequency curve cross −180° after it drops to −180°. According to the stability criterion, the single-loop system is unstable.

Regarding the double-loop control, the crossover frequency is −61,000 rad/s and the phase margin is 46.4°. Due to the capacitor current feedback, the crossover frequency and the phase margin decrease slightly. However, this outcome meets the requirement f_c ≈ 10 kHz and φ_m > 45°. When $20\log \left|G(j\omega )\right|\ge 0$, the phase–frequency curve does not cross −180°. According to the stability criterion, the double-loop system is stable.

6. Simulations and Experiments

The method was implemented in the Altera Cyclone IV FPGA with the parameters given in Table 2. Figure 14 shows a photograph of the prototype. It consists of a FPGA (EP4CE22E22C7N, Altera Corporation, San Jose, CA, USA) control board, a switching power supply, a MOSFET driver, and a power circuit. The method is verified in the simulation using Saber.

Figure 15 and Figure 16 show the simulation and experimental transitional waveforms of the main switches, respectively. During the turn-on commutation, the drain currents i_d3 and i_d4 begin increasing after the drain-source voltage v_ds3 and v_ds4 drop to zero. ZVS of S₄ is achieved with the operation of S_r1, whereas the auxiliary switches are not turned on to achieve ZVS of S₃. Regarding the turn-off commutation, the drain current overlaps the drain-source voltage slightly because the resonant capacitance is not large enough. Due to the parasitic components, ringing occurs during the commutation in the experiment.

Figure 17 and Figure 18 show the simulation and experimental waveforms of the auxiliary current with an 8 A, 100 Hz sinusoidal output current. The peak auxiliary switch current follows the load current with clear load adaptability. It can be seen that the lower the load current, the lower the auxiliary current.

Figure 19 and Figure 20 show the simulation and experimental results of the output current with and without active damping method, respectively. Figure 19 demonstrates that strong resonance occurs in the output current without the active damping method, because closed-loop poles are outside the unit circle shown in Figure 11. After utilizing the capacitor current feedback, the poles can be moved into the unit circle. Therefore, the system can be stable both at the DC or sinusoidal output current conditions. Figure 20 also demonstrates that active damping is necessary to maintain stability and current quality.

Figure 21 and Figure 22 show the simulation and experimental results of the load dynamic response, respectively. The results demonstrate that the output current tracks the reference current quickly. However, a bit of overshot exists in the transient response.

7. Conclusions

In some high-performance applications, an LC filter must be added to the auxiliary resonant snubber inverter (ARSI) to reduce the output current ripple. This makes the system quite different to the conventional ARSI without LC filter. This paper presents the modeling and the double-loop digital control of the ARSI with LC filter. The following points can be summarized to cover the paper:

(1)

An improved loading scheme that the data is updating at the upper limit and lower limit of the carrier is proposed to improve the maximum duty ratio.

(2)

The filter capacitor current feedback is introduced to damp the resonance caused by the LC filter.

(3)

A step-by-step digital controller design method, including the auxiliary current controller and the output PI controller, is proposed, in which the computation and transport delay is considered.

The control method has been verified by simulations and experiments. The maximum duty ratio is improved by 0.01 with the proposed loading method. In addition, soft-switching can be realized for the entire load range. Also, the resonance can be eliminated with the capacitor current feedback.