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Appl. Sci. 2014, 4(2), 99-127; doi:10.3390/app4020099

Round-Off Noise of Multiplicative FIR Filters Implemented on an FPGA Platform

1
Department ESAT, KU Leuven Kulab, Zeedijk 101 Ostend 8400, Belgium
2
School of Engineering and Digital Arts, University of Kent, Canterbury Kent CT2-7NT, UK
*
Author to whom correspondence should be addressed.
Received: 28 November 2013 / Revised: 7 February 2014 / Accepted: 19 February 2014 / Published: 25 March 2014
(This article belongs to the Special Issue Digital Signal Processing and Engineering Applications)
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Abstract

The paper analyzes the effects of round-off noise on Multiplicative Finite Impulse Response (MFIR) filters used to approximate the behavior of pole filters. General expressions to calculate the signal to round-off noise ratio of a cascade structure of Finite Impulse Response (FIR) filters are obtained and applied on the special case of MFIR filters. The analysis is based on fixed-point implementations, which are most common in digital signal processing algorithms implemented in Field-Programmable Gate-Array (FPGA) technology. Three well known scaling methods, i.e., L2 bound; infinity bound and absolute bound scaling are considered and compared. The paper shows that the ordering of the MFIR stages, in combination with the scaling methods, have an important impact on the round-off noise. An optimal ordering of the stages for a chosen scaling method can improve the round-off noise performance by 20 dB.
Keywords: MFIR; FIR-filters; linear phase filters; FPGA; fixed point digital signal processing DSP; round-off noise; filter cascade structure MFIR; FIR-filters; linear phase filters; FPGA; fixed point digital signal processing DSP; round-off noise; filter cascade structure
This is an open access article distributed under the Creative Commons Attribution License (CC BY 3.0).

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MDPI and ACS Style

Vandenbussche, J.-J.; Lee, P.; Peuteman, J. Round-Off Noise of Multiplicative FIR Filters Implemented on an FPGA Platform. Appl. Sci. 2014, 4, 99-127.

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