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Article

Study on the Current-Limiting-Capable Control Strategy for Grid-Connected Three-Phase Four-Leg Inverter in Low-Voltage Network

The Key Laboratory of Smart Grid of Ministry of Education, Tianjin University, Tianjin 300072, China
*
Author to whom correspondence should be addressed.
Energies 2016, 9(9), 726; https://doi.org/10.3390/en9090726
Submission received: 7 July 2016 / Revised: 31 August 2016 / Accepted: 5 September 2016 / Published: 8 September 2016

Abstract

:
The three-phase four-leg inverter can produce balanced voltages even with unbalanced loads, yet its controller design is quite complicated. Based on the analysis on time domain equations, a decoupled sequence control strategy for the three-phase four-leg inverter in a low-voltage network is proposed. A negative sequence controller and a zero sequence controller are added to the control strategy besides the positive sequence controller. Furthermore, considering the output limit of the inverter, a current limit design scheme is raised through the analysis on each sequence current in synchronous rotating frame. In the case of asymmetry, the limit value of each sequence current can be adjusted dynamically according to the design scheme. The output currents in each sequence can be controlled and limited for different purposes respectively. Finally, simulation results based on PSCAD/EMTDC V4.5.0 verify the validity of the control strategy.

1. Introduction

In the low-voltage distribution network there are many single-phase loads, which of each phase cannot achieve absolute balance, so the voltages of the three phases are not completely symmetrical. To solve this problem as well as to improve power quality, the three-phase four-leg inverter is recommended to be used for the connection of the distributed generator to grids with a high power quality requirement [1,2,3]. In order to achieve a three-phase symmetrical output voltage, a bridge arm is applied to form the neutral point in the three-phase four-leg inverter, making the inverter more complex than the traditional one. Due to its special function, the control strategy is also very different from that of the traditional three-phase inverter [2,4]. Furthermore, studying the current-limiting scheme is meaningful for exerting the maximum capability in the case of limited inverter capacity. Unlike the three-phase inverter, this inverter’s three phase currents are different from each other, so the current limit cannot be simply determined by only one phase current in the traditional way. Besides providing a feasible method of determining the current limit, this paper also addresses the control strategy of the inverter and the way to limit the output current.
As the important role of the three-phase four-leg inverter is balancing voltage, its control strategy has been studied by many insiders. According to the analysis by using symmetrical component method and large-signal averaged modeling method, it is found that an asymmetric output voltage is generated when the three-phase inverter fails to keep the neutral point potential constant in the case of unbalanced loads [5]. The research on three-phase inverters with unbalanced loads is also widely carried out [6,7,8,9,10], but constrained by the structure, it is difficult to completely solve the problem of voltage asymmetry. On this basis, the structure of neutral point clamped (NPC) inverter begins to be studied [11,12]. Its DC capacitor is split and the midpoint is connected with the neutral line. However, problems of neutral point voltage balancing and low DC voltage utilization are complicated. Another method to solve the voltage asymmetry problem is the three-phase four-leg structure. According to modeling and analyzing the load neutral point voltage (LNPV) of three-phase four-leg inverter, the factors influencing the LNPV are revealed, and the methods to mitigate the LNPV is proposed [13]. The transfer functions of open-loop control or the proportional integral (PI) controller in the synchronous frame are studied in [14], and a method of restraining current disturbances to the three-phase four-leg inverter with unbalanced load is proposed. A strategy with model predictive control is proposed and the mathematical model of the four-leg inverter is analyzed in [15]. To keep the voltage three-phase balanced, a method of eliminating the neutral current is studied [16]. Paper [17] proposes a method based on modified repetitive control (MRC) which integrates with a non-phase-shifting low-pass filter, having a better tradeoff between the performance and robustness of repetitive control, but the effectiveness of this method is highly subject to the pole placement, bandwidth, and damping coefficient of the MRC. By using the symmetrical component method, each component can be decomposed into positive, negative, and zero sequence, which can simplify the control of three-phase four leg inverter [18,19]. Space-vector-modulation strategies respectively based on ABC and 3D coordinate systems are proposed in [20,21,22], but they are sort of complicated. However, the papers above only focus on the control strategy of the three-phase four-leg inverter, and do not involve discussion on how to play its maximum capacity when the output current is limited.
This paper is focused on a simple control strategy of the three-phase four-leg inverter connected to the low-voltage network with unbalance loads. By decoupling the mathematical model of three-phase four-leg inverter to three-phase form and single-phase form with the symmetrical component method, a sequence-independent control scheme is presented. On this basis, the current-limiting scheme is proposed for the inverter to achieve the maximum output capability with the output current of each leg under the limit.

2. Control Strategy of the Three-Phase Four-Leg Inverter

2.1. Modeling and Analysis of the Three-Phase Four-Leg Inverter

Compared with the traditional three-phase inverter, the three-phase four-leg inverter has an extra bridge arm as the neutral point, shown as Figure 1.
In Figure 1, u dc is the DC voltage, u a , u b , u c , u n each represent a leg voltage, i n is the current flowing through the neutral inductor L n , u sa , u sb , u sc are respectively the voltages of the three phases at the point of common coupling (PCC), and i a , i b , i c are the currents flowing into PCC. L f is the three-phase inductance of filter and C f is the filter capacitance.
It is shown in Figure 1 that the fourth leg can provide a pathway for zero-sequence current. According to the topological structure, the differential equation of the circuit can be written as
u a = L f ( d i a d t + C f d 2 u sa d t 2 ) + u sa u b = L f ( d i b d t + C f d 2 u sb d t 2 ) + u sb u c = L f ( d i c d t + C f d 2 u sc d t 2 ) + u sc u n = L n d i n d t
Since most of the high-frequency harmonic components of the output voltage and current can be filtered by the grid-connected filter, they are not discussed for the basic control strategy study in this paper. The following analyses are based on fundamental components of 50 or 60 Hz.
To achieve the decoupling of each sequence component with the symmetrical component method, (1) is transformed to the phasor Equation (2).
[ U ˙ a U ˙ b U ˙ c ] = j ω L f [ I ˙ a I ˙ b I ˙ c ] + ( 1 ω 2 L f C f ) [ U ˙ sa U ˙ sb U ˙ sc ]
Multiplying (2) by the symmetrical component transformation matrix S , we get
S [ U ˙ a U ˙ b U ˙ c ] = j ω L f S [ I ˙ a I ˙ b I ˙ c ] + ( 1 ω 2 L f C f ) S [ U ˙ sa U ˙ sb U ˙ sc ]
where the matrix S is
S = 1 3 [ 1 a a 2 1 a 2 a 1 1 1 ]
where the operator a = e j 120 .
Then there is
[ U ˙ a ( 1 ) U ˙ a ( 2 ) U ˙ a ( 0 ) ] = j ω L f [ I ˙ a ( 1 ) I ˙ a ( 2 ) I ˙ a ( 0 ) ] + ( 1 ω 2 L f C f ) [ U ˙ sa ( 1 ) U ˙ sa ( 2 ) U ˙ sa ( 0 ) ]
It can be seen from (5) that the three-sequence components are independent of each other, so the differential equations of each sequence in time domain are
u a ( 1 ) = L f ( d i a ( 1 ) d t + C f d 2 u sa ( 1 ) d t 2 ) + u sa ( 1 ) u b ( 1 ) = L f ( d i b ( 1 ) d t + C f d 2 u sb ( 1 ) d t 2 ) + u sb ( 1 ) u c ( 1 ) = L f ( d i c ( 1 ) d t + C f d 2 u sc ( 1 ) d t 2 ) + u sc ( 1 )
u a ( 2 ) = L f ( d i a ( 2 ) d t + C f d 2 u sa ( 2 ) d t 2 ) + u sa ( 2 ) u b ( 2 ) = L f ( d i b ( 2 ) d t + C f d 2 u sb ( 2 ) d t 2 ) + u sb ( 2 ) u c ( 2 ) = L f ( d i c ( 2 ) d t + C f d 2 u sc ( 2 ) d t 2 ) + u sc ( 2 )
u a ( 0 ) = L f ( d i a ( 0 ) d t + C f d 2 u sa ( 0 ) d t 2 ) + u sa ( 0 )
Subscripts (1), (2), and (0) respectively indicate the positive, negative and zero sequence components. Then (6) is the positive sequence equation of the inverter, while (7) is the negative and (8) is the zero. As the zero sequence components of three phases are exactly identical, only the equation of phase A is given.
According to the Kirchhoff’s Current Law, the current i n flowing through the neutral line must satisfy
i n = ( i a + i b + i c ) + C f ( d u sa d t + d u sb d t + d u sc d t ) = 3 ( i a ( 0 ) + C f d u sa ( 0 ) d t )
So, the fourth equation in (1) can be written as
u n = 3 L n ( d i a ( 0 ) d t + C f d 2 u sa ( 0 ) d t 2 )
From (9) and (10) we can know that the neutral line current i n only contains the zero sequence component. Therefore, the output voltage of the fourth leg is just the zero sequence voltage.
Through the analysis, it is known that the positive and negative sequence components are only dependent on the voltages and currents of the first three legs, consistent with the mathematical model of the traditional three-phase inverter, but the zero sequence components are different.
According to (8) and (10), the zero sequence equation is
u an ( 0 ) = u a ( 0 ) u n = ( L f + 3 L n ) ( d i a ( 0 ) d t + C f d 2 u sa ( 0 ) d t 2 ) + u sa ( 0 )
where u an ( 0 ) is the zero sequence potential difference between the outlets of the first and fourth legs.
The zero sequence circuit topology described by (11) is shown in Figure 2.
In summary, (6), (7), and (11) can respectively describe the positive, negative, and zero sequence mathematical models of three-phase four leg inverter. To maintain the symmetry of the three-phase voltage in the low-voltage distribution network with unbalanced loads, the negative and zero sequence voltage have to be 0. In other words, the PCC voltage contains only the positive sequence component.

2.2. Control Strategy of Positive and Negative Sequence Components

For the grid-connected distributed generator (DG), the constant power control (PQ control) is widely adopted. According to the instantaneous power theory [23], the average part of instantaneous power, in which form the energy is transferred in the three-phase four-wire system, can be expressed as (12).
p ¯ = 3 V ( 1 ) I ( 1 ) cos ϕ v ( 1 ) ϕ i ( 1 ) ) + 3 V ( 2 ) I ( 2 ) cos ϕ v ( 2 ) ϕ i ( 2 ) ) + 3 V ( 0 ) I ( 0 ) cos ϕ v ( 0 ) ϕ i ( 0 ) ) q ¯ = 3 V ( 1 ) I ( 1 ) sin ϕ v ( 1 ) ϕ i ( 1 ) ) 3 V ( 2 ) I ( 2 ) sin ϕ v ( 2 ) ϕ i ( 2 ) )
where p ¯ , q ¯ represent the average parts of active power and reactive power respectively, and the pairs of V ( 1 ) and I ( 1 ) , V ( 2 ) and I ( 2 ) , as well as V ( 0 ) and I ( 0 ) , represent the effective voltage and current values of positive, negative and zero sequences separately, with their corresponding phases being ϕ v ( 1 ) , ϕ i ( 1 ) , ϕ v ( 2 ) , ϕ i ( 2 ) , ϕ v ( 0 ) , and ϕ i ( 0 ) .
Assuming the negative and zero sequence voltages are 0 to achieve symmetry, p ¯ and q ¯ in (12) are determined only by the positive sequence components. Therefore, the positive sequence components can be regulated with the PQ control method as a way to control the power flow.
Through the Park transformation, both the positive sequence and the negative sequence components acquire the DC form in d-q coordinate system, and thus can be easily controlled by the PI controller without the static error [24]. Here we show the transforming process:
The Park transformation matrix is
C 3 s / 2 r = 2 3 [   cos θ   cos ( θ 2 π 3 )   cos ( θ + 2 π 3 ) sin θ sin ( θ 2 π 3 ) sin ( θ + 2 π 3 ) ]
For the positive sequence,
[ u sd ( 1 ) u sq ( 1 ) ] = C 3 s / 2 r [ u sa ( 1 ) u sb ( 1 ) u sc ( 1 ) ] = C 3 s / 2 r [ U ( 1 ) m sin ( ω t + α 1 ) U ( 1 ) m sin ( ω t + α 1 2 π / 3 ) U ( 1 ) m sin ( ω t + α 1 + 2 π / 3 ) ] = U ( 1 ) m [ sin ( ω t + α 1 θ ) cos ( ω t + α 1 θ ) ]
where u sd ( 1 ) and u sq ( 1 ) are the d-axis and q-axis components of the PCC positive voltage, U ( 1 ) m is its amplitude and ω is the system angular frequency which is obtained by the phase-locked loop (PLL) in real time, and α 1 is the initial phase of u sa ( 1 ) . To make u sd ( 1 ) and u sq ( 1 ) take the DC form, and to enable u sq ( 1 ) = 0 , the following condition has to be met
θ = ω t + α 1 π / 2
For the negative sequence, the negative sequence current is used as an example. Let θ = θ = ( ω t + α 1 π / 2 ) , and get C 3 s / 2 r by replacing the θ in C 3 s / 2 r with θ . Then,
[ i d ( 2 ) i q ( 2 ) ] = C 3 s / 2 r [ i a ( 2 ) i b ( 2 ) i c ( 2 ) ] = C 3 s / 2 r [ I ( 2 ) m sin ( ω t + φ 2 ) I ( 2 ) m sin ( ω t + φ 2 + 2 π / 3 ) I ( 2 ) m sin ( ω t + φ 2 2 π / 3 ) ] = I ( 2 ) m [ cos ( φ 2 α 1 ) sin ( φ 2 α 1 ) ]
where I ( 2 ) m and φ 2 are the amplitude and initial phase of i a ( 2 ) .
Through the transformations (14) and (16), the PI controller is introduced to the d-q frame. Because the harmonics in the primary currents and voltages will bring problems for PI controller, low pass filters should be applied to the decomposition process of sequence components.
The inner-loop and outer-loop controllers of the positive sequence components are expressed as (17) and (18), respectively.
u d ( 1 ) _ ref = ( K iP ( 1 ) + K iI ( 1 ) s ) ( i d ( 1 ) _ ref i d ( 1 ) ) ω L f i q ( 1 ) + u sd ( 1 ) u q ( 1 ) _ ref = ( K iP ( 1 ) + K iI ( 1 ) s ) ( i q ( 1 ) _ ref i q ( 1 ) ) + ω L f i d ( 1 ) + u sq ( 1 )
i d ( 1 ) _ ref = ( K oP ( 1 ) + K oI ( 1 ) s ) ( P ref P ) i q ( 1 ) _ ref = ( K oP ( 1 ) + K oI ( 1 ) s ) ( Q ref Q )
where i d ( 1 ) and i q ( 1 ) are the d-axis and q-axis components of the positive sequence current; K iP ( 1 ) and K oP ( 1 ) the proportionality coefficients of the inner and outer loops; K iI ( 1 ) and K oI ( 1 ) the integral coefficients of the inner and outer loops; i d ( 1 ) _ ref and i q ( 1 ) _ ref the reference currents; P ref and Q ref the reference powers; and, u d ( 1 ) _ ref and u q ( 1 ) _ ref the modulation signals.
The outer loop is used to achieve power control, while the inner loop speeds up the dynamic response.
For the negative sequence components, as they are converted to the DC form, they can also be regulated by the same control method as the positive sequence components in (17) and (18), with components P and Q replaced by the negative voltages for the outer loop control [25]:
i d ( 2 ) _ ref = ( K oP ( 2 ) + K oI ( 2 ) s ) u sd ( 2 ) i q ( 2 ) _ ref = ( K oP ( 2 ) + K oI ( 2 ) s ) u sq ( 2 )
The positive and negative sequence control strategies are illustrated in Figure 3.

2.3. Control Strategy of Zero Sequence Component

In (11), the zero sequence model of the three-phase four-leg inverter can be regarded as a single-phase inverter, so it can be controlled by a similar strategy to that of a single-phase inverter.
Due to the static error in controlling an AC system, the PI controller fails when high precision is required, and has to give way to the proportional resonant (PR) controller, which has no static error. However, this is only in principle, for it is difficult to build an ideal PR controller and its regulating performance is subject to the fluctuations of the grid frequency [26]. Another way to avoid this disadvantage is trying to convert the single-phase AC signal to DC form to make it acceptable for the application of the PI controller.
For a single-phase voltage or current, with a delay of a quarter of the period, a new signal is created, whose vector is perpendicular to that of the former [27]. The two signals can be converted into DC components through the αβ-dq transformation. Take the zero sequence current i a ( 0 ) for example, whose expression is
i a ( 0 ) = I ( 0 ) m sin ( ω t + φ 0 )
In the αβ static coordinate system, let
i α = i a ( 0 ) = I ( 0 ) m sin ( ω t + φ 0 ) i β = I ( 0 ) m sin ( ω t + φ 0 90 ) = I ( 0 ) m cos ( ω t + φ 0 )
After the αβ-dq transformation, two DC components i d ( 0 ) and i q ( 0 ) are obtained as
[ i d ( 0 ) i q ( 0 ) ] = [ cos θ sin θ sin θ cos θ ] [ i α i β ] = I ( 0 ) m [ sin ( ω t + φ 0 θ ) cos ( ω t + φ 0 θ ) ] = I ( 0 ) m [ cos ( φ 0 α 1 ) sin ( φ 0 α 1 ) ]
where θ = ω t + α 1 π / 2 .
Figure 4 illustrates the transformation process.
Through the transformation, the static error of the PI controller can be eliminated. The control method is similar to that of negative sequence components, only with L f replaced by ( L f + 3 L n ) and each voltage and current replaced by its zero sequence counterpart in (17) and (19).
Finally, the control signals of the three sequences should be superimposed and modulated in the way shown in Figure 5 to achieve the control on the three-phase four-leg inverter. In this paper, sine-wave pulse-width modulation (SPWM) is chosen as the modulation strategy.

3. Current-Limiting Scheme Embedded in Control Strategy

To maintain the PCC voltage symmetry, each phase current output by the three-phase four-leg inverter is usually unequal in magnitude with others. The method of the modulus limit on current reference value is not applicable to limiting the output current and protect the inverter. In addition, setting limit values for each sequence independently may cause the waste of the inverter capacity. It is necessary to find a method which can limit the phase currents and make full use of the capacity of the inverter.
According to the control strategy above, the controller of each sequence is independent with others. The positive sequence current is determined by the target of the output power. It takes on the role of outputting active and reactive power. The negative and zero sequence currents depend on the load condition, and they play a common role of balancing the PCC voltage. Thus, the negative and zero sequence currents can be put into one block to be discussed, and for convenience, their sum I ˙ k ( 2 , 0 ) can be called as the balance regulating current.
I ˙ k ( 2 , 0 ) = I ˙ k ( 2 ) + I ˙ ( 0 )   ,    ( k = a , b , c )
where I ˙ k ( 2 ) is the negative sequence current of phase k, and as the zero sequence components of three phases are exactly identical, the zero sequence current is written as I ˙ ( 0 ) .
Then, the currents are divided into two categories: the positive sequence current is for power transmission, and the balance regulating current, which is the sum of the negative and zero sequence currents, is for voltage balance.

3.1. Output Characteristic of Each Sequence

When the direction of the AC voltage vector U ( 1 ) is selected as that of the d-axis in the synchronous rotating coordinate system, the output power and positive sequence current of the DG have such relationships [24]
{ P = 1.5 u sd ( 1 ) i d ( 1 ) Q = 1.5 u sd ( 1 ) i q ( 1 )
where P and Q are the active power and reactive power output by the inverter. Since the Park transformation will not change the amplitude, u sd ( 1 ) has the same amplitude with U ( 1 ) .
Therefore, the d-axis and q-axis components of the positive sequence current can be obtained as
{ i d ( 1 ) = 2 3 P u sd ( 1 ) = 2 3 P | U ( 1 ) | i q ( 1 ) = 2 3 Q u sd ( 1 ) = 2 3 Q | U ( 1 ) |
According to Figure 6, the current vector I ( 1 ) lags behind the voltage vector U ( 1 ) by an angle Δ θ . Accordingly, each phase current lags behind the corresponding phase voltage by Δ θ in abc frame. According to (14), the amplitude of each phase current is equal with that of I ( 1 ) . The A phase current phasor can be expressed as
I ˙ a ( 1 ) = i d ( 1 ) 2 + i q ( 1 ) 2 ( θ 0 + Δ θ )
where θ 0 = arg U ˙ sa ( 1 ) and Δ θ = arctan ( i q ( 1 ) / i d ( 1 ) ) .
In addition, the control system of the inverter is generally equipped with a modulus limiter, which can limit the amplitude of the output current within a certain value I ( 1 ) max . Therefore, according to (25) and (26), the positive sequence current is
I ˙ a ( 1 ) = 2 3 P ref 2 + Q ref 2 | U ( 1 ) | ( θ 0 + Δ θ ) ,     2 3 P ref 2 + Q ref 2 | U ( 1 ) | < I ( 1 ) max
When the voltage is very small, which means the I ˙ a ( 1 ) will be rather large, I ˙ a ( 1 ) should be limited at the maximum value I ( 1 ) max . The modulus limiter can limit the amplitude of the current without changing its phase [25]. Then, the positive sequence current can be written as
I ˙ a ( 1 ) = I ( 1 ) max ( θ 0 + Δ θ ) ,     2 3 P ref 2 + Q ref 2 | U ( 1 ) | I ( 1 ) max
For the negative and zero sequence currents, which are introduced to maintain voltage symmetry, they are determined by loads, and only the electrical states of the negative and zero sequence components are known
U ˙ sa ( 2 ) = U ˙ s ( 0 ) = 0 ,    | I ˙ k ( 2 , 0 ) | < I ( 2 , 0 ) max   ( k = a , b , c )
where the zero sequence voltage of PCC is written as U ˙ s ( 0 ) for that of each phase is identical; U ˙ sa ( 2 ) is the A phase negative voltage and I ( 2 , 0 ) max is the amplitude limit of the balance regulating current I ˙ k ( 2 , 0 ) .
To keep the voltages of both the negative sequence and zero sequence being zero, the amplitude of I ˙ k ( 2 , 0 ) cannot exceed I ( 2 , 0 ) max . It is noted that if the amplitude of I ˙ k ( 2 , 0 ) for any phase has the trend of surpassing I ( 2 , 0 ) max , it will be limited at this maximum, but in this case, the voltages may not be maintained at 0.
max | I ˙ k ( 2 , 0 ) | = I ( 2 , 0 ) max    ( k = a , b , c )
Thus I ( 2 , 0 ) max can be seen as an indicator of the capability of the inverter to maintain the voltage symmetry.

3.2. Current Modulus Limiters of Each Sequence

The equations in (28) and (30) can be satisfied by applying a modulus limiter to each of the outer loops.
For (28), the three-phase current is symmetrical, so the model of the modulus limiter in Figure 7 can be used [24].
However, for (30), the balance regulating current I ˙ k ( 2 , 0 ) of each phase is unique and thus should be calculated separately.
For the negative and zero sequence currents, after the Park transformation, the d-axis and q-axis components are shown as (16) and (22) respectively.
Then make the phasor diagram of the negative and zero sequence currents as Figure 8. By selecting the direction of U ˙ sa ( 1 ) as that of the x-axis, a Rectangular coordinate system is built, where the x-axis and y-axis components of each phase can be obtained.
In terms of the negative sequence, the components of the three phases are calculated according to the Figure 8 and Park transformation results (16) and (22).
For phase A,
I a ( 2 ) x = I ( 2 ) m cos ( φ 2 α 1 ) = i d ( 2 ) I a ( 2 ) y = I ( 2 ) m sin ( φ 2 α 1 ) = i q ( 2 )
For phase B,
I b ( 2 ) x = I ( 2 ) m cos ( φ 2 α 1 + 2 π 3 ) = 1 2 i d ( 2 ) + 3 2 i q ( 2 ) I b ( 2 ) y = I ( 2 ) m sin ( φ 2 α 1 + 2 π 3 ) = 3 2 i d ( 2 ) + 1 2 i q ( 2 )
For phase C,
I c ( 2 ) x = I ( 2 ) m cos ( φ 2 α 1 2 π 3 ) = 1 2 i d ( 2 ) 3 2 i q ( 2 ) I c ( 2 ) y = I ( 2 ) m sin ( φ 2 α 1 2 π 3 ) = 3 2 i d ( 2 ) + 1 2 i q ( 2 )
In (31), (32), and (33), I k ( 2 ) x and I k ( 2 ) y (k = a, b, c) are the x-axis and y-axis components of the negative sequence current of phase k, and φ 2 the phase angle of I ˙ a ( 2 ) .
For the zero sequence current,
I ( 0 ) x = I ( 0 ) m cos ( φ 0 α 1 ) = i d ( 0 ) I ( 0 ) y = I ( 0 ) m sin ( φ 0 α 1 ) = i q ( 0 )
Therefore, the balance regulating current I ˙ k ( 2 , 0 ) can be calculated through (35).
I k ( 2 , 0 ) m = ( I k ( 2 ) x + I ( 0 ) x ) 2 + ( I k ( 2 ) y + I ( 0 ) y ) 2 tan φ k ( 2 , 0 ) = I k ( 2 ) y + I ( 0 ) y I k ( 2 ) x + I ( 0 ) x
where I k ( 2 , 0 ) m is the amplitude of I ˙ k ( 2 , 0 ) ; φ k ( 2 , 0 ) the included angle between I ˙ k ( 2 , 0 ) and the x-axis; I ( 0 ) x and I ( 0 ) y the x-axis and y-axis components of the zero sequence current.
The modulus limit for I ˙ k ( 2 , 0 ) can be achieved by the limiter in Figure 9.
In Figure 9, φ k ( 2 ) is the included angle between I ˙ k ( 2 ) and the x-axis, and φ ( 0 ) is that between I ˙ ( 0 ) and the x-axis, which can be deduced by
tan φ k ( 2 ) = I k ( 2 ) y / I k ( 2 ) x tan φ ( 0 ) = I ( 0 ) y / I ( 0 ) x
To limit the amplitude of the balance regulating current without changing the phase angle, the redistribution of the x-axis and y-axis components can be achieved by
{ I k ( 2 ) y / I k ( 2 ) x = tan φ k ( 2 ) I ( 0 ) y / I ( 0 ) x = tan φ ( 0 ) I k ( 2 ) x + I ( 0 ) x = I k ( 2 , 0 ) m cos φ k ( 2 , 0 ) I k ( 2 ) y + I ( 0 ) y = I k ( 2 , 0 ) m sin φ k ( 2 , 0 )
It is defined that
β k = I k ( 2 , 0 ) m cos φ k ( 2 , 0 ) tan φ ( 0 ) tan φ k ( 2 )
The negative and zero sequence components output by the modulus limiter are
{ I k ( 2 ) x = β k ( tan φ ( 0 ) tan φ k ( 2 , 0 ) ) I k ( 2 ) y = β k ( tan φ ( 0 ) tan φ k ( 2 , 0 ) ) tan φ k ( 2 ) I ( 0 ) x = β k ( tan φ k ( 2 , 0 ) tan φ k ( 2 ) ) I ( 0 ) y = β k ( tan φ k ( 2 , 0 ) tan φ k ( 2 ) ) tan φ ( 0 )
It is noted that (39) needs to be calculated for each of the three phases separately, and the corresponding i d ( 2 ) , i q ( 2 ) , i d ( 0 ) and i q ( 0 ) for each phase can be obtained through the inverse transformation of (31)–(33). The minimum of them will be used as the new references to ensure that each phase current does not exceed the limit value.

3.3. Combined Current-Limiting Method

The amplitude limit value for the positive sequence current is I ( 1 ) max , and that for the sum of the negative and zero sequence currents is I ( 2 , 0 ) max , but the real constriction for the inverter output current is the maximum phase current which is determined by the current-carrying capacity of the IGBT and the saturation current of the output filter. Therefore, the real current limit should be modified as
{ | I ˙ k ( 1 ) + I ˙ k ( 2 ) + I ˙ ( 0 ) | < I max 3 | I ˙ ( 0 ) | < I max    ( k = a , b , c )
where I max is the amplitude of the maximum phase current the DG can endure. The first condition in (40) should be met by each of the three phases. The second condition can be easily satisfied by using a modulus limiter next to the zero sequence outer loop.
If the priority is given to balancing the voltage over outputting power, the inverter needs to maintain the voltage symmetry as possible as it can. Thus, I ( 2 , 0 ) max should be set as I max , and I ( 1 ) max can be calculated graphically as shown in Figure 10, where the phase A is taken for example.
When P ref and Q ref are known, the phase angle Δ θ is determined. Thus | I ˙ a ( 1 ) | can be calculated with the cosine theorem.
Further, the maximum of the amplitude I k ( 1 ) m (k = a, b, c) can be obtained by solving (41).
{ α = cos ( φ k ( 2 , 0 ) Δ θ k ) I k ( 2 , 0 ) m 2 + I k ( 1 ) max 2 2 α I k ( 2 , 0 ) m I k ( 1 ) max = I max 2
where Δ θ k is the phase angle of the positive sequence current of phase k, and the solutions of (41) are
I k ( 1 ) max = α I k ( 2 , 0 ) m ± ( α 2 1 ) I k ( 2 , 0 ) m 2 + I max 2
As I k ( 2 , 0 ) m I max and α I k ( 2 , 0 ) m ( α 2 1 ) I k ( 2 , 0 ) m 2 + I max 2 < 0 , this solution can be excluded.
Therefore,
I ( 1 ) max = min { I k ( 1 ) max } = min { α I k ( 2 , 0 ) m + ( α 2 1 ) I k ( 2 , 0 ) m 2 + I max 2 } ,   ( k = a , b , c )
Similarly, when outputting power is the first consideration, the limit value should be set by
I ( 1 ) max = I max I ( 2 , 0 ) max = min { α I k ( 1 ) m + ( α 2 1 ) I k ( 1 ) m 2 + I max 2 } ,   ( k = a , b , c )
The scheme above can provide a current-limiting method in the case that the phase currents are not equal with each other in size. It can ensure that the current of any phase would not exceed the limit. Meanwhile, according to the different functions of the inverter, the switch between output power priority and balance voltage priority can be achieved flexibly. Furthermore, the scheme has self-adaptation capability. The limit values can be adjusted with the change of the load so that the capacity of the inverter can be fully utilized.

4. Simulation and Analysis

To verify the effectiveness of the control strategy for the three-phase four-leg inverter and the embedded current-limiting scheme, the simulation models are established in PSCAD/EMTDC, which is shown in Figure 11.
In Figure 11, the system power is equivalent to a 0.4 kV three-phase voltage source E ˙ and an impedance Z s in series. Z s is set as 0.09 + j 0.5   Ω . The feeder line is equivalent to a PI section. The positive sequence impedance of the feeder Z 1 is 0.412 + j 0.0625   Ω and the zero sequence impedance of the feeder Z 0 is 1.648 + j 0.2501   Ω . The parameters of the DG model in Figure 11 are listed in Table 1.
The case studies are separated into two parts. The first part is done to verify the voltage-balancing capability of the control strategy, and the second part is to verify the current-limiting scheme embedded in the control strategy.

4.1. Verification of the Voltage-Balancing Capability of the Control Strategy

Voltage unbalance of the distribution network is mainly caused by load asymmetry, so the impedance change of the load is applied to verify the voltage-balancing capability of the control strategy.
Firstly, a tunable three-phase resistor R is used as the load in simulation. At the very beginning of the simulation, R a , R b , and R c are all set as 10 Ω. At 0.52 s in simulation, R a increases to 20 Ω and R c decreases to 5 Ω. The voltage and current waveforms can be obtained through simulation.
In Figure 12a, there is a minor disturbance to the three-phase voltage when the resistances of the load changes at 0.52 s, and the voltage regains symmetry quickly afterwards. By contrast, in Figure 12b, the three-phase current becomes asymmetric after the load change. In Figure 12c,d, where the voltage and current are decomposed into positive, negative, and zero sequence components, the negative and zero sequence voltages disappear right after its occurrence at 0.52 s, while the corresponding currents have been existing ever since this moment. This is an indication of the fast response of the control system.
Besides the simulation with the resistive loads, simulations with inductive loads and resistively-inductive loads are also carried out. At the very beginning of the simulation, the inductive loads L a , L b , and L c are all set as 30 mH. At 0.52 s, L a grows to 60 mH and L c falls to 15 mH. The output voltage and current performances in this case are shown in Figure 13a. The three phase resistances of the resistively-inductive loads R a , R b , and R c are all set as 10 Ω while the inductance L a , L b , and L c are set as 10 mH. At 0.52 s in simulation, R a grows to 20 Ω, L a grows to 20 mH, R c falls to 5 Ω, and L c falls to 5 mH. The simulation results of output voltages and currents are presented in Figure 13b.
As is shown in Figure 13, when the inductive and resistively-inductive loads change, the voltages in both cases can transition to three-phase symmetrical conditions fast. The transition period with inductive loads is slightly longer than that with resistively-inductive loads, but finally both of the voltages can get symmetrical within 0.06 s.
From the simulation results, it is concluded that the three-phase four-leg inverter with this control strategy can ensure the output voltage balance.

4.2. Verification of the Current-Limiting Scheme

The current-limiting capability of the scheme has been tested in two cases—where a large reference power is given and where a severely unbalanced load is applied. For the model in Figure 11, it is assumed that R a is set as 10 Ω, R b is set as 5 Ω, and R c is set as 2 Ω. So the load is unbalanced. The active power reference is set as 40 kW and the reactive power is 0. The amplitude limit of the phase current is set as 0.2 kA. The current-limiting scheme is designed with the priority of voltage balance.
Case (1): The case is used to test the current-limiting capability while the current increase is caused by the ascent of the output reference of inverter. In this case, the active power reference is changed to 70 kW at 0.5 s, the external load condition keeps constant. The simulation results are shown in Figure 14.
In Figure 14a, the amplitude of the sum of negative and zero sequence currents for each phase is presented. When the active power reference changes to 70 kW, each of them increases slightly, but they are still under the limit of 0.2 kA. Therefore, the PCC voltage in Figure 14d is still three-phase symmetrical. Accordingly, in Figure 14b, the limit value of the positive sequence current has a slight drop. To output more power, the positive sequence current rises before it is capped at the limit value. Therefore, in Figure 14c, the active power output by the inverter fails to reach the reference, but finally stops at around 58 kW. In a word, the output power is limited to ensure the current of each phase will not go beyond the set limit. According to Figure 14e, the current of phase C is the largest whose amplitude is limited at 0.2 kA.
In case (1), the three phase currents are all no more than the limit and the three phase voltages are symmetrical throughout. The increase of the output power reference only has a minor influence on the negative and zero sequence currents through the slight variation of the voltage. Therefore, the voltage-balancing capability can be ensured by the embedded current-limiting scheme with different output reference.
Case (2): The case is used to test the current-limiting capability while the current increase is caused by the deterioration of the external load asymmetry. At 0.5 s, the resistance of phase C changes from 2 to 0.5 Ω. The unbalanced load is introduced to show the adjusting process and performance of the currents while the voltage unbalance rises beyond the capacity of control strategy under the constraint of the current-limiting scheme. The simulation results are shown as Figure 15.
In Figure 15a, the amplitude of the sum of the negative and zero sequence currents in phase C has reached the limit. The inverter is supposed to maintain voltage symmetry to its greatest capacity yet fails to achieve the goal due to the severe asymmetry of the load. So in Figure 15d, the PCC voltage cannot keep balanced after 0.5 s. Also, in Figure 15b, the limit value of the positive sequence current drops to 0, which causes the positive sequence active power to fall to 0 in Figure 15c. According to Figure 15d, it can be seen that the largest phase current appears in phase C, and it has an impulse to exceed the amplitude limit of 0.2 kA, but finally stabilizes under the limit.
In case (2), with the asymmetry increasing, the inverter needs to output larger negative and zero sequence currents to maintain voltage symmetry, which may cause the currents to exceed the limit. As the priority of the current-limiting scheme is voltage balance, the negative and zero sequence currents are preferentially output. So the positive sequence current drops to 0 to give way to the negative and zero sequence currents in this case. The voltage finally becomes asymmetrical because the demand of the negative and zero sequence currents to maintain the voltage symmetry is beyond the limit of the current-limiting scheme.

5. Conclusions

In the paper, a novel control strategy including an adaptive current-limiting scheme for grid-connected three-phase four-leg inverter is proposed. It has the capability to dynamically adjust the current limit of each sequence while keeping the output voltage symmetrical. The main features are listed as follows:
  • The independent control schemes for the positive, negative, and zero sequence in synchronous rotating frame are realized based on the symmetrical component method. All three sequence components are transformed into DC to make the PI controller applicative.
  • Through the coordinate transformation, all the DC components of the three sequence currents in d-q frames are unified into one coordinate system. The current limiter is designed by calculating the current reference of each sequence in this unified coordinate system.
  • The current-limiting scheme is adaptive to the output power reference and the loads asymmetry condition. It can set the current limit of each sequence reasonably while giving full play to the output capability of the inverter.

Acknowledgments

This work was supported in part by the National Natural Science Foundation of China under Grant 51677125, by the Specialized Research Fund for the Doctoral Program of Higher Education for New Teacher under Grant 20120032120085 and by National High Technology Research and Development (863 program) under Grant 2015AA050102.

Author Contributions

Botong Li put forward the research direction, organized the research activities, provided theory guidance, and completed the revision of the article. Jianfei Jia completed the principle analysis and the method design, provided the results of the simulation, and drafted the article. Valuable comments on the first draft were received from Shimin Xue and Botong Li. All three were involved in revising the paper.

Conflicts of Interest

The authors declare no conflict of interest.

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Figure 1. Topological structure of three-phase four-leg inverter with LC filter.
Figure 1. Topological structure of three-phase four-leg inverter with LC filter.
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Figure 2. Equivalent circuit topology of zero sequence.
Figure 2. Equivalent circuit topology of zero sequence.
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Figure 3. Control strategy of the three-phase four-leg inverter: (a) Positive sequence control strategy; (b) Negative sequence control strategy.
Figure 3. Control strategy of the three-phase four-leg inverter: (a) Positive sequence control strategy; (b) Negative sequence control strategy.
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Figure 4. The transformation process of zero sequence.
Figure 4. The transformation process of zero sequence.
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Figure 5. Superimposition of control signals.
Figure 5. Superimposition of control signals.
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Figure 6. Positive sequence current in d-q frame.
Figure 6. Positive sequence current in d-q frame.
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Figure 7. The positive sequence modulus limiter.
Figure 7. The positive sequence modulus limiter.
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Figure 8. Phasor diagram of the negative sequence and zero sequence currents in x-y frame.
Figure 8. Phasor diagram of the negative sequence and zero sequence currents in x-y frame.
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Figure 9. The negative and zero sequence modulus limiter.
Figure 9. The negative and zero sequence modulus limiter.
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Figure 10. Method to get the maximum of the positive sequence current.
Figure 10. Method to get the maximum of the positive sequence current.
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Figure 11. Distribution network with a three-phase four-leg inverter-based DG.
Figure 11. Distribution network with a three-phase four-leg inverter-based DG.
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Figure 12. Waveforms of the PCC voltage and output current: (a) Three-phase voltage; (b) Three-phase current; (c) The positive, negative, and zero sequence voltages; (d) The positive, negative, and zero sequence currents.
Figure 12. Waveforms of the PCC voltage and output current: (a) Three-phase voltage; (b) Three-phase current; (c) The positive, negative, and zero sequence voltages; (d) The positive, negative, and zero sequence currents.
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Figure 13. Waveforms of voltages and currents with inductive and resistively-inductive loads: (a) The inductive loads change; (b) The resistively-inductive loads change.
Figure 13. Waveforms of voltages and currents with inductive and resistively-inductive loads: (a) The inductive loads change; (b) The resistively-inductive loads change.
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Figure 14. Simulation results of the case with the power reference changing: (a) The amplitudes of the balance regulating currents; (b) The positive sequence current and its amplitude limit; (c) The active power and reactive power outputted by the inverter; (d) The three-phase PCC voltage; (e) The three-phase output current.
Figure 14. Simulation results of the case with the power reference changing: (a) The amplitudes of the balance regulating currents; (b) The positive sequence current and its amplitude limit; (c) The active power and reactive power outputted by the inverter; (d) The three-phase PCC voltage; (e) The three-phase output current.
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Figure 15. Simulation results in the case with load changing: (a) The amplitudes of the balance regulating currents; (b) The positive sequence current and its amplitude limit; (c) The active power and reactive power output by the inverter; (d) The three-phase PCC voltage; (e) The three-phase output current.
Figure 15. Simulation results in the case with load changing: (a) The amplitudes of the balance regulating currents; (b) The positive sequence current and its amplitude limit; (c) The active power and reactive power output by the inverter; (d) The three-phase PCC voltage; (e) The three-phase output current.
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Table 1. Parameters of the DG.
Table 1. Parameters of the DG.
System ParametersValuesPI ParametersValues
DC voltage0.8 kV K iP ( 1 ) / K iI ( 1 ) 0.1/0.01
system voltage0.4 kV K oP ( 1 ) / K oI ( 1 ) 3.0/0.001
rated power P/Q50 kW/0 kVar K iP ( 2 ) / K iI ( 2 ) 0.25/0.015
filter inductance4 mH K oP ( 2 ) / K oI ( 2 ) 2.5/0.002
filter capacitance100 μF K iP ( 0 ) / K iI ( 0 ) 2.0/0.12
L n 1.5 mH K oP ( 0 ) / K oI ( 0 ) 5.0/0.005

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MDPI and ACS Style

Li, B.; Jia, J.; Xue, S. Study on the Current-Limiting-Capable Control Strategy for Grid-Connected Three-Phase Four-Leg Inverter in Low-Voltage Network. Energies 2016, 9, 726. https://doi.org/10.3390/en9090726

AMA Style

Li B, Jia J, Xue S. Study on the Current-Limiting-Capable Control Strategy for Grid-Connected Three-Phase Four-Leg Inverter in Low-Voltage Network. Energies. 2016; 9(9):726. https://doi.org/10.3390/en9090726

Chicago/Turabian Style

Li, Botong, Jianfei Jia, and Shimin Xue. 2016. "Study on the Current-Limiting-Capable Control Strategy for Grid-Connected Three-Phase Four-Leg Inverter in Low-Voltage Network" Energies 9, no. 9: 726. https://doi.org/10.3390/en9090726

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