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Energies 2014, 7(2), 1003-1026; doi:10.3390/en7021003
Published: 24 February 2014
Abstract
: The presence of an unbalanced voltage at the point of common coupling (PCC) results in the appearance of a negative sequence current component that deteriorates the control performance. Static synchronous compensators (STATCOMs) are well-known to be a power application capable of carrying out the regulation of the PCC voltage in distribution lines that can suffer from grid disturbances. This article proposes a novel PCC voltage controller in synchronous reference frame to compensate an unbalanced PCC voltage by means of a STATCOM, allowing an independent control of both positive and negative voltage sequences. Several works have been proposed in this line but they were not able to compensate an unbalance in the PCC voltage. Furthermore, this controller includes aspects as antiwindup and droop control to improve the control system performance.1. Introduction
The ongoing large-scale integration of wind energy into the power system demands the continuous revision of grid codes and power quality standards in order to fulfill restrictive constraints. Furthermore, most host utilities also require that wind farms must tolerate system disturbances [1]. These requirements become of paramount importance in remote locations where the feeders are long and operated at a medium voltage level, providing a weak grid connection. The main feature of this type of connection is the increased voltage regulation sensitivity to changes in load [2]. Thus, the system's ability to regulate voltage at the point of common coupling (PCC) to the electrical system is a key factor for the successful operation of the wind farm [3], even in the face of voltage flicker caused by wind gusts or post fault electromechanical swings in the power grid [1].
Nowadays, there are grid operators that allow providing unbalanced currents so that the power at the PCC remains constant. This is very useful in weak grids because it allows connecting all loads to a balanced PCC voltage, which is especially important for sensitive loads that could disconnect if the AC voltage does not meet restrictive voltage standards.
This task can be accomplished by means of a STATCOM, which is a Voltage-Source Converter (VSC) system whose prime function is to exchange reactive power with the host AC system [4] and control the power factor. In a distribution system, it is mainly used for voltage regulation [5]. This has a major application in weak grids, whose significant grid impedance may lead to large PCC voltage variations compared to that of strong grids. The general system under investigation is shown in Figure 1. Several loads and wind farms are connected to the same PCC along with a STATCOM, which is in charge of the PCC voltage regulation. In this figure, L and R are the grid filter parameters, L_{g} and R_{g} are the grid impedance parameters, C_{DC}_{1} and C_{DC}_{2} are the DC-link capacitors and the STATCOM is a three-level neutral point clamped (NPC) converter.
One of the most typical disturbances in power systems is an unbalance in the PCC voltage [6], which is a difference in the magnitude of the phase-to-neutral (or phase-to-phase) voltages of a three-phase system. There is no standardized mathematical expression to quantify the unbalance of a three-phase system. Three definitions of unbalance are reviewed in [7]; one was developed by the National Equipment Manufacturer's Association (NEMA), another was developed by the IEEE and the other is the most common definition used by engineering community (the so-called true definition). The latter expresses the voltage unbalance factor (VUF) in percent as:
It is well-known that any three-phase system can be split into the sum of three balanced systems, namely, positive, negative and zero sequences. A balanced three-phase system will be only composed of a positive sequence system. However, in real power systems several types of disturbances may affect the grid and give rise to the appearance of a negative sequence system in addition to the positive sequence one. Zero sequence systems only appear in three-phase four-wire power systems [8] and this case is not tackled in this article, since a three-phase three-wire power system is considered.
The unbalanced three-phase voltage shown in Figure 2a has a VUF equal to 8.3%, and it has been considered as the ideal grid voltage in the simulations results of Section 6.1. It is composed of the sum of a positive sequence three-phase system with ${U}^{+}=0.9\cdot 400/\sqrt{3}\approx 207.8\text{V}$ (Figure 2b) and a negative sequence three-phase system with ${U}^{-}=0.075\cdot 400/\sqrt{3}\approx 17.3\text{V}$ (Figure 2c). In accordance with IEC 61000-3-13, the maximum VUF during normal operation in transmission systems must not exceed 2%; therefore, the grid voltage of Figure 2a can be used to justify and test the proposed algorithm.
An unbalanced voltage has several negative effects. For instance, it reduces efficiency and can cause failure in induction machines [9]. It also produces negative effects on power electronic converters. The voltage unbalance can impair a Pulse-Width Modulation (PWM) converter system because the input active and reactive power ripples are generated by the cross products of line currents and unbalanced voltages [10]. The grid synchronization algorithm has to be sufficiently fast and accurate to extract the positive and negative voltage sequences precisely, in order to generate the output current references. A PCC voltage controller is needed to cancel these harmful effects while allowing an independent control of positive and negative sequence components.
The article is organized as follows: Section 2 analyzes the PCC voltage equations under unbalanced conditions and provides their corresponding plant models, which are focused in the grid model under a voltage unbalance. Section 3 details the control scheme that has been developed, as well as the design and tuning of the proposed PCC voltage controller. Section 4 addresses the possibility of performing an online adaptation of the DC-link reference voltage to always ensure an optimal modulation index. Section 5 investigates the sampling mode of the PCC voltage when working with an L-filter, which is of paramount importance for the correct operation of the control system in weak grids. Section 6 shows the effectiveness of the novel PCC voltage control through simulation results and, lastly, conclusions are presented in Section 7.
2. Grid Modeling Under Unbalanced Conditions
A VSC can be represented as an ideal AC voltage source (per phase). Therefore, its connection to the grid can be depicted according to the scheme of Figure 3, where L and R are the grid filter parameters, L_{g} and R_{g} are the grid impedance parameters, V is the VSC output voltage, U is the PCC voltage, E is the ideal grid voltage and ι⃗ is the current flowing from the VSC to the grid.
In order to obtain a general model of the grid, valid for both balanced and unbalanced conditions, the scheme of Figure 3 is considered. The grid model is calculated from the voltage equation between the points U (PCC) and E (ideal grid). The grid filter is not taken into account to obtain such model, since PCC voltage variations in an unbalanced system are imposed by the grid impedance and not by the grid filter.
The grid model can be expressed in time domain and in synchronous reference frame (dq-axes) as shown in Equation (2a) for positive sequence (superscript “+”) and Equation (2b) for negative sequence (superscript “−”). In these equations, ω_{1} is the fundamental angular frequency ω_{1} = 2π50 rad/s. Each PCC voltage component is formed by the voltage drop across the grid impedance, a cross-coupling term between axes and the ideal grid voltage:
Each of these voltages is separated into its d and q projections: positive sequence voltages ${u}_{d}^{+}$ and ${u}_{q}^{+}$ are shown in Equation (3a) and (3b), whereas negative sequence voltages ${u}_{d}^{-}$ and ${u}_{q}^{-}$ are shown in Equation (4a) and (4b). These four expressions are steady-state approximations. Grid resistance R_{g} is considered to be very small, so that its contribution to the PCC voltage can be neglected (compared to the voltage drop across the grid filter inductance). Furthermore, the derivative of a constant signal (such as ι⃗ in dq-axes) is zero. Note that ${u}_{d}^{+}$ is equal to zero Equation (3a) because a Phase-Locked Loop (PLL) is used to synchronize the positive sequence PCC voltage vector (u⃗^{+}) with the q-axis, hence the projection of u⃗^{+} on this axis is equal to its amplitude $\left({u}_{q}^{+}\equiv \left|{\overrightarrow{u}}^{+}\right|\right)$:
From the above equations it is straightforward to observe that each PCC voltage component is related to only one current component: ${u}_{q}^{+}$ and ${i}_{d}^{+}$; ${u}_{d}^{-}$ and ${i}_{q}^{-}$; and ${u}_{q}^{-}$ and ${i}_{d}^{-}$. The current component ${i}_{q}^{+}$ is related to the control of the DC-link voltage and does not influence the PCC voltage level directly. Thus, three independent voltage controllers are needed for ${u}_{q}^{+}$, ${u}_{d}^{-}$ and ${u}_{q}^{-}$. Since they are constant voltages, a Proportional-Integral (PI) controller is enough to ensure zero steady-state error. The plant models needed for the design of these controllers are shown in Figure 4 for each component, based on Equation (3b) and (4).
3. Control Scheme
The block diagram of the proposed control scheme is shown in Figure 5, which is composed of the following parts:
DC-link voltage control
Reactive power control
PCC voltage control & calculation of ${i}_{q}^{+\ast}$
Calculation of ${i}_{dq}^{+\ast}$ and ${i}_{dq}^{-\ast}$
Current control
Modulation strategy
In first place, the active power reference P* is set by the “DC-link voltage control” block. Its output constitutes an input for two possible blocks, namely, “Calculation of ${i}_{dq}^{+\ast}$ and ${i}_{dq}^{-\ast}$” block or “PCC voltage control & calculation of ${i}_{q}^{+\ast}$” block. Depending on the application, one block or another will be chosen. The output of both blocks is the dq-axes reference current (positive and negative sequence, ${i}_{dq}^{+\ast}$ and ${i}_{dq}^{-\ast}$). The following stage is the dq to αβ transformation plus the calculation of ${i}_{\alpha \beta}^{\ast}$. Finally, the low level control is performed by the “Current control” block and the modulation strategy.
3.1. DC-link Voltage Control
The DC-link voltage controller is usually based on a PI controller along with an antiwindup mechanism. However, this scheme may not be sufficient in the case of weak grids. Due to the compensation of the negative sequence voltage at the PCC, an oscillation of frequency 2ω_{1} appears in u_{DC}. If u_{DC} is not filtered, this oscillation propagates through the control system, appearing in P* and, therefore, in the reference currents. The oscillation of frequency 2ω_{1} in dq-axes is transformed into an oscillation of frequency 3ω_{1} in the abc-axes.
In short, if u_{DC} is not filtered, the PCC currents will be affected by the appearance of a 3rd order harmonic (this being no zero-sequence harmonic). To eliminate this harmonic, the 2nd order oscillation is removed from the measured u_{DC} by means of a band-pass filter centered at ω_{0} = 2ω_{1}. This filter is implemented with a Second Order Generalized Integrator for Quadrature Signal Generation (SOGI-QSG) [11], using the output in phase with the input since its transfer function behaves as a band-pass filter centered at ω_{0}. This way, the dynamics of the mean value of the DC-link voltage is not altered.
The block diagram of the DC-link voltage controller is shown in Figure 6, where k_{px} is the proportional gain, k_{ix} is the integral gain and k_{awx} is the antiwindup gain. The DC-link model based on the energy stored in the capacitor has been used [12]. As mentioned before, the basis of the DC-link voltage control is a PI controller and its parameters are tuned without taking into account the inner current controller. To do so, the Zero-Order Hold (ZOH) method has been applied to the plant to obtain its discrete time version, where C_{DC} = (C_{DC}_{1}·C_{DC}_{2})/(C_{DC}_{1}+C_{DC}_{2}):
The PI controller can be expressed in pole-zero form as:
3.2. Reactive Power Control
This is a controller associated to variables that modify the reactive power at the PCC. In this case, this block specifies the reactive power reference Q*, which is an output to the block “Calculation of ${i}_{dq}^{+\ast}$ & ${i}_{dq}^{-\ast}$”. Another variable that could be used to modify the reactive power at the PCC is the power factor.
3.3. Calculation of ${i}_{dq}^{+\ast}$ and ${i}_{dq}^{-\ast}$
This controller is regulated by the equation system in Equation (10). It relates active power, reactive power, PCC voltage and current in dq-axes and it is usually employed in active and reactive power control, as well as in power factor control. Active and reactive powers are divided into three parts: average power (P and Q), oscillating power with cosine terms [P_{2ω(}_{c}_{)} and Q_{2ω(}_{c}_{)}] and oscillating power with sine terms [P_{2ω(}_{s}_{)} and Q_{2ω(}_{s}_{)}]. If grid conditions are balanced, these four oscillating powers are zero and there are only positive sequence voltages and currents. Multiplying by the inverse matrix, the corresponding expressions for the calculation of the reference currents are obtained ( ${i}_{dq}^{+\ast}$ and ${i}_{dq}^{-\ast}$). To do so, P_{2ω(}_{c}_{)} and P_{2ω(}_{s}_{)} are set to zero to compensate the unbalance caused by negative sequence voltage and Q_{2ω(}_{c}_{)} and Q_{2ω(}_{s}_{)} are not controlled, therefore their corresponding rows are eliminated from Equation (10). Trying to control these oscillating reactive powers only deteriorates the control performance, therefore they are allowed to run freely:
3.4. PCC Voltage Control
The block diagram of the PCC voltage controller is shown in Figure 7 and it is implemented in dq-axes. This stage is formed by three “individual voltage controllers” in parallel, whose outputs are ${i}_{d}^{+\ast}$, ${i}_{d}^{-\ast}$, and ${i}_{q}^{-\ast}$, plus the calculation of ${i}_{d}^{+\ast}$ by means of Equation (11). This equation is obtained from Equation (10). The minus sign that goes with ${u}_{q}^{+}$ is due to the current direction. These four outputs are the references for the current controller. In this figure, ε represents the error signal and the subscript “lim” stands for “limited”. The reference voltages ${u}_{d}^{-\ast}$ and ${u}_{q}^{-\ast}$ are set to zero in order to eliminate the PCC voltage negative sequence, whereas the reference voltage ${u}_{q}^{+\ast}$ should be equal to the PCC fundamental voltage.
The inner structure of each “individual voltage controller” is depicted in Figure 8. As mentioned, it is mainly formed by a PI controller with a forward Euler integrator. The constant δ is 1 for the voltage controllers of ${u}_{q}^{+}$ and ${u}_{d}^{-}$, and -1 for the voltage controller of ${u}_{q}^{-}$ due to the minus sign in Equation (4b). It is a first order system and, considering the cascaded system of Figure 5, the tuning goal is to achieve a settling time larger than ten times the settling time of the current controller (t_{s}|_{vc} > 10 · t_{s}|_{cc}, where t_{s} is the settling time, “vc” means voltage control and “cc” means current control). This constraint affects the position of the closed-loop pole introduced by the PI controller. The integral constant (k_{i}) helps achieve zero steady-state error in the event of model mismatch and disturbances. Therefore, the parameter tuning is focused on settling time and controller bandwidth. The resulting parameters are k_{p} = 0.05 and k_{i} = 350.
In order to prevent the windup of the integrator, an antiwindup mechanism has been added to each PI controller. It is characterized by the antiwindup constant, which has been set as k_{aw} = 0.1. High values for this parameter cause system instability. When using an antiwindup technique, an important detail to be taken into account is that its contribution should not be added to the integral branch of the PI controller until the whole control system starts. Otherwise, the control system would be forced to start with a non-zero error.
The linear operating range of a STATCOM with given maximum capacitive and inductive ratings can be extended if a regulation “droop” is allowed. Regulation “droop” means that the terminal voltage is allowed to be smaller than the nominal no-load value at full capacitive compensation and, conversely, it is allowed to be higher than the nominal value at full inductive compensation [13]. It also ensures automatic load sharing with other voltage compensators. Perfect regulation (zero droop or slope) could result in poorly defined operating point, and a tendency of oscillation, if the system impedance exhibited a “flat” region (low impedance) in the operating frequency range of interest [13]. It should be mentioned that this possible regulation makes sense in scenarios where there are several converters connected in parallel trying to control the PCC voltage. This droop control has been added to the voltage controller as shown in Figure 8, characterized by the constant droop = 0.01. Similarly to k_{aw}, high values for this parameter cause system instability. The expression in Equation (11) is obtained from Equation (10).
3.5. dq to αβ Transformation and Calculation of ${i}_{\alpha \beta}^{\ast}$
The outputs of the first stage of the control scheme are ${i}_{dq}^{+\ast}$ and ${i}_{dq}^{-*}$. These current references have to be transformed to αβ-axes, since the current controller is implemented in stationary reference frame. The reason for this is that a resonant controller tuned at ω in αβ-axes is able to compensate both positive and negative sequences, whereas in dq-axes two controllers would be necessary, a PI controller and a resonant controller tuned at 2ω_{1}. The fact of increasing the number of controllers connected in parallel endangers the system stability and increases the settling time of the controller.
Positive and negative sequence current references in αβ-axes are calculated as shown in Equation (12a) and (12b). The estimated phase angle θ̂) of the positive sequence voltage vector is obtained with a PLL, whose bandwidth is 20 Hz. This results in a good tradeoff between selectivity, steady-state error and response speed. Afterwards, the final current references are calculated according to Equation (13a) and (13b):
3.6. Current Controller
The third stage of the control scheme is the current controller. The harmonics present in power systems are those of order 6k ± 1 (k ∈ ℤ), which turn into 6k (k ∈ ℤ) when changing the reference frame from stationary (abc or αβ) to synchronous (dq). This allows halving the number of resonant controllers needed to implement the current controller [14]. Therefore, since the 5th (negative sequence) and 7th (positive sequence) harmonics are usually present in the grid, the current control scheme of Figure 9 has been used to obtain the simulation results. It consists of two resonant controllers (SOGIs) tuned at ω_{1} and 6ω_{1} (the blocks labeled as “ω_{1}” and “6ω_{1}” are composed of an integral gain k_{i} connected in series with a SOGI), a feedforward of the positive sequence PCC voltage, and αβ to dq and dq to αβ transformations. A feedforward of the total PCC voltage (including negative sequence) would introduce non-desired harmonics in the control. The error signals in αβ-axes and dq-axes are ε_{αβ} and ε_{dq}, respectively.
In general, the resonant frequency of the SOGI is represented by ω_{0}. The discrete SOGI transfer function is given by Equation (14) and, if ${\omega}_{0}^{2}{T}_{s}^{2}\ll 2$, which is verified for T_{s} < 1.4 ms (supposing that ${\omega}_{0}^{2}{T}_{s}^{2}=0.2$ is small enough, i.e., a factor of 10) and if ω_{0} = 2π50 rad/s, Equation (14) can be approximated by Equation (15):
The SOGI is combined with a proportional and integral gain (k_{p} and k_{i}, respectively) to form the current controller. The resulting transfer function can be expressed as:
To help decreasing the computational burden, the trigonometric functions employed in the calculation of these transformations can be implemented by means of look-up tables if the digital platform has enough memory.
3.7. Modulation Strategy
The NPC converter, whose scheme is shown in Figure 10, has some drawbacks such as the additional clamping diodes, a more complicated PWM switching pattern design and possible deviation of neutral point (NP) voltage [15]. The capacitors can be charged or discharged by neutral current i_{NP}, causing NP voltage deviation. It might appear a ripple of frequency three times the fundamental in u_{DC}_{1} and u_{DC}_{2} that can destroy components if both DC-link voltages are not balanced.
To minimize this effect, a carrier-based PWM strategy with zero-sequence voltage injection [16] is applied to the three-level NPC converter. Using this technique, the locally averaged NP current is kept to zero, and consequently, the locally averaged voltages on the DC-link capacitors are constant [17].
4. Online Adaptation of the DC-Link Reference Voltage
To enable the power transfer between the grid and the DC-link capacitors, u_{DC} must be greater than $\sqrt{2}$ v_{LL}, where v_{LL} is the RMS phase-to-phase NPC output voltage. When calculating the reference DC-link voltage, a safety margin Δu_{DC} is usually given to ensure the energy transfer in case of voltage fluctuations. This margin takes values from 20 V to 50 V in weak grids. Therefore, the calculation of ${u}_{DC}^{\ast}$ is shown in Equation (18):
When the PCC voltage is expected to suffer large variations, as in the case of weak grids, ${u}_{DC}^{\ast}$ should be recalculated online to adapt its value to the actual AC voltage. In this way, the modulation index is kept around its optimal value, i.e., m_{a} ≈ 1. Otherwise, the modulation index will be altered, which can increase the converter power losses, modify the expected harmonic content and worsen the overall system performance [15]. It is also advisable to limit the possible values of ${u}_{DC}^{\ast}$ so that controllability is always ensured, as in the case of voltage dips, and limit the transition rate of ${u}_{DC}^{\ast}.$
5. Sampling Mode When Working With an L-Filter
One of the essential parts of the converter control is the synchronization system, which allows detecting the angle of the PCC voltage vector. This angle would coincide with that of the grid voltage if it were an ideal grid. Generally, the grid impedance is neglected in terms of controller design, considering the voltage at the PCC as the system voltage [18].
Blasko et al. [19] established that the optimal moment to sample the currents are those in which the PWM carrier signal reaches its maximum and minimum value, since it is in those moments when the zero-crossing of the current ripple takes place. When working with an LCL-filter and a non-ideal grid, and sampling the PCC voltage at those same moments, the obtained PCC voltage in dq-axes corresponds to its actual value. However, this is not the same situation when working with an L-filter and a non-ideal grid. In this case, the PCC voltage presents a ripple in which two envelopes can be seen. By sampling synchronously with the sampling period of the currents, which is also the controller sampling period, the obtained PCC voltage corresponds to one of those envelopes, giving rise to incorrect projections of the PCC voltage on the dq-axes.
Briz et al. [20] posed two alternative methods to the method suggested by Blasko for sampling the currents, when the inverter is connected to a load whose natural frequency may be close to the sampling frequency. In such cases, the method based on the maximum and minimum points of the carrier signal introduces an error at the current fundamental frequency as well as aliasing problems. The methods the authors proposed were based on advancing the sampling instant and on multi-sampling per switching period.
The methods studied here for sampling the PCC voltage are similar to those shown in [20]. With the system configuration defined in Table 1, several methods for performing the PCC voltage sampling are shown in Figure 11 [21]:
- (a)
The previously mentioned sampling method synchronized with the current sampling, where the sampling period of the PCC voltage and the timer, T_{ss}, is equal to T_{s} (Figure 12a);
- (b)
Sampling at the midpoint of T_{s}, with T_{ss} = T_{s}, which obtains a PCC voltage in dq-axes higher than the real value (Figure 12b);
- (c)
Sampling shifted a time t_{ad} with respect to the sampling instants of the current, where T_{ss} = T_{s} and where the voltage remains erroneous (Figure 12c, where t_{ad} = T_{s}/4);
- (d)
Oversampling of two samples, synchronized with T_{s}, where T_{ss} = T_{s}/2 and for which the voltage remains slightly erroneous (Figure 12d);
- (e)
Oversampling of three samples, synchronized with T_{s}, where T_{ss} = T_{s}/3 and for which the voltage still remains slightly erroneous (Figure 12e), and
- (f)
Oversampling of four samples, which obtains a correct PCC voltage in dq-axes (Figure 12f).
The estimated ${u}_{q}^{+}$ ( ${\tilde{u}}_{q}^{+}$) in steady-state with the six methods mentioned above are compared with the peak value of the fundamental PCC voltage in Figure 12g. Figure 13 shows the effect of applying each sampling method on the a-phase of the PCC voltage. It is straightforward to see the relationship between Figures 12g and 13:
Methods (a) and (c) detect an inner envelope of u, giving ${\tilde{u}}_{q}^{+}<{u}_{q}^{+}$. Besides, the envelope detected with method (c) is the one closest to the fundamental voltage and, thus, ${{\tilde{u}}_{q}^{+}|}_{a)}<{{\tilde{u}}_{q}^{+}|}_{c)}<{u}_{q}^{+}$;
Method (b) detects an outer envelope of u, yielding ${{\tilde{u}}_{q}^{+}|}_{b)}>{u}_{q}^{+}$;
Methods (d) and (e) perform a more precise detection of the PCC voltage than methods (a) to (c), although there is still a small steady-state error. It is also observed that ${{\tilde{u}}_{q}^{+}|}_{e)}>{{\tilde{u}}_{q}^{+}|}_{d)}>{u}_{q}^{+}$ in spite of using a higher oversampling, which is due to the sampling at highly-noisy points of u;
Method (f), i.e., oversampling of four samples synchronized with T_{s}, is the only method that performs a precise detection of the PCC fundamental voltage: ${{\tilde{u}}_{q}^{+}|}_{f)}\approx {u}_{q}^{+}.$
The initial transient in the estimation of ${u}_{dq}^{+}$ (Figure 12a–f) is due to the stabilization process of the PLL. However, this transient is not significant from the viewpoint of control performance because the converter control system only starts when the PLL is stable.
6. Simulation Results
6.1. Weak Grid Without Harmonics
A simulation has been carried out with MATLAB/Simulink^{®} in order to test the performance of the proposed voltage controller. The ideal grid voltage of Figure 2 has been considered, along with the system parameters of Table 1. The NPC rated power is 100 kVA and the DC-link capacitors have a value of C_{DC}_{1} = C_{DC}_{2} = 4.5 mF. No load is connected to the PCC. The proposed voltage controller is enabled at t = 0.5 s.
Figure 14 shows the temporary evolution of the filtered PCC voltage in abc-axes. Its non-filtered waveform presents a high ripple due to the high grid impedance and, in order to appreciate the effect of the PCC voltage controller, its filtered waveform is the one represented. In the following figures, the corresponding control activation time is marked with a dashed black line. It is clear that, when the voltage control is enabled, the PCC voltage is balanced. This is corroborated by decomposing this voltage in their positive and negative sequences as shown in Figure 15. The positive sequence ${u}_{dq}^{+}$ remains equal because its reference voltage corresponds to the value it had before enabling the PCC voltage control. The negative sequence ${u}_{dq}^{-}$ becomes almost zero since its reference voltage is set to zero for both d and q components, as well as the VUF.
The current flowing from the VSC to the grid is represented in Figure 16a in abc-axes. Since no load is connected to the PCC, the current before enabling the voltage control is zero. Afterwards, the VSC provides an unbalanced current in order to compensate the negative sequence component. This is better observed in Figure 16b, which is a representation of Figure 16a between t = [0.45 0.65] s. Figure 16c is the equivalent of Figure 16b if the resonant controller 2ω is not included in the DC-link voltage controller, showing a PCC current with a 3rd order harmonic.
Since the PCC voltage is no longer unbalanced due to the effect of the voltage controller, the unbalance now appears in u_{DC}. Figure 17a shows that a large oscillation appears in u_{DC}, reaching nearly ±150 V. Besides, the DC-link voltage unbalance, calculated as the difference between positive and negative DC-link voltages (u_{DC}_{1} − u_{DC}_{2}), also increases. If the oscillation level is not permissible, the reference for the negative sequence voltage can be set with a value different from zero but still low enough to satisfy regulations when it comes to maximum PCC voltage unbalance. In any case, it is worth remembering that the high level of unbalance applied to carry out these tests is usually not found in a real power system, so that in practice the amplitude of the oscillation will be much smaller. According to current regulations, a VUF greater than 2% in the worst case (e.g., IEC 61000-3-13 regulation) and 3% in the best case (e.g., ENTSO-E regulation) requires the disconnection of the converter from the grid, which can be avoided with the proposed PCC voltage controller.
6.2. Weak Grid With 5th and 7th Order Harmonics and a Higher Level of Negative Sequence
In order to test the performance of the proposed PCC voltage controller in a more realistic situation, 5th and 7th order harmonics have been included in the grid voltage with a level of A_{5} = 0.01 · A_{1} and A_{7} = 0.03 · A_{1}, respectively. Furthermore, a higher level of negative sequence has been chosen (VUF = 10%). Figure 18 shows the temporal evolution of the PCC voltage waveform, validating as well the proper operation of the PCC voltage controller by compensating its negative sequence. The performance of the proposed controller is also observed in Figure 19, which collects the evolution of ${u}_{dq}^{+}$ (Figure 19a), ${u}_{dq}^{-}$ (Figure 19b) and the VUF (Figure 19c).
7. Conclusions
This article has proposed a PCC voltage controller in synchronous reference frame to compensate an unbalanced PCC voltage by means of a STATCOM, allowing an independent control of both positive and negative voltage sequences. To do so, the grid model has been studied under unbalanced conditions, showing the equations that relate voltage and current.
This voltage controller has been placed inside a control scheme to evaluate its performance by means of simulation results. These results have demonstrated the efficacy of this controller, managing to significantly reduce the oscillation present in the DC-link voltage.
However, due to the compensation of the PCC voltage negative sequence, an oscillation appears on the DC-link voltage, with frequency twice the fundamental grid frequency. The magnitude of this oscillation depends on the level of negative sequence. If the level of this oscillation is not permissible, the voltage reference for negative sequence voltage can be set with a value different from zero but still low enough to satisfy regulations when it comes to maximum PCC voltage unbalance. This would result in a reduction of u_{DC} oscillation and DC-link voltage unbalance.
Experimental results have not been provided because the grid at our laboratory is not a weak grid and, even though this could be simulated by increasing the inductance in series with the VSC (thus, increasing the grid impedance), our three-level NPC converter has not been sized for compensating such unbalances.
This work has been funded by the Spanish Ministry of Economy and Competitiveness; projects ENE2011-28527-C04-01 and ENE2011-28527-C04-02.
Conflicts of Interest
The authors declare no conflict of interest.
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Table 1. System parameters with L-filter and non-ideal grid. |
Parameter | Symbol | Value | Units |
---|---|---|---|
Base apparent power | S_{base} | 100 | kVA |
Base voltage | U_{n} | $400\sqrt{2/3}$ | V |
Fundamental pulsation | ω_{1} | 2π50 | rad/s |
Grid-filter inductance | L | 0.2209 | p.u. |
Grid-filter resistance | R | 0.0034 | p.u. |
Grid-impedance inductance | L_{g} | 0.0736 | p.u. |
Grid-impedance resistance | R_{g} | 0.0005 | p.u. |
Switching period | T_{sw} | 200 | μs |
Sampling period | T_{s} | 100 | μs |
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