Suppression of Switching Crosstalk and Voltage Oscillations in a SiC MOSFET Based Half-Bridge Converter

Abstract

The silicon carbide (SiC) MOSFET is characterized by high operating voltage, temperature, switching frequency and efficiency which enables a converter to achieve high power density. However, at high switching frequency, the crosstalk phenomenon occurs when the gate voltage spike introduced by high dv/dt and voltage ringing forces false turn-on of SiC MOSFET which causes a crow-bar current thereby increasing switching losses. In order to increase the immunity against the crosstalk phenomenon in a half-bridge configuration, this paper presents a gate driver for SiC MOSFET capable of generating the negative turn-off voltage without using a negative power supply. In addition, the effect of parasitic inductances on the switching response is analyzed and an RC snubber is designed using high-frequency based circuit reduction technique to dampen the switching ringing. The performance of the proposed gate driver and the designed RC snubber is validated using simulation and experiment at the 1 MHz switching frequency. The results show that the proposed gate driver with RC snubber eliminates crosstalk by maintaining any spurious gate spike below the gate threshold voltage.

1. Introduction

The demand for fast-switching, high voltage, and high-temperature devices, capable of operating at elevated efficiency has enabled the trend towards WBG semiconductor materials [1,2]. Among the WBG, the SiC and GaN technologies have matured enough and devices up to 1.7 kV and 650 V voltage ratings respectively, are commercially available which have been proved as promising alternatives to the Si. Due to an almost identical gate drive requirements, the GaN cascode transistor can easily replace Si MOSFET [3]. However, due to features such as a restricted-range of gate voltage, low threshold voltage, and low parasitic capacitances the gate drive requirements of a SiC MOSFET are more stringent [4,5].

The recent research focuses on the gate driver design for SiC MOSFET to enable the high switching speed, also featuring the damping of parasitic resonance and crosstalk suppression [6,7]. The crosstalk phenomena in half-bridge configuration refer to the spurious triggering of the low-side SiC MOSFET during the turn-on transition of the high-side SiC MOSFET and vice versa [8]. Due to voltage rise across the device in off-state, a charging current flow through its parasitic gate-drain capacitance and induces a positive spike in its gate voltage. When this voltage spike exceeds the gate threshold voltage, it can falsely trigger the high-side MOSFET, which causes a crow-bar current and result in increased switching power losses. Therefore, it is essential to suppress the crosstalk phenomena for the high-frequency and reliable operation of the half-bridge converter [9].

The gate-impedance control technique reduces the gate voltage spike by adding external gate-source capacitance to provide a low-impedance path [10,11]. However, the crosstalk mitigation is vestigial as it results in a prolonged switching transition, increasing the switching losses [12]. The active suppression technique reported in [13], employed a transistor between the gate and source terminals to create a short when the gate-source voltage climb above the threshold voltage is detected. However, due to the high internal gate and source impedances, the gate voltage feedback for crosstalk detection lacks accuracy and degrades the effectiveness of active suppression system.

Another reported technique used a negatively biased gate voltage, which by level shifting the gate voltage spike prevents false turn-on and accelerates the SiC MOSFET’s turn-off [14]. The negative turn-off voltage is commonly supplied using an additional negative voltage source, but, the level shifter circuits proposed in [15,16] used voltage divider circuit to get rid of the negative voltage source. However, due to increased circuit complexity, it is not a viable solution for volume optimized and cost-sensitive converters. In this paper, a gate driver is proposed for SiC MOSFET to suppress the crosstalk phenomena by a negative level shifting of the gate voltage using a parallel connected zener diode and a capacitor. Furthermore, the proposed driver circuit does not require a dedicated negative voltage source and voltage feedback and is realized using low-cost components.

The parasitic inductance and stray capacitance of SiC MOSFET at a high-switching frequency manifest resonance which introduces a voltage overshoot and ringing during turn-off transition [17]. The parasitic package inductances of the SiC MOSFET becomes further unpropitious when combined with the stray inductance of PCB interconnection [18]. The parasitic inductance reinforces voltage overshoot which deteriorates the total harmonic distortion (THD) performance, and as a result, the converter may require a higher-order filter to meet the desired performance. Therefore, it is necessary to suppress the parasitic resonance to enable improved THD of half-bridge dc-ac converter or otherwise; the high-frequency operation will be vestigial [19].

Optimization of package inductances for pushing higher the parasitic resonant frequency is becoming faltered, and therefore, the conspicuous solution is to maneuver the impedance of the switching circuit using an auxiliary network [20]. Several techniques aimed to suppress the voltage ringing, range in complexity from reducing the switching speed using high gate impedance to active gate control involving a feedback compensator [21,22]. The simplest approach advocates lowering the switching speed by raising the gate impedance, however, the prolonged switching transition enlarges switching losses [23]. Due to magnetic saturation caused by current escalation limits application of ferrite bead to restrain the parasitic inductance. Moreover, the suppression using dc-link capacitors [24] and magnetically coupled damping circuits [25] is not very convincing. The RC shunt snubber is the familiar and most effective technique which offers flexibility to achieve the desired level of suppression. However, the experience-based design commonly leads to inadequate damping [26]. In [27], the authors formulated a root-locus based RC snubber design for the double-pulse circuit by neglecting the parasitic source inductance of the SiC MOSFET. In this work, the same design procedure is adapted to optimize the suppression circuit for the half-bridge dc-ac converter while the SiC MOSFET embodies the parasitic source inductance.

The rest of this paper is organized as follows. The gate driver for SiC MOSFET is presented in Section 2. Effect of parasitic components on switching response is illustrated in Section 3. In Section 4, the snubber circuit design is proposed for mitigating the switching ringing. Simulation and experimental results are presented in Section 5, followed by the conclusion in Section 6.

2. Gate Driver for SiC MOSFET

2.1. Crosstalk Phenomenon in Half-Bridge dc-ac Converter

Due to fast-rising drain-source voltage, the parasitic capacitances of a MOSFET cause a gate voltage spike during switching transitions and may result in spurious turn-on if it exceeds the threshold voltage. The SiC MOSFET is more vulnerable to false triggering due to its low-threshold voltage as compared to Si counterpart. For instance, the typical threshold voltage of Si MOSFET IPW65R190CFD from Infineon Technologies is 4 V, while for SiC MOSFET C3M0120090J from Cree Inc., the value is only 2.1 V. A detailed schematic of the half-bridge dc-ac converter, including the parasitic components of SiC MOSFET is shown in Figure 1a. The driving voltages v_GH and v_GL control the switching state of the high-side S_H and low-side S_L MOSFETs respectively. Further, the R_GL and R_GL(in) are the external and internal gate resistances of low-side MOSFET S_L respectively, while C_GSL, C_DGL, and C_DSL are its parasitic gate-source, drain-gate, and drain-source capacitances respectively.

It is assumed that S_L is in its blocking state, and the MOSFET S_H is tuning-on as shown in Figure 1b to illustrate the mechanism of spurious gate voltage spike. At time t₁, the v_GSH crosses the threshold voltage V_TH, which allows the drain-source voltage of the low-side MOSFET v_DSL to rise abruptly, producing a current i_DGL through parasitic capacitance C_DGL. This charging current i_DGL further flows through the parasitic capacitance C_GSL and the gate resistors R_GL(in) and R_GL, respectively denoted as i_GSL and i_GL. The current i_GL introduces a spike in the gate voltage v_GSL with the peak determined by R_GL, C_GSL, and C_DGL. Consequently, a spurious turn-on of the low-side MOSFET occurs if the resulting voltage spike exceeds the threshold voltage V_TH. A likely method to reduce i_GL is by adding external gate-source capacitance, which not only shunts the i_DGL but also useful in suppressing the resonance due to the stray inductance and gate-source capacitance C_GSL. However, the external gate-source capacitance increases the rise time of the gate voltage and thereby results in increased switching losses. In this paper, the crosstalk suppression by level-shifting of the gate voltage is adopted using a gate driver that does not require a dedicated negative voltage source and voltage feedback while is realized only using passive components.

2.2. Previous Work on Gate Driver for SiC MOSFET with Level Shifter

To increase the immunity of SiC MOSFET against the crosstalk phenomenon in a half-bridge configuration, a gate driver capable of generating the negative turn-off voltage without using a negative power supply is trending. The reason is that the elimination of negative voltage supply significantly reduces the complexity in the converter’s layout design. However, it is required that the level shifter circuit must be simple and effective to justify the replacement. Two of the recently reported gate drivers use RCD level shifter and voltage divider circuit.

The RCD level shifter [15] consists of two pairs of parallel connected resistor and capacitor and a diode as shown in Figure 2a. The diode D_P conducts when the driving voltage v_GL is high, otherwise it operates in the blocking mode. For C_P and C_N >> C_GSL, conduction of D_P sets the steady-state v_N as given by Equation (1). When v_GL flips back to the low-state, the D_P disconnects the R_P-C_P and forcing the turn-off gate current to flow through R_N-C_N branch. Therefore, the applied gate voltage is level shifted by V_N.

A modified version of the RCD level shifter reported in [28] is shown in Figure 2b, in which the offset in the gate voltage is also given by Equation (1). During turn-on of SiC MOSFET, the gate current returns through resistor R_M which triggers the transistor Q by creating a positive emitter-base voltage. The capacitor C_P precharged by gate driving voltage, charges C_GSL to avoid delays in turning-on. During turn-off of SiC MOSFET, the current flows through diode D when the capacitor C_N acts as local voltage source to supply negative voltage.

$$V_{\mathrm{N}}=\frac{R_{\mathrm{N}}}{R_{\mathrm{N}}+R_{\mathrm{P}}}{V}_{\mathrm{GG}}$$

(1)

2.3. Proposed Gate Driver for SiC MOSFET

The proposed gate driver is shown in Figure 3a only for low-side MOSFET, which is comprised of a capacitor C_ZL, an ultra-fast diode D_OFL, two resistors R_1L and R_2L, and three zener diodes D_ZL, D_ZPL and D_ZNL. The components of the high-side driver use similar notation, except their subscripts end with the letter “H” instead of letter “L”. The parallel connected zener diode D_ZL and capacitor C_ZL generates a negative gate voltage and thus perform the voltage level shifting without using a negative voltage supply. Due to narrow operating gate voltage range, i.e., 8/18 V, two zener diodes are used as a voltage clipper between the gate and source terminals to protect the MOSFET against the gate breakdown. The diode D_OFL enables a lower impedance path for the turn-off gate current to accelerate the turn-off transition. When the diode D_OFL is forward biased, a lower turn-off gate resistance is realized by the parallel connection of resistors R_1L and R_2L.

The design criterion of the components is approached through the transient analysis of the proposed gate driver. Mathematical expressions are derived for gate-source voltage during turn-on and turn-off process.

2.3.1. Turn-on Process

An equivalent circuit of the gate driver when the gate drive voltage v_GL steps from 0 to V_G at time t₀ is shown in Figure 3b. The inceptive gate current i_GPL path comprises the components C_ZL, R_1L, R_GL(in) and C_GSL, ramping up the voltage v_N to the zener voltage V_Z of the diode D_ZL. As a result, the current through the zener diode denoted as i_ZL rises and take over the capacitor current i_CL regulating v_N at V_Z. This indicates that i_GPL is the algebraic sum of the capacitor current i_CL and the current through the zener diode i_ZL. Kirchhoff voltage law (KVL) is applied to the equivalent circuit in Figure 3b which gives Equation (1) which is essential to derive the mathematical relation for i_GPL.

$$V_{\mathrm{G}}=\{\begin{array}{l}\left(R_{1\mathrm{L}}+R_{\mathrm{GL}\left(\mathrm{in}\right)}\right)i_{\mathrm{CL}}+\frac{1}{\left(C_{\mathrm{ZL}}+C_{\mathrm{GSL}}\right)}{\displaystyle \int i_{\mathrm{CL}}dt}\hspace{1em}\hspace{1em}\mathrm{when} v_{\mathrm{N}}<V_{\mathrm{Z}}\\ \left(R_{1\mathrm{L}}+R_{\mathrm{GL}\left(\mathrm{in}\right)}\right)i_{\mathrm{ZL}}+\frac{1}{C_{\mathrm{GSL}}}{\displaystyle \int i_{\mathrm{ZL}}dt}+V_{\mathrm{Z}}\hspace{1em}\hspace{1em}\mathrm{when} v_{\mathrm{N}}=V_{\mathrm{Z}}\end{array}$$

(2)

Using the Laplace transform, the solution of the integral equations in (2) are given in (3)

$$i_{\mathrm{GLP}}=\{\begin{array}{l}{i}_{\mathrm{CL}}=\frac{V_{\mathrm{G}}}{\left(R_{1\mathrm{L}}+R_{\mathrm{GL}\left(\mathrm{in}\right)}\right)}\exp \left(\frac{-t}{{\tau }_a}\right)\hspace{1em}\hspace{1em}\hspace{1em}\mathrm{when} v_{\mathrm{N}}<V_{\mathrm{Z}}\\ i_{\mathrm{ZL}}=\frac{V_{\mathrm{G}}-V_{\mathrm{Z}}}{\left(R_{1\mathrm{L}}+R_{\mathrm{GL}\left(\mathrm{in}\right)}\right)}\exp \left(\frac{-\left(t-t_1\right)}{{\tau }_b}\right)\hspace{1em}\hspace{1em}\mathrm{when} v_{\mathrm{N}}=V_{\mathrm{Z}}\end{array}$$

(3)

where t₁ is the time required to charge C_ZL to voltage V_Z, and τ_a and τ_b are the time constants expressed in (4). Equation (3) indicates that the peak i_GPL is determined by the driving voltage V_G, and the external and intrinsic gate resistors, i.e., R_1L and R_GL(in). Since τ_a > τ_b, the current i_ZL decays faster than i_CL. However, for the desired level shifting operation, the zener diode must not cease conduction until the v_GL step to 0 V.

$${\tau }_a=\left(C_{\mathrm{ZL}}+C_{\mathrm{GSL}}\right)\left(R_{1\mathrm{L}}+R_{\mathrm{GL}\left(\mathrm{in}\right)}\right)\hspace{1em}\mathrm{and}\hspace{1em}{\tau }_b=C_{\mathrm{GSL}}\left(R_{1\mathrm{L}}+R_{\mathrm{GL}\left(\mathrm{in}\right)}\right)$$

(4)

It is essential to observe v_GSL as gate-source voltage determines the MOSFET turn-on. Using KVL the voltage equation is given as

$$v_{\mathrm{GSL}}=V_{\mathrm{G}}-i_{\mathrm{GPL}}{R}_{1\mathrm{L}}-\left(\frac{1}{C_{\mathrm{ZL}}}{\displaystyle \int i_{\mathrm{GPL}}dt}+v_{\mathrm{N}}\left(t=t_0\right)\right)$$

(5)

substituting i_GPL gives the v_GSL expressed in (6). It indicates that the decay rate of v_GSL can be controlled by tuning C_ZL and R_1L. To prevent the abrupt drop of v_GSL the criteria, i.e., C_ZL >> C_GSL, should be ensured.

$$v_{\mathrm{GSL}}=\{\begin{array}{l}\frac{V_{\mathrm{G}}}{{\tau }_b}\left(R_{\mathrm{GL}\left(\mathrm{in}\right)}{C}_{\mathrm{GSL}}-{\tau }_a\right)\exp \left(\frac{-t}{{\tau }_a}\right)-v_{\mathrm{N}}\left(t=t_0\right)\hspace{1em}\hspace{1em}\mathrm{when} v_{\mathrm{N}}<V_{\mathrm{Z}}\\ \left(V_{\mathrm{G}}-V_{\mathrm{Z}}\right)\left(1-\frac{R_{1\mathrm{L}}}{\left(R_{1\mathrm{L}}+R_{\mathrm{GL}\left(\mathrm{in}\right)}\right)}\exp \left(\frac{-\left(t-t_1\right)}{{\tau }_b}\right)\right)\hspace{1em}\hspace{1em}\hspace{1em}\mathrm{when} v_{\mathrm{N}}=V_{\mathrm{Z}}\end{array}$$

(6)

2.3.2. Turn-off Process

When v_GL steps to 0 V, the diode D_OFL provides a low impedance path for the gate drive current i_GNL, turning-off MOSFET as shown in Figure 3c. It is desirable to use low-valued external gate resistance as it shortens the turn-off time. The Kirchhoff voltage law applied to the equivalent circuit in Figure 3c gives the integral equation

$$\left(R_{\mathrm{TL}}+R_{\mathrm{GL}\left(\mathrm{in}\right)}\right)i_{\mathrm{GNL}}+\frac{1}{\left(C_{\mathrm{ZL}}+C_{\mathrm{GSL}}\right)}{\displaystyle \int i_{\mathrm{GNL}}dt}=V_{\mathrm{Z}}$$

(7)

where R_TL = R_1L//R_2L. Again, solving the Equation (7) using the Laplace Transform gives the gate loop current i_GPL and voltage-source v_GSL voltage as

$$\{\begin{array}{l}{i}_{\mathrm{GNL}}=\frac{V_{\mathrm{Z}}}{R_{\mathrm{TL}}+R_{\mathrm{GL}\left(\mathrm{in}\right)}}\exp \left(\frac{-t}{{\tau }_{\mathrm{c}}}\right)\\ V_{\mathrm{GSL}}=-V_{\mathrm{Z}}\exp \left(\frac{-t}{{\tau }_{\mathrm{c}}}\right)\end{array}$$

(8)

where τ_c is the time constant of the equivalent driver circuit during turn-off and is expressed by

$${\tau }_{\mathrm{c}}=\left(C_{\mathrm{ZL}}+C_{\mathrm{GSL}}\right)\left(\frac{R_{1\mathrm{L}}{R}_{2\mathrm{L}}}{R_{1\mathrm{L}}+R_{2\mathrm{L}}}+R_{\mathrm{GL}\left(\mathrm{in}\right)}\right)$$

(9)

The capacitor C_ZL, precharged up to voltage V_Z serves as a local storage and supplies a negative gate voltage during turn-off without using a dedicated negative voltage supply. Again, to maintain the negative gate voltage, the value of C_ZL must satisfy the condition

$$\left(C_{\mathrm{ZL}}+C_{\mathrm{GSL}}\right)\left(\frac{R_{1\mathrm{L}}{R}_{2\mathrm{L}}}{R_{1\mathrm{L}}+R_{2\mathrm{L}}}+R_{\mathrm{GL}\left(\mathrm{in}\right)}\right)>D_{\mathrm{m}}{T}_{\mathrm{S}}$$

(10)

where D_m is the expected maximum duty-cycle, and T_S is the switching period.

Equations (6) and (8) indicate that the proposed gate driver level shift v_GSL by −V_Z and thus toggles between −V_Z and V_G − V_Z voltage levels. The negative bias voltage has a negligible effect on the turn-on transient of the MOSFET, but accelerates the turn-off as illustrated by the waveforms of the proposed gate driver in Figure 4.

3. Effect of Parasitic Inductances on Switching Waveform of SiC MOSFET

The demand for miniaturized power converters pushes the semiconductor devices to operate at higher switching frequencies. However, the parasitic inductances from PCB interconnections and device packages together with the stray capacitances of the SiC MOSFET can influence switching operation due to high di/dt [29,30]. They causes parasitic resonances which increase electrical stress [31] and slow down the rise and fall of drain current [32]. Therefore, it is important to model effect of parasitic components on switching characteristics. For the study, a conduction overlap is assumed, followed by the low-side MOSFET turn-off transient.

3.1. Overlap Conduction

In the presence of interconnection inductances, an overlap in the conduction of two switches is first investigated to recognize the effect on the turn-off process. Figure 5a shows the half-bridge dc-ac converter with lumped package and interconnection inductances. The L_DH and L_DL represent the drain inductances, and L_SH and L_SL represent source inductances of S_H and S_L MOSFETs respectively. When the dead-time is too short, there is overlap conduction which allows a momentary crow-bar current. It is assumed that switch S_L is initially conducting current I_o and before its transition to blocking state, the high-side MOSFET S_H turns-on creating a crow-bar current. Therefore, MOSFETs S_H and S_L are replaced with close switches with conduction resistance R_ONH and R_ONL respectively. The inductor current is assumed as a current source I in order to simplify the analysis. The voltage equations of the equivalent circuit during overlap conduction are given as

$$\{\begin{array}{l}{V}_{\mathrm{IN}}=\left(L_{\mathrm{DH}}+L_{\mathrm{SH}}\right)\frac{d{i}_{\mathrm{DH}}}{dt}+i_{\mathrm{DH}}{R}_{\mathrm{ONH}}+L_{\mathrm{DL}}\frac{d{i}_{\mathrm{DL}}}{dt}+v_{\mathrm{DSL}}\\ v_{\mathrm{DSL}}=L_{\mathrm{SL}}\frac{d{i}_{\mathrm{DL}}}{dt}+i_{\mathrm{DL}}{R}_{\mathrm{ONL}}\end{array}$$

(11)

using i_DH = I + i_DL in (11), and using Laplace transform to solve, the low-side drain current i_DL and drain voltage v_DSL are expressed as follows.

$$\{\begin{array}{l}{i}_{\mathrm{DL}}=I_{\mathrm{o}}\exp \left(\frac{-t}{{\tau }_{\mathrm{d}}}\right)+\frac{\left(V_{\mathrm{IN}}-I{R}_{\mathrm{ONH}}\right)}{\left(R_{\mathrm{ONL}}+R_{\mathrm{ONH}}\right)}\left(1-\exp \left(\frac{-t}{{\tau }_{\mathrm{d}}}\right)\right) \mathrm{where} {\tau }_{\mathrm{d}}=\frac{\left(R_{\mathrm{ONL}}+R_{\mathrm{ONH}}\right)}{\left(L_{\mathrm{DL}}+L_{\mathrm{SL}}+L_{\mathrm{DH}}+L_{\mathrm{SH}}\right)}\\ v_{\mathrm{DSL}}=\frac{\left(L_{\mathrm{DL}}+L_{\mathrm{SL}}\right)}{{\tau }_{\mathrm{d}}}\left\{\frac{\left(V_{\mathrm{IN}}-I{R}_{\mathrm{ONH}}\right)}{\left(R_{\mathrm{ONL}}+R_{\mathrm{ONH}}\right)}-I_{\mathrm{o}}\right\}\exp \left(\frac{-t}{{\tau }_{\mathrm{d}}}\right)+\left(V_{\mathrm{IN}}-I{R}_{\mathrm{ONH}}\right)\frac{R_{\mathrm{ONL}}}{\left(R_{\mathrm{ONL}}+R_{\mathrm{ONH}}\right)}\left(1-\exp \left(\frac{-t}{{\tau }_{\mathrm{d}}}\right)\right)\end{array}$$

(12)

Assuming R_ONL = R_ONH, Equation (11) indicates that v_DSL will approach 0.5 × (V_IN − IR_ONH) during the overlap time of length T_oc, energizing the parasitic inductances.

3.2. The S_L Turn-off Transient

Following the overlap conduction, the transition of low-side MOSFET from conduction to blocking state is shown in Figure 5b, with S_L replaced with an open switch. During this switching transition, the interconnection inductances release their previously stored energy. The drain-source capacitance C_DSL and inductances L_DL and L_SL of the low-side MOSFET realizes a resonant circuit which introduces oscillations in v_DSL. The circuit equation during S_L turn-off is given as

$$\{\begin{array}{l}{V}_{\mathrm{IN}}=\left(L_{\mathrm{DH}}+L_{\mathrm{SH}}\right)\frac{d{i}_{\mathrm{DH}}}{dt}+i_{\mathrm{DH}}{R}_{\mathrm{ONH}}+L_{\mathrm{DL}}\frac{d{i}_{\mathrm{DL}}}{dt}+v_{\mathrm{DSL}}\\ v_{\mathrm{DSL}}=L_{\mathrm{SL}}\frac{d{i}_{\mathrm{DL}}}{dt}+\frac{1}{C_{\mathrm{DS}}}{\displaystyle \int i_{\mathrm{DL}}dt}\end{array}$$

(13)

Differentiation of (14) and using i_DH = I + i_DL, reduces the circuit equation to the following standard form

$$\frac{d^2{i}_{\mathrm{DL}}}{d{t}^2}+2{\omega }_{\mathrm{r}}\zeta \frac{d{i}_{\mathrm{DL}}}{dt}+{\omega }_{\mathrm{r}}^2{i}_{\mathrm{DL}}=0$$

(14)

where the resonance frequency ω_r and damping factor ζ are related to the parasitic components as

$${\omega }_{\mathrm{r}}=\frac{1}{\sqrt{C_{\mathrm{DS}}\left(L_{\mathrm{DH}}+L_{\mathrm{SH}}+L_{\mathrm{DL}}+L_{\mathrm{SL}}\right)}} \mathrm{and} \zeta =\frac{R_{\mathrm{ONH}}}{2}\sqrt{\frac{C_{\mathrm{DS}}}{\left(L_{\mathrm{DH}}+L_{\mathrm{SH}}+L_{\mathrm{DL}}+L_{\mathrm{SL}}\right)}}$$

(15)

Using the Laplace transform, the equation for drain current i_DL is expressed in (15)

$$i_{\mathrm{DL}}=A\exp \left(-\zeta {\omega }_{\mathrm{r}}t\right)\sin \left(\left({\omega }_{\mathrm{r}}\sqrt{1-{\zeta }^2}\right)t\right)+B\exp \left(-\zeta {\omega }_{\mathrm{r}}t\right)\cos \left(\left({\omega }_{\mathrm{r}}\sqrt{1-{\zeta }^2}\right)t\right)$$

(16)

where the initial conditions determine the constants A and B. Due to the equivalent second-order circuit, i_DL exhibit underdamped oscillations as determined by the milliohm ranged conduction resistance R_ONH, forcing v_DSL to swing accordingly.

Figure 6 shows the waveform of i_DL for overlap conduction interval T_oc followed by turn-off of low side MOSFET S_L. Assuming an initial 1.2 A steady drain-source current through the body diode of S_L, during T_oc the cross-bar current forces i_DL to rise rapidly. Finally, elapse of T_oc results in underdamped oscillations. A significant reduction is noted in the average drain-source voltage which would result in a lower voltage gain of the dc-ac conversion.

3.3. PCB Guidelines

Besides, there is always inescapable intrinsic parasitic inductances of the device, but an adequate PCB layout can optimize the efficiency, enhances the input voltage operating range and reduces the noise among traces of converter [33]. Importantly, minimizing the high-frequency loop inductance enables higher switching frequencies and reduces the voltage overshoot and EMI. Besides improving the THD, it also relaxes the filter requirement. The input path carries the pulsating current and thereby needs special attention as high di/dt and parasitic inductance of a trace can generate voltage ringing [34]. Therefore, it is necessary to minimize the circumference of the high-frequency power-loop.

Conventionally, the power-loop is routed on a single layer known as the lateral power-loop, while the next inner layer is used as a shield plane [19], which reduces the impact of the field generated by high-frequency switching. Due to pulsating current, the power-loop induces a current in the shield layer which produces a magnetic field of its own, counteracting the field of the power-loop. Here the shortest loop has been achieved using the top and the next inner layer (power plane) for laying out the power-loop. Transistors have been placed on the topmost layer, while the internal power plane serves as the return path. Furthermore, the power inductor has been placed on the bottom layer and connected to the drain of MOSFET using vias. Several interleaved channels by assuming vias reduce the current density and thus the interconnection inductances. This results in a smaller power-loop with the field cancellation capability.

The soldering pad for the transistor’s tab serves as the primary heat-sink, and thereby a larger copper area is assigned to spread out the heat. The vias used to connect the power plane, and drain of the high-side MOSFET not only reduces the parasitic inductance but also improves the thermal performance by facilitating heat conduction from top to bottom of the PCB [35]. Since the bottom is a low-resistance path for heat flow, vias on the bottom side are connected to the large copper polygon. Heat sink soldered on the bottom-side is recommended to improve the thermal performance further.

4. RC Snubber for Suppression of Parasitic Ringing

The antecedent section discussed the negative influence of parasitic elements on the switching waveform of SiC MOSFET. The derived equation indicates that due to parasitic inductance and capacitance the drain current undergoes ringing, thereby forcing the drain-source voltage to oscillate [36,37]. Suppression of this obtruded ringing in the switching waveform is vital to ensure low distortion and stunted electromagnetic noise [38]. Here, the objective is to dampen the ringing in the drain-source voltage of the low-side MOSFET S_L during turn-off by employing an RC snubber across the S_L as shown in Figure 7a. The R_SBR and C_SBR represent snubber circuit resistance and capacitance respectively, while R_C1 and R_C2 are the equivalent series resistance (ESR) of dc-link capacitors.

The snubber design starts with deriving an equivalent circuit of Figure 7a using the high-frequency minimization [27]. It is supposed that initially, the low-side MOSFET S_L conducts current I_o. When the channel resistance increases during the turn-off process, a change in drain-source voltage v_DSL causes the drain-source capacitance C_DS of the MOSFET to conduct. Finally, neglecting body-diode conduction resistance, replacing large inductances such as L and interconnection inductance between source and converter with open, and replacing dc-link capacitances with short-circuit result in the equivalent circuit shown in Figure 7b. The notation i_SBR, i_D, and v_DSL represent current through snubber, drain current and drain-source voltage of S_L respectively. In [27], the authors ignored the parasitic source inductance L_SL and assumed v_DSL as the voltage across C_DS. On the contrary, v_DSL is exercised here as the sum of the voltage across C_DS and L_SL to achieve more accurate analysis.

The next step is to derive the expression for v_DSL as a function of initial drain current I_o using the equivalent circuit, which gives the rule for snubber components design. Applying KCL and KVL to the equivalent circuit gives the dynamics in (17).

$$\{\begin{array}{l}{i}_{\mathrm{M}}=i_{\mathrm{DL}}+i_{\mathrm{SBR}}\\ v_{\mathrm{DSL}}=\frac{1}{C_{\mathrm{DSL}}}{\displaystyle \int i_{\mathrm{D}}dt}+L_{\mathrm{SL}}\frac{d{i}_{\mathrm{DL}}}{dt}\\ v_{\mathrm{DSL}}=\frac{1}{C_{\mathrm{SBR}}}{\displaystyle \int i_{\mathrm{SBR}}dt}+i_{\mathrm{SBR}}{R}_{\mathrm{SBR}}-L_{\mathrm{DL}}\frac{d{i}_{\mathrm{DL}}}{dt}\\ v_{\mathrm{DSL}}=-i_{\mathrm{M}}\left(R_{\mathrm{C}1}+R_{\mathrm{C}2}\right)-\left(L_{\mathrm{DH}}+L_{\mathrm{SH}}\right)\frac{d{i}_{\mathrm{M}}}{dt}-L_{\mathrm{DL}}\frac{d{i}_{\mathrm{DL}}}{dt}\end{array}$$

(17)

Applying Laplace transform and using I_SBR, I_DL, I_M, and V_DSL for the corresponding s-domain functions of i_SBR, i_DL, i_M, and v_DSL, respectively, gives Equation (18).

$$\{\begin{array}{l}{I}_{\mathrm{M}}=I_{\mathrm{DL}}+I_{\mathrm{SBR}}\left(\mathrm{a}\right)\\ V_{\mathrm{DSL}}=\frac{I_{\mathrm{D}}}{s{C}_{\mathrm{DSL}}}+L_{\mathrm{SL}}\left(s{I}_{\mathrm{D}}-I_{\mathrm{o}}\right)\left(\mathrm{b}\right)\\ V_{\mathrm{DSL}}=\frac{I_{\mathrm{SBR}}}{s{C}_{\mathrm{SBR}}}+I_{\mathrm{SBR}}{R}_{\mathrm{SBR}}-L_{\mathrm{DL}}\left(s{I}_{\mathrm{DL}}-I_{\mathrm{o}}\right)\left(\mathrm{c}\right)\\ V_{\mathrm{DSL}}=-I_{\mathrm{M}}\left(R_{\mathrm{C}1}+R_{\mathrm{C}2}\right)-\left(L_{\mathrm{DH}}+L_{\mathrm{SH}}\right)\left(s{I}_{\mathrm{M}}-I_{\mathrm{o}}\right)-L_{\mathrm{DL}}\left(s{I}_{\mathrm{D}}-I_{\mathrm{o}}\right)\left(\mathrm{d}\right)\end{array}$$

(18)

Using (18a)–(18c) in (18d) and solving for V_DSL gives (19) in terms of initial drain current I_o.

$$V_{\mathrm{DSL}}=\frac{N\left(s\right)}{\Delta \left(s\right)}{I}_{\mathrm{o}}$$

(19)

where the numerator N and denominator ∆ are expressed in (19) and (20) respectively.

$$\begin{array}{l}N(s)=s^2\left(C_{\mathrm{SBR}}{L}_{\mathrm{DH}}{L}_{\mathrm{DL}}+C_{\mathrm{SBR}}{L}_{\mathrm{SH}}{L}_{\mathrm{DL}}-C_{\mathrm{DSL}}{C}_{\mathrm{SBR}}{L}_{\mathrm{SL}}{R}_{\mathrm{C}1}{R}_{\mathrm{SBR}}-C_{\mathrm{DSL}}{C}_{\mathrm{SBR}}{L}_{\mathrm{SL}}{R}_{\mathrm{C}2}{R}_{\mathrm{SBR}}\right)\\ +s\left(\begin{array}{l}{C}_{\mathrm{SBR}}{R}_{\mathrm{SBR}}{L}_{\mathrm{DL}}+C_{\mathrm{SBR}}{R}_{\mathrm{SBR}}{L}_{\mathrm{SH}}+C_{\mathrm{SBR}}{R}_{\mathrm{SBR}}{L}_{\mathrm{DH}}+C_{\mathrm{SBR}}{R}_{\mathrm{C}1}{L}_{\mathrm{DL}}+C_{\mathrm{SBR}}{R}_{\mathrm{C}2}{L}_{\mathrm{DL}}\\ -C_{\mathrm{DSL}}{R}_{\mathrm{C}1}{L}_{\mathrm{SL}}-C_{\mathrm{DSL}}{R}_{\mathrm{C}2}{L}_{\mathrm{SL}}\end{array}\right)\\ +L_{\mathrm{DH}}+L_{\mathrm{SH}}+L_{\mathrm{DL}}\end{array}$$

(20)

$$\begin{array}{l}\Delta (s)=s^4\left(C_{\mathrm{DSL}}{C}_{\mathrm{SBR}}{L}_{\mathrm{SL}}{L}_{\mathrm{DH}}+C_{\mathrm{DSL}}{C}_{\mathrm{SBR}}{L}_{\mathrm{SL}}{L}_{\mathrm{SH}}+C_{\mathrm{DSL}}{C}_{\mathrm{SBR}}{L}_{\mathrm{DL}}{L}_{\mathrm{SH}}+C_{\mathrm{DSL}}{C}_{\mathrm{SBR}}{L}_{\mathrm{DL}}{L}_{\mathrm{DH}}\right)\\ +s^3\left(\begin{array}{l}{C}_{\mathrm{DSL}}{C}_{\mathrm{SBR}}{L}_{\mathrm{SL}}{R}_{\mathrm{C}1}+C_{\mathrm{DSL}}{C}_{\mathrm{SBR}}{L}_{\mathrm{SL}}{R}_{\mathrm{C}2}+C_{\mathrm{DSL}}{C}_{\mathrm{SBR}}{L}_{\mathrm{DL}}{R}_{\mathrm{C}1}+C_{\mathrm{DSL}}{C}_{\mathrm{SBR}}{L}_{\mathrm{DL}}{R}_{\mathrm{C}2}\\ +C_{\mathrm{DSL}}{C}_{\mathrm{SBR}}{L}_{\mathrm{DH}}{R}_{\mathrm{SBR}}+C_{\mathrm{DSL}}{C}_{\mathrm{SBR}}{L}_{\mathrm{SH}}{R}_{\mathrm{SBR}}+C_{\mathrm{DSL}}{C}_{\mathrm{SBR}}{L}_{\mathrm{SL}}{R}_{\mathrm{SBR}}+C_{\mathrm{DSL}}{C}_{\mathrm{SBR}}{L}_{\mathrm{DL}}{R}_{\mathrm{SBR}}\end{array}\right)\\ +s^2\left(\begin{array}{l}{C}_{\mathrm{DSL}}{C}_{\mathrm{SBR}}{R}_{\mathrm{C}1}{R}_{\mathrm{SBR}}+C_{\mathrm{DSL}}{C}_{\mathrm{SBR}}{R}_{\mathrm{C}2}{R}_{\mathrm{SBR}}+C_{\mathrm{DSL}}{L}_{\mathrm{DH}}+C_{\mathrm{DSL}}{L}_{\mathrm{SH}}+C_{\mathrm{SBR}}{L}_{\mathrm{DH}}+C_{\mathrm{SBR}}{L}_{\mathrm{SH}}\\ C_{\mathrm{DSL}}{L}_{\mathrm{SL}}+C_{\mathrm{DSL}}{L}_{\mathrm{DL}}\end{array}\right)\\ +s\left(C_{\mathrm{DSL}}{R}_{\mathrm{C}1}+C_{\mathrm{DSL}}{R}_{\mathrm{C}2}+C_{\mathrm{SBR}}{R}_{\mathrm{C}1}+C_{\mathrm{SBR}}{R}_{\mathrm{C}2}+C_{\mathrm{SBR}}{R}_{\mathrm{SBR}}\right)\\ +1\end{array}$$

(21)

The response of v_DSL can be analyzed from the denominator ∆ which give the rules to suppress the ringing. By choosing R_SBR and C_SBR such that all the roots of ∆(s) are real, ensures successful mitigation of oscillations in v_DSL. However, it is not a straightforward to comprehend in case of a fourth-order equation as there is a breakaway point due to the intersection of only two root loci with the real axis. Therefore, to reduce ∆(s) to a third-order polynomial equation, the drain-source inductances of high-side MOSFET are assumed negligibly small. Substitution of L_SH = L_DH = 0 in (21) and solving algebraic equations ∆(s) = 0 and d∆(s)/dt = 0 for R_SBR and C_SBR gives

$$C_{\mathrm{SBR}}=\frac{N_C\left(s\right)}{{\Delta }_C\left(s\right)} \mathrm{and} R_{\mathrm{SBR}}=\frac{N_R\left(s\right)}{{\Delta }_R\left(s\right)}$$

(22)

where the N_C(s), ∆_C(s), N_R(s) and ∆_R(s) are explicity given in (23)

$$\{\begin{array}{l}{N}_C\left(s\right)={\Delta }_R\left(s\right)={\left(s{C}_{\mathrm{DSL}}{R}_{\mathrm{C}1}+s{C}_{\mathrm{DSL}}{R}_{\mathrm{C}2}+s^2{C}_{\mathrm{DSL}}{L}_{\mathrm{SL}}+s^2{C}_{\mathrm{DSL}}{L}_{\mathrm{DL}}+1\right)}^2\\ {\Delta }_C=s^2\left(\begin{array}{l}{s}^2\left(C_{\mathrm{DSL}}^2{L}_{\mathrm{SL}}{R}_{\mathrm{C}2}^2+C_{\mathrm{DSL}}^2{L}_{\mathrm{DL}}{R}_{\mathrm{C}1}^2+C_{\mathrm{DSL}}^2{L}_{\mathrm{DL}}{R}_{\mathrm{C}2}^2+C_{\mathrm{DSL}}^2{L}_{\mathrm{SL}}{R}_{\mathrm{C}1}^2+2C_{\mathrm{DSL}}^2{L}_{\mathrm{SL}}{R}_{\mathrm{C}1}{R}_{\mathrm{C}2}+2C_{\mathrm{DSL}}^2{L}_{\mathrm{DL}}{R}_{\mathrm{C}1}{R}_{\mathrm{C}2}\right)\\ -\left(C_{\mathrm{DSL}}{R}_{\mathrm{C}2}^2+2R_{\mathrm{C}1}{R}_{\mathrm{C}2}+C_{\mathrm{DSL}}{R}_{\mathrm{C}1}^2\right)\end{array}\right)\\ N_R=-\left(R_{\mathrm{C}1}+R_{\mathrm{C}2}\right)\left(\begin{array}{l}{s}^4{C}_{\mathrm{DSL}}^2\left(L_{\mathrm{SL}}^2+L_{\mathrm{DL}}^2+2L_{\mathrm{SL}}{L}_{\mathrm{DL}}\right)+s^{3}2C_{\mathrm{DSL}}^2\left(L_{\mathrm{SL}}{R}_{\mathrm{C}1}+L_{\mathrm{SL}}{R}_{\mathrm{C}2}+L_{\mathrm{DL}}{R}_{\mathrm{C}1}+L_{\mathrm{DL}}{R}_{\mathrm{C}2}\right)\\ +s^{2}2C_{\mathrm{DSL}}\left(L_{\mathrm{SL}}+L_{\mathrm{DL}}\right)+1\end{array}\right)\end{array}$$

(23)

The final step is to draw R_SBR verses C_SBR parametric curve by sweeping the variable s in (22), which gives the boundary of the region where all the roots of ∆(s) are real. Since the solutions to ∆(s) = 0 are negative for a stable operation, the parameter s is swept on the negative real axis of the complex plane. Figure 8 shows the resulting parametric curve with the snubber components chosen in the shaded region ensures suppression of switching oscillations. In addition to dampen the voltage vibrations, the snubber must also ensure minimum power losses. Therefore, the lower part of the critically damped region is more suitable as the C_SBR significantly affects snubber losses as compared to R_SBR.

5. Results and Discussion

In this section, the proposed gate driver performance is verified using computer simulation and experimental prototype of SiC half-bridge dc-ac converter. Specifications of the converter under study are given in

Table 1. Specifications of the SiC MOSFET based half-bridge dc-ac converter.

Parameter	Value
Source voltage (VIN)	100 V
Capacitor (C)	1.5 µF
Inductor (L)	33 µH
Load Resistance (R)	10 Ω
Switching frequency (fs)	1 MHz

. To simulate the Spice model of SiC MOSFET provided by Cree Inc., LTspice software is used with a step size of 1 ns. Parameters of SiC MOSFET, i.e., C3M0120090J related to the gate driving are listed in

Table 2. Parameters of the C3M0120090J.

Parameter	Value
Threshold voltage	2.1 V
Intrinsic gate resistance	16 Ω
Maximum gate-source voltage	−8/+18
Input capacitance	350 pF
Output capacitance	40 pF
Reverse transfer capacitance	3 pF

. For reduced conduction losses, 16 V turn-on gate-source voltage is recommended. Since the proposed circuit performs level shifting, therefore, a regulated 18.4 V gate driver source is applied to set +16 V and -2.4 V, as the on and off gate driving voltages respectively. Other specifications of the gate driver components based on its transient analysis are given in

Table 3. Parameters of the proposed gate driver.

Parameter	Value
R1L	3 Ω
R2L	3 Ω
DZPL	18 V
DZNL	5 V
CZL	1 µF

.

5.1. Simulation Results

The captured switching waveforms are shown in Figure 9, where the gate-source voltages are level shifted by 2.4 V. During the turn-on process of low-side MOSFET, the v_GSL rises to 16V in 5 ns thereby forcing drain-source voltage v_DSL to fall as shown in Figure 9a. Below 50 V, the change in v_DSL is high, i.e., 15 V/ns, and induces 1.7 V in v_GSH. A similar phenomenon is observed in the turning-off waveform shown in Figure 9b. However, due to the level shifted gate-source voltages, there is no spurious turn-on.

Moreover, using LTspice simulation the effect of gate resistance on the switching operation is investigated. Figure 10a shows the turning-off gate-source waveforms under 3 Ω, 9 Ω, and 18 Ω gate resistances. SiC MOSFET based half-bridge converter is simulated using the Spice model with inductances of 7.46 nH, 1.5 nH, and 7.06 nH added to the source, drain and gate terminals of each MOSFET respectively in order to verify the theoretically analyzed effects of parasitic elements. It is observed that the increase in gate resistance slows down the transition of gate-source voltage and results in higher spurious peaks, which can also be noted from the relationship between gate resistance R_1L and gate voltage spike, shown in Figure 10b. Thus, it is significantly important to choose a relatively lower R_1L to achieve the desired level shifting and protects the MOSFET from false turn-on. On the other hand, while choosing R_2L the high intrinsic gate resistance is particularly noteworthy as spurious turn-on can occur if the voltage drop across R_1L//R_2L exceeds the gate threshold voltage. Therefore, R_2L is chosen same as R_1L to ensure the turning-off gate impedance as half of the turning-on counterpart.

Thus, it is concluded that the parasitic inductances negatively influence the switching response of SiC MOSFET, including voltage overshoot exceeding the steady-state drain-source voltage and high-frequency oscillations, thereby enlarging voltage stress and EMI noise. Moreover, since the source inductance couples the power and gate-loop, therefore, the ringing in drain-source voltage forces the gate-source voltage to oscillate accordingly.

An RC snubber circuit is used to suppress such oscillations. Figure 11 shows the simulation results of voltage ringing using different snubber combinations. Figure 11a shows that raising the R_SBR dampens the oscillations, while, the converter simulated for different C_SBR and R_SBR = 1 Ω is shown in Figure 11b, which indicates that raising C_SBR can also suppress the parasitic ringing. However, the power losses significantly increase by raising C_SBR [39]. Therefore, its minimum value is chosen for experimental implementation.

5.2. Experimental Results

Figure 12 shows the setup of a half-bridge dc-ac converter for experimental verification. An isolated driver IC (Si8234) from Silicon Labs incorporation is used, which can operate at elevated frequencies, source and sink high gate current, and show significant immunity to EMI. Since the driver circuit traces carry a high-frequency signal, therefore, they are routed on the same layer to prevent the propagation of noise to other layers. Furthermore, to ensure Equation (24) [18], the driver circuit is routed using wide (25 mil) and shortest possible traces.

$$L_{\mathrm{G}}\frac{d{i}_{\mathrm{G}}}{dt}<I_{\mathrm{R}}\frac{1}{g_{\mathrm{fs}}}10\%$$

(24)

The symbol I_R represents the rated current, g_fs is the transconductance of SiC MOSFET, and L_G is the parasitic gate inductance. Since the stray input capacitance is fixed, thereby, minimizing L_G is effective in improving the damping of gate voltage resonance. In addition, a 10 kΩ gate-source resistor is connected, which is also useful in suppressing gate voltage oscillations.

Figure 13 shows the experimental gate voltage waveform v_GSL generated using the proposed gate driver at the 1 MHz switching frequency. The driver sets the turn-on and turn-off voltage to 16.5 V and −2.4 V respectively. The −2.4 V offset in gate voltage validates the basic level shifting capability of the gate driver. Moreover, Figure 14a,b show the turn-off and turn-on transition of the low-side MOSFET, respectively. Although, the spurious spike in gate-source voltage introduced by the fast-rising v_DSL is below the gate threshold voltage, but the oscillations in v_GSL are alarming due to the higher peaks. The ringing in v_DSL due to circuit parasitics forces v_GSL to oscillate, which can cause the crosstalk as well as stressing the device by exceeding the negative gate voltage limit. Therefore, RC snubber is used to dampen the parasitic ringing and thus increase the immunity to the crosstalk phenomenon and the gate breakdown. Figure 15 shows the gate-source and drain-source voltage waveforms of low-side MOSFET for two different RC snubbers. The waveform in Figure 15a shows the measured v_DSL and v_GSL when C_SBR = 440 pF and R_SBR = 10 Ω, resulting in a voltage overshoot of 41 V and settling time of 90 ns. For measurement of Figure 15b, C_SBR has been raised to 1 nF, which reduces the voltage overshoot to 27 V and settling time to 54 ns. The results indicate that the assumption L_SH = L_DH = 0 leads to a mismatch between the experimental and mathematically derived parametric curves, and thus, the snubber selected using valley in the non-oscillatory region of Figure 8 is not viable. It is vital to choose high-valued R_SBR to improve damping rather than C_SBR to maintain relatively low power losses.

5.3. Limitations of the Proposed Gate Driver and the Snubber Design Technique

Although the proposed level shifter circuit relaxes the gate driver layout by getting rid of the additional negative voltage supply, but at the same time it relatively lowers the performance bar. The important concern is that the introduction of the capacitor C_ZL in the gate loop delays the turn-on transition of the SiC MOSFET. Moreover, v_N requires several switching cycles at the start-up to rise up to the zener voltage V_Z, and thus the negative turn-off voltage as determined by v_N gradually increases in magnitude V_Z. Finally, the negative voltage generated using the level shifter circuit is prone to parasitic oscillations, which can force gate voltage to exceed the negative limit, as a result overstressing the SiC MOSFET.

The snubber design technique presented in the paper predicts a region in the R_SBR-C_SBR plane where the switching ringing is suppressed. However, the accuracy of parasitic inductances and capacitances in the power loop determines the matching of the region derived using analytical equations with the experimental counterpart. Although, the manufacturer provides device specifications, but for computation of interconnection inductance, programs driven by the finite-element algorithm such as Maxwell 3D is required.

6. Conclusions

To improve the immunity against crosstalk phenomena, a gate driver has been proposed for SiC MOSFET capable of generating the negative turn-off voltage without using a negative power supply. Unlike the voltage divider based level shifters, the proposed circuit adds a negative offset to the gate-source voltage using reduced components with no additional resistor in the gate loop, thereby not affecting the efficiency. The effectiveness of the level shifter circuit has been validated by driving the SiC MOSFET in the half-bridge dc-ac converter at a switching frequency of 1 MHz which is 10 times higher than the RCD counterpart. Moreover, oscillation due to circuit parasitics are modeled, and guidelines for PCB layout to minimize the interconnection inductances are recommended. It is emphasized that due to unavoidable parasitic inductances, certain voltage ringing still exists which encourages passive damping. A procedure for the RC snubber design has been presented to avoid the trial and error based design. The snubber circuit has successfully lowered the gate voltage spike by 2.56 V and reduced the damping time by 63 ns.