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Sensors 2017, 17(4), 865; doi:10.3390/s17040865

A 7.4 ps FPGA-Based TDC with a 1024-Unit Measurement Matrix

1
School of Electro-Mechanical Engineering, Xidian University, Xi’an 710071, China
2
School of Aerospace Science and Technology, Xidian University, Xi’an 710071, China
*
Author to whom correspondence should be addressed.
Academic Editor: Vittorio M. N. Passaro
Received: 18 February 2017 / Revised: 10 April 2017 / Accepted: 11 April 2017 / Published: 14 April 2017
(This article belongs to the Section Physical Sensors)

Abstract

In this paper, a high-resolution time-to-digital converter (TDC) based on a field programmable gate array (FPGA) device is proposed and tested. During the implementation, a new architecture of TDC is proposed which consists of a measurement matrix with 1024 units. The utilization of routing resources as the delay elements distinguishes the proposed design from other existing designs, which contributes most to the device insensitivity to variations of temperature and voltage. Experimental results suggest that the measurement resolution is 7.4 ps, and the INL (integral nonlinearity) and DNL (differential nonlinearity) are 11.6 ps and 5.5 ps, which indicates that the proposed TDC offers high performance among the available TDCs. Benefitting from the FPGA platform, the proposed TDC has superiorities in easy implementation, low cost, and short development time. View Full-Text
Keywords: time-to-digital converter (TDC); field-programmable gate arrays (FPGA); measurement matrix; delay circuits time-to-digital converter (TDC); field-programmable gate arrays (FPGA); measurement matrix; delay circuits
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This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. (CC BY 4.0).

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Zhang, M.; Wang, H.; Liu, Y. A 7.4 ps FPGA-Based TDC with a 1024-Unit Measurement Matrix. Sensors 2017, 17, 865.

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