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Sensors 2016, 16(6), 761; doi:10.3390/s16060761

Synchronous OEIC Integrating Receiver for Optically Reconfigurable Gate Arrays

1
Institute of Electrodynamics, Microwave and Circuit Engineering, Vienna University of Technology, Gußhausstraße 25/354, Vienna 1040, Austria
2
Group of Electronic Design, Aragón Institute of Engineering Research, Universidad de Zaragoza, Pedro Cerbuna 12, Zaragoza 50009, Spain
*
Author to whom correspondence should be addressed.
Academic Editor: Vittorio M. N. Passaro
Received: 28 April 2016 / Revised: 19 May 2016 / Accepted: 20 May 2016 / Published: 25 May 2016
(This article belongs to the Section Physical Sensors)
View Full-Text   |   Download PDF [1552 KB, uploaded 25 May 2016]   |  

Abstract

A monolithically integrated optoelectronic receiver with a low-capacitance on-chip pin photodiode is presented. The receiver is fabricated in a 0.35 μm opto-CMOS process fed at 3.3 V and due to the highly effective integrated pin photodiode it operates at μW. A regenerative latch acting as a sense amplifier leads in addition to a low electrical power consumption. At 400 Mbit/s, sensitivities of −26.0 dBm and −25.5 dBm are achieved, respectively, for λ = 635 nm and λ = 675 nm (BER = 10−9 ) with an energy efficiency of 2 pJ/bit. View Full-Text
Keywords: integrated optoelectronics; integrated pin photodiode; integrating receiver integrated optoelectronics; integrated pin photodiode; integrating receiver
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This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. (CC BY 4.0).

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MDPI and ACS Style

Sánchez-Azqueta, C.; Goll, B.; Celma, S.; Zimmermann, H. Synchronous OEIC Integrating Receiver for Optically Reconfigurable Gate Arrays. Sensors 2016, 16, 761.

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