Next Article in Journal
Design and Realization of a Three Degrees of Freedom Displacement Measurement System Composed of Hall Sensors Based on Magnetic Field Fitting by an Elliptic Function
Previous Article in Journal
Carbon Nanomaterials Based Electrochemical Sensors/Biosensors for the Sensitive Detection of Pharmaceutical and Biological Compounds
Article Menu

Export Article

Open AccessArticle
Sensors 2015, 15(9), 22509-22529; doi:10.3390/s150922509

A 181 GOPS AKAZE Accelerator Employing Discrete-Time Cellular Neural Networks for Real-Time Feature Extraction

Institute of Microelectronics, Tsinghua University, Beijing 100084, China
*
Author to whom correspondence should be addressed.
Academic Editor: Leonhard M. Reindl
Received: 17 July 2015 / Revised: 20 August 2015 / Accepted: 25 August 2015 / Published: 4 September 2015
(This article belongs to the Section Sensor Networks)
View Full-Text   |   Download PDF [1934 KB, uploaded 7 September 2015]   |  

Abstract

This paper proposes a real-time feature extraction VLSI architecture for high-resolution images based on the accelerated KAZE algorithm. Firstly, a new system architecture is proposed. It increases the system throughput, provides flexibility in image resolution, and offers trade-offs between speed and scaling robustness. The architecture consists of a two-dimensional pipeline array that fully utilizes computational similarities in octaves. Secondly, a substructure (block-serial discrete-time cellular neural network) that can realize a nonlinear filter is proposed. This structure decreases the memory demand through the removal of data dependency. Thirdly, a hardware-friendly descriptor is introduced in order to overcome the hardware design bottleneck through the polar sample pattern; a simplified method to realize rotation invariance is also presented. Finally, the proposed architecture is designed in TSMC 65 nm CMOS technology. The experimental results show a performance of 127 fps in full HD resolution at 200 MHz frequency. The peak performance reaches 181 GOPS and the throughput is double the speed of other state-of-the-art architectures. View Full-Text
Keywords: AKAZE; binary feature descriptor; feature extraction; hardware architecture; VLSI implementation AKAZE; binary feature descriptor; feature extraction; hardware architecture; VLSI implementation
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. (CC BY 4.0).

Scifeed alert for new publications

Never miss any articles matching your research from any publisher
  • Get alerts for new papers matching your research
  • Find out the new papers from selected authors
  • Updated daily for 49'000+ journals and 6000+ publishers
  • Define your Scifeed now

SciFeed Share & Cite This Article

MDPI and ACS Style

Jiang, G.; Liu, L.; Zhu, W.; Yin, S.; Wei, S. A 181 GOPS AKAZE Accelerator Employing Discrete-Time Cellular Neural Networks for Real-Time Feature Extraction. Sensors 2015, 15, 22509-22529.

Show more citation formats Show less citations formats

Related Articles

Article Metrics

Article Access Statistics

1

Comments

[Return to top]
Sensors EISSN 1424-8220 Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert
Back to Top