Sensors 2013, 13(12), 16829-16850; doi:10.3390/s131216829
Article

Design Methodology of an Equalizer for Unipolar Non Return to Zero Binary Signals in the Presence of Additive White Gaussian Noise Using a Time Delay Neural Network on a Field Programmable Gate Array

Institute for Technological Development and Innovation in Communications, University of Las Palmas de Gran Canaria, Las Palmas de Gran Canaria 35017, Spain
* Author to whom correspondence should be addressed.
Received: 31 October 2013; in revised form: 29 November 2013 / Accepted: 29 November 2013 / Published: 6 December 2013
(This article belongs to the Special Issue State-of-the-Art Sensors Technology in Spain 2013)
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Abstract: This article presents a design methodology for designing an artificial neural network as an equalizer for a binary signal. Firstly, the system is modelled in floating point format using Matlab. Afterward, the design is described for a Field Programmable Gate Array (FPGA) using fixed point format. The FPGA design is based on the System Generator from Xilinx, which is a design tool over Simulink of Matlab. System Generator allows one to design in a fast and flexible way. It uses low level details of the circuits and the functionality of the system can be fully tested. System Generator can be used to check the architecture and to analyse the effect of the number of bits on the system performance. Finally the System Generator design is compiled for the Xilinx Integrated System Environment (ISE) and the system is described using a hardware description language. In ISE the circuits are managed with high level details and physical performances are obtained. In the Conclusions section, some modifications are proposed to improve the methodology and to ensure portability across FPGA manufacturers.
Keywords: equalizer; AWGN; neural network; FPGA; floating point; fixed point; Matlab; Simulink; System Generator; ISE

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MDPI and ACS Style

Suárez, S.T.P.; González, C.M.T.; Hernández, J.B.A. Design Methodology of an Equalizer for Unipolar Non Return to Zero Binary Signals in the Presence of Additive White Gaussian Noise Using a Time Delay Neural Network on a Field Programmable Gate Array. Sensors 2013, 13, 16829-16850.

AMA Style

Suárez STP, González CMT, Hernández JBA. Design Methodology of an Equalizer for Unipolar Non Return to Zero Binary Signals in the Presence of Additive White Gaussian Noise Using a Time Delay Neural Network on a Field Programmable Gate Array. Sensors. 2013; 13(12):16829-16850.

Chicago/Turabian Style

Suárez, Santiago T.P.; González, Carlos M.T.; Hernández, Jesús B.A. 2013. "Design Methodology of an Equalizer for Unipolar Non Return to Zero Binary Signals in the Presence of Additive White Gaussian Noise Using a Time Delay Neural Network on a Field Programmable Gate Array." Sensors 13, no. 12: 16829-16850.

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