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Sensors 2012, 12(9), 11661-11683; doi:10.3390/s120911661

Efficient k-Winner-Take-All Competitive Learning Hardware Architecture for On-Chip Learning

1
Department of Electronic Engineering, Ching Yun University, Jhongli 320, Taiwan
2
Department of Computer Science and Information Engineering, National Taiwan Normal University, Taipei 116, Taiwan
*
Author to whom correspondence should be addressed.
Received: 2 July 2012 / Revised: 14 August 2012 / Accepted: 15 August 2012 / Published: 27 August 2012
(This article belongs to the Section Physical Sensors)
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Abstract

A novel k-winners-take-all (k-WTA) competitive learning (CL) hardware architecture is presented for on-chip learning in this paper. The architecture is based on an efficient pipeline allowing k-WTA competition processes associated with different training vectors to be performed concurrently. The pipeline architecture employs a novel codeword swapping scheme so that neurons failing the competition for a training vector are immediately available for the competitions for the subsequent training vectors. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for realtime on-chip learning. Experimental results show that the SOPC has significantly lower training time than that of other k-WTA CL counterparts operating with or without hardware support. View Full-Text
Keywords: reconfigurable computing; system on programmable chip; FPGA; competitive learning; k-winners-take-all reconfigurable computing; system on programmable chip; FPGA; competitive learning; k-winners-take-all
This is an open access article distributed under the Creative Commons Attribution License (CC BY 3.0).

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MDPI and ACS Style

Ou, C.-M.; Li, H.-Y.; Hwang, W.-J. Efficient k-Winner-Take-All Competitive Learning Hardware Architecture for On-Chip Learning. Sensors 2012, 12, 11661-11683.

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