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Column-Parallel Correlated Multiple Sampling Circuits for CMOS Image Sensors and Their Noise Reduction Effects
Research of Institute, Shizuoka University, 3-5-1 Johoku Nakaku Hmamatsu, Shizuoka, Japan
Brookman Technology Inc., 3-1-7 Wajiyama Nakaku Hmamatsu, Shizuoka, Japan
* Author to whom correspondence should be addressed.
Received: 21 July 2010; in revised form: 3 September 2010 / Accepted: 27 September 2010 / Published: 12 October 2010
Abstract: For low-noise complementary metal-oxide-semiconductor (CMOS) image sensors, the reduction of pixel source follower noises is becoming very important. Column-parallel high-gain readout circuits are useful for low-noise CMOS image sensors. This paper presents column-parallel high-gain signal readout circuits, correlated multiple sampling (CMS) circuits and their noise reduction effects. In the CMS, the gain of the noise cancelling is controlled by the number of samplings. It has a similar effect to that of an amplified CDS for the thermal noise but is a little more effective for 1/f and RTS noises. Two types of the CMS with simple integration and folding integration are proposed. In the folding integration, the output signal swing is suppressed by a negative feedback using a comparator and one-bit D-to-A converter. The CMS circuit using the folding integration technique allows to realize a very low-noise level while maintaining a wide dynamic range. The noise reduction effects of their circuits have been investigated with a noise analysis and an implementation of a 1Mpixel pinned photodiode CMOS image sensor. Using 16 samplings, dynamic range of 59.4 dB and noise level of 1.9 e- for the simple integration CMS and 75 dB and 2.2 e- for the folding integration CMS, respectively, are obtained.
Keywords: CMOS image sensor; low noise; wide dynamic range; column-parallel correlated multiple sampling; folding integration technique
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Cite This Article
MDPI and ACS Style
Suh, S.; Itoh, S.; Aoyama, S.; Kawahito, S. Column-Parallel Correlated Multiple Sampling Circuits for CMOS Image Sensors and Their Noise Reduction Effects. Sensors 2010, 10, 9139-9154.
Suh S, Itoh S, Aoyama S, Kawahito S. Column-Parallel Correlated Multiple Sampling Circuits for CMOS Image Sensors and Their Noise Reduction Effects. Sensors. 2010; 10(10):9139-9154.
Suh, Sungho; Itoh, Shinya; Aoyama, Satoshi; Kawahito, Shoji. 2010. "Column-Parallel Correlated Multiple Sampling Circuits for CMOS Image Sensors and Their Noise Reduction Effects." Sensors 10, no. 10: 9139-9154.